1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2018/12/23 Bernard The first version 9*10465441SEvalZero * 2018/12/27 Jesven Add secondary cpu boot 10*10465441SEvalZero */ 11*10465441SEvalZero 12*10465441SEvalZero #include <rthw.h> 13*10465441SEvalZero #include <rtthread.h> 14*10465441SEvalZero #include <stdint.h> 15*10465441SEvalZero 16*10465441SEvalZero #include "board.h" 17*10465441SEvalZero #include <encoding.h> 18*10465441SEvalZero #include <clint.h> 19*10465441SEvalZero #include <atomic.h> 20*10465441SEvalZero 21*10465441SEvalZero #ifdef RT_USING_SMP 22*10465441SEvalZero rt_hw_cpu_id(void)23*10465441SEvalZeroint rt_hw_cpu_id(void) 24*10465441SEvalZero { 25*10465441SEvalZero return read_csr(mhartid); 26*10465441SEvalZero } 27*10465441SEvalZero rt_hw_spin_lock(rt_hw_spinlock_t * lock)28*10465441SEvalZerovoid rt_hw_spin_lock(rt_hw_spinlock_t *lock) 29*10465441SEvalZero { 30*10465441SEvalZero spinlock_lock((spinlock_t *)lock); 31*10465441SEvalZero } 32*10465441SEvalZero rt_hw_spin_unlock(rt_hw_spinlock_t * lock)33*10465441SEvalZerovoid rt_hw_spin_unlock(rt_hw_spinlock_t *lock) 34*10465441SEvalZero { 35*10465441SEvalZero spinlock_unlock((spinlock_t *)lock); 36*10465441SEvalZero } 37*10465441SEvalZero rt_hw_ipi_send(int ipi_vector,unsigned int cpu_mask)38*10465441SEvalZerovoid rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) 39*10465441SEvalZero { 40*10465441SEvalZero int idx; 41*10465441SEvalZero 42*10465441SEvalZero for (idx = 0; idx < RT_CPUS_NR; idx ++) 43*10465441SEvalZero { 44*10465441SEvalZero if (cpu_mask & (1 << idx)) 45*10465441SEvalZero { 46*10465441SEvalZero clint_ipi_send(idx); 47*10465441SEvalZero } 48*10465441SEvalZero } 49*10465441SEvalZero } 50*10465441SEvalZero 51*10465441SEvalZero extern rt_base_t secondary_boot_flag; rt_hw_secondary_cpu_up(void)52*10465441SEvalZerovoid rt_hw_secondary_cpu_up(void) 53*10465441SEvalZero { 54*10465441SEvalZero mb(); 55*10465441SEvalZero secondary_boot_flag = 0xa55a; 56*10465441SEvalZero } 57*10465441SEvalZero 58*10465441SEvalZero extern void rt_hw_scondary_interrupt_init(void); 59*10465441SEvalZero extern int rt_hw_tick_init(void); 60*10465441SEvalZero extern int rt_hw_clint_ipi_enable(void); 61*10465441SEvalZero secondary_cpu_c_start(void)62*10465441SEvalZerovoid secondary_cpu_c_start(void) 63*10465441SEvalZero { 64*10465441SEvalZero rt_hw_spin_lock(&_cpus_lock); 65*10465441SEvalZero 66*10465441SEvalZero /* initialize interrupt controller */ 67*10465441SEvalZero rt_hw_scondary_interrupt_init(); 68*10465441SEvalZero 69*10465441SEvalZero rt_hw_tick_init(); 70*10465441SEvalZero 71*10465441SEvalZero rt_hw_clint_ipi_enable(); 72*10465441SEvalZero 73*10465441SEvalZero rt_system_scheduler_start(); 74*10465441SEvalZero } 75*10465441SEvalZero rt_hw_secondary_cpu_idle_exec(void)76*10465441SEvalZerovoid rt_hw_secondary_cpu_idle_exec(void) 77*10465441SEvalZero { 78*10465441SEvalZero asm volatile ("wfi"); 79*10465441SEvalZero } 80*10465441SEvalZero #endif /*RT_USING_SMP*/ 81