1*10465441SEvalZero #ifndef __IO_H__
2*10465441SEvalZero #define __IO_H__
3*10465441SEvalZero
4*10465441SEvalZero #define __iomem
5*10465441SEvalZero
6*10465441SEvalZero /*
7*10465441SEvalZero * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
8*10465441SEvalZero *
9*10465441SEvalZero * Read operations have additional twi & isync to make sure the read
10*10465441SEvalZero * is actually performed (i.e. the data has come back) before we start
11*10465441SEvalZero * executing any following instructions.
12*10465441SEvalZero */
in_8(const volatile unsigned char __iomem * addr)13*10465441SEvalZero static inline int in_8(const volatile unsigned char __iomem *addr)
14*10465441SEvalZero {
15*10465441SEvalZero int ret;
16*10465441SEvalZero
17*10465441SEvalZero __asm__ __volatile__(
18*10465441SEvalZero "sync; lbz%U1%X1 %0,%1;\n"
19*10465441SEvalZero "twi 0,%0,0;\n"
20*10465441SEvalZero "isync" : "=r" (ret) : "m" (*addr));
21*10465441SEvalZero return ret;
22*10465441SEvalZero }
23*10465441SEvalZero
out_8(volatile unsigned char __iomem * addr,int val)24*10465441SEvalZero static inline void out_8(volatile unsigned char __iomem *addr, int val)
25*10465441SEvalZero {
26*10465441SEvalZero __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
27*10465441SEvalZero }
28*10465441SEvalZero
in_le16(const volatile unsigned short __iomem * addr)29*10465441SEvalZero extern inline int in_le16(const volatile unsigned short __iomem *addr)
30*10465441SEvalZero {
31*10465441SEvalZero int ret;
32*10465441SEvalZero
33*10465441SEvalZero __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
34*10465441SEvalZero "twi 0,%0,0;\n"
35*10465441SEvalZero "isync" : "=r" (ret) :
36*10465441SEvalZero "r" (addr), "m" (*addr));
37*10465441SEvalZero return ret;
38*10465441SEvalZero }
39*10465441SEvalZero
in_be16(const volatile unsigned short __iomem * addr)40*10465441SEvalZero extern inline int in_be16(const volatile unsigned short __iomem *addr)
41*10465441SEvalZero {
42*10465441SEvalZero int ret;
43*10465441SEvalZero
44*10465441SEvalZero __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
45*10465441SEvalZero "twi 0,%0,0;\n"
46*10465441SEvalZero "isync" : "=r" (ret) : "m" (*addr));
47*10465441SEvalZero return ret;
48*10465441SEvalZero }
49*10465441SEvalZero
out_le16(volatile unsigned short __iomem * addr,int val)50*10465441SEvalZero extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
51*10465441SEvalZero {
52*10465441SEvalZero __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
53*10465441SEvalZero "r" (val), "r" (addr));
54*10465441SEvalZero }
55*10465441SEvalZero
out_be16(volatile unsigned short __iomem * addr,int val)56*10465441SEvalZero extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
57*10465441SEvalZero {
58*10465441SEvalZero __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
59*10465441SEvalZero }
60*10465441SEvalZero
in_le32(const volatile unsigned __iomem * addr)61*10465441SEvalZero extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
62*10465441SEvalZero {
63*10465441SEvalZero unsigned ret;
64*10465441SEvalZero
65*10465441SEvalZero __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
66*10465441SEvalZero "twi 0,%0,0;\n"
67*10465441SEvalZero "isync" : "=r" (ret) :
68*10465441SEvalZero "r" (addr), "m" (*addr));
69*10465441SEvalZero return ret;
70*10465441SEvalZero }
71*10465441SEvalZero
in_be32(const volatile unsigned __iomem * addr)72*10465441SEvalZero extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
73*10465441SEvalZero {
74*10465441SEvalZero unsigned ret;
75*10465441SEvalZero
76*10465441SEvalZero __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
77*10465441SEvalZero "twi 0,%0,0;\n"
78*10465441SEvalZero "isync" : "=r" (ret) : "m" (*addr));
79*10465441SEvalZero return ret;
80*10465441SEvalZero }
81*10465441SEvalZero
out_le32(volatile unsigned __iomem * addr,int val)82*10465441SEvalZero extern inline void out_le32(volatile unsigned __iomem *addr, int val)
83*10465441SEvalZero {
84*10465441SEvalZero __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
85*10465441SEvalZero "r" (val), "r" (addr));
86*10465441SEvalZero }
87*10465441SEvalZero
out_be32(volatile unsigned __iomem * addr,int val)88*10465441SEvalZero extern inline void out_be32(volatile unsigned __iomem *addr, int val)
89*10465441SEvalZero {
90*10465441SEvalZero __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
91*10465441SEvalZero }
92*10465441SEvalZero
93*10465441SEvalZero #endif
94