1*10465441SEvalZero #ifndef _PPC4xx_UIC_H_ 2*10465441SEvalZero #define _PPC4xx_UIC_H_ 3*10465441SEvalZero 4*10465441SEvalZero /* 5*10465441SEvalZero * Define the number of UIC's 6*10465441SEvalZero */ 7*10465441SEvalZero #define UIC_MAX 1 8*10465441SEvalZero #define IRQ_MAX UIC_MAX * 32 9*10465441SEvalZero 10*10465441SEvalZero /* UIC0 dcr base address */ 11*10465441SEvalZero #define UIC0_DCR_BASE 0xc0 12*10465441SEvalZero 13*10465441SEvalZero /* 14*10465441SEvalZero * UIC register 15*10465441SEvalZero */ 16*10465441SEvalZero #define UIC_SR 0x0 /* UIC status */ 17*10465441SEvalZero #define UIC_ER 0x2 /* UIC enable */ 18*10465441SEvalZero #define UIC_CR 0x3 /* UIC critical */ 19*10465441SEvalZero #define UIC_PR 0x4 /* UIC polarity */ 20*10465441SEvalZero #define UIC_TR 0x5 /* UIC triggering */ 21*10465441SEvalZero #define UIC_MSR 0x6 /* UIC masked status */ 22*10465441SEvalZero #define UIC_VR 0x7 /* UIC vector */ 23*10465441SEvalZero #define UIC_VCR 0x8 /* UIC vector configuration */ 24*10465441SEvalZero 25*10465441SEvalZero #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ 26*10465441SEvalZero #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ 27*10465441SEvalZero #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ 28*10465441SEvalZero #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ 29*10465441SEvalZero #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ 30*10465441SEvalZero #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ 31*10465441SEvalZero #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ 32*10465441SEvalZero #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ 33*10465441SEvalZero 34*10465441SEvalZero /* The following is for compatibility with 405 code */ 35*10465441SEvalZero #define uicsr uic0sr 36*10465441SEvalZero #define uicer uic0er 37*10465441SEvalZero #define uiccr uic0cr 38*10465441SEvalZero #define uicpr uic0pr 39*10465441SEvalZero #define uictr uic0tr 40*10465441SEvalZero #define uicmsr uic0msr 41*10465441SEvalZero #define uicvr uic0vr 42*10465441SEvalZero #define uicvcr uic0vcr 43*10465441SEvalZero 44*10465441SEvalZero /* the interrupt vector definitions */ 45*10465441SEvalZero #define VECNUM_MAL_SERR 10 46*10465441SEvalZero #define VECNUM_MAL_TXEOB 11 47*10465441SEvalZero #define VECNUM_MAL_RXEOB 12 48*10465441SEvalZero #define VECNUM_MAL_TXDE 13 49*10465441SEvalZero #define VECNUM_MAL_RXDE 14 50*10465441SEvalZero #define VECNUM_ETH0 15 51*10465441SEvalZero #define VECNUM_ETH1_OFFS 2 52*10465441SEvalZero #define VECNUM_EIRQ6 29 53*10465441SEvalZero 54*10465441SEvalZero /* 55*10465441SEvalZero * Mask definitions (used for example in 4xx_enet.c) 56*10465441SEvalZero */ 57*10465441SEvalZero #define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) 58*10465441SEvalZero /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ 59*10465441SEvalZero #define UIC_NR(vec) ((vec) >> 5) 60*10465441SEvalZero 61*10465441SEvalZero #endif /* _PPC4xx_UIC_H_ */ 62