1*10465441SEvalZero/* 2*10465441SEvalZero * File : mips_cache_gcc.S 3*10465441SEvalZero * This file is part of RT-Thread RTOS 4*10465441SEvalZero * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5*10465441SEvalZero * 6*10465441SEvalZero * This program is free software; you can redistribute it and/or modify 7*10465441SEvalZero * it under the terms of the GNU General Public License as published by 8*10465441SEvalZero * the Free Software Foundation; either version 2 of the License, or 9*10465441SEvalZero * (at your option) any later version. 10*10465441SEvalZero * 11*10465441SEvalZero * This program is distributed in the hope that it will be useful, 12*10465441SEvalZero * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*10465441SEvalZero * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*10465441SEvalZero * GNU General Public License for more details. 15*10465441SEvalZero * 16*10465441SEvalZero * You should have received a copy of the GNU General Public License along 17*10465441SEvalZero * with this program; if not, write to the Free Software Foundation, Inc., 18*10465441SEvalZero * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19*10465441SEvalZero * 20*10465441SEvalZero * Change Logs: 21*10465441SEvalZero * Date Author Notes 22*10465441SEvalZero * 2016��9��19�� Urey the first version 23*10465441SEvalZero */ 24*10465441SEvalZero 25*10465441SEvalZero#ifndef __ASSEMBLY__ 26*10465441SEvalZero# define __ASSEMBLY__ 27*10465441SEvalZero#endif 28*10465441SEvalZero 29*10465441SEvalZero#include "../common/mips.h" 30*10465441SEvalZero 31*10465441SEvalZero .text 32*10465441SEvalZero .set noreorder 33*10465441SEvalZero 34*10465441SEvalZero .globl cache_init 35*10465441SEvalZero .ent cache_init 36*10465441SEvalZerocache_init: 37*10465441SEvalZero .set noreorder 38*10465441SEvalZero mtc0 zero, CP0_TAGLO 39*10465441SEvalZero move t0, a0 // cache total size 40*10465441SEvalZero move t1, a1 // cache line size 41*10465441SEvalZero li t2, 0x80000000 42*10465441SEvalZero addu t3, t0, t2 43*10465441SEvalZero 44*10465441SEvalZero_cache_init_loop: 45*10465441SEvalZero cache 8, 0(t2) // icache_index_store_tag 46*10465441SEvalZero cache 9, 0(t2) // dcache_index_store_tag 47*10465441SEvalZero addu t2, t1 48*10465441SEvalZero bne t2, t3, _cache_init_loop 49*10465441SEvalZero nop 50*10465441SEvalZero 51*10465441SEvalZero mfc0 t0, CP0_CONFIG 52*10465441SEvalZero li t1, 0x7 53*10465441SEvalZero not t1 54*10465441SEvalZero and t0, t0, t1 55*10465441SEvalZero or t0, 0x3 // cacheable, noncoherent, write-back, write allocate 56*10465441SEvalZero mtc0 t0, CP0_CONFIG 57*10465441SEvalZero 58*10465441SEvalZero jr ra 59*10465441SEvalZero nop 60*10465441SEvalZero 61*10465441SEvalZero .set reorder 62*10465441SEvalZero .end cache_init 63