1*10465441SEvalZero /*********************************************************************
2*10465441SEvalZero *
3*10465441SEvalZero * Generic Exception Handler
4*10465441SEvalZero *
5*10465441SEvalZero *********************************************************************
6*10465441SEvalZero * FileName: exceptions.c
7*10465441SEvalZero * Dependencies:
8*10465441SEvalZero *
9*10465441SEvalZero * Processor: PIC32
10*10465441SEvalZero *
11*10465441SEvalZero * Complier: MPLAB C32
12*10465441SEvalZero * MPLAB IDE
13*10465441SEvalZero * Company: Microchip Technology, Inc.
14*10465441SEvalZero * Author: Darren Wenn
15*10465441SEvalZero *
16*10465441SEvalZero * Software License Agreement
17*10465441SEvalZero *
18*10465441SEvalZero * The software supplied herewith by Microchip Technology Incorporated
19*10465441SEvalZero * (the �Company�) for its PIC32/PIC24 Microcontroller is intended
20*10465441SEvalZero * and supplied to you, the Company�s customer, for use solely and
21*10465441SEvalZero * exclusively on Microchip PIC32/PIC24 Microcontroller products.
22*10465441SEvalZero * The software is owned by the Company and/or its supplier, and is
23*10465441SEvalZero * protected under applicable copyright laws. All rights are reserved.
24*10465441SEvalZero * Any use in violation of the foregoing restrictions may subject the
25*10465441SEvalZero * user to criminal sanctions under applicable laws, as well as to
26*10465441SEvalZero * civil liability for the breach of the terms and conditions of this
27*10465441SEvalZero * license.
28*10465441SEvalZero *
29*10465441SEvalZero * THIS SOFTWARE IS PROVIDED IN AN �AS IS� CONDITION. NO WARRANTIES,
30*10465441SEvalZero * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
31*10465441SEvalZero * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
32*10465441SEvalZero * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
33*10465441SEvalZero * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR
34*10465441SEvalZero * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
35*10465441SEvalZero *
36*10465441SEvalZero *
37*10465441SEvalZero *
38*10465441SEvalZero ********************************************************************/
39*10465441SEvalZero
40*10465441SEvalZero #include <p32xxxx.h>
41*10465441SEvalZero
42*10465441SEvalZero // declared static in case exception condition would prevent
43*10465441SEvalZero // auto variable being created
44*10465441SEvalZero static enum {
45*10465441SEvalZero EXCEP_IRQ = 0, // interrupt
46*10465441SEvalZero EXCEP_AdEL = 4, // address error exception (load or ifetch)
47*10465441SEvalZero EXCEP_AdES, // address error exception (store)
48*10465441SEvalZero EXCEP_IBE, // bus error (ifetch)
49*10465441SEvalZero EXCEP_DBE, // bus error (load/store)
50*10465441SEvalZero EXCEP_Sys, // syscall
51*10465441SEvalZero EXCEP_Bp, // breakpoint
52*10465441SEvalZero EXCEP_RI, // reserved instruction
53*10465441SEvalZero EXCEP_CpU, // coprocessor unusable
54*10465441SEvalZero EXCEP_Overflow, // arithmetic overflow
55*10465441SEvalZero EXCEP_Trap, // trap (possible divide by zero)
56*10465441SEvalZero EXCEP_IS1 = 16, // implementation specfic 1
57*10465441SEvalZero EXCEP_CEU, // CorExtend Unuseable
58*10465441SEvalZero EXCEP_C2E // coprocessor 2
59*10465441SEvalZero } _excep_code;
60*10465441SEvalZero
61*10465441SEvalZero static unsigned int _epc_code;
62*10465441SEvalZero static unsigned int _excep_addr;
63*10465441SEvalZero
64*10465441SEvalZero #include <rtthread.h>
65*10465441SEvalZero // this function overrides the normal _weak_ generic handler
_general_exception_handler(void)66*10465441SEvalZero void _general_exception_handler(void)
67*10465441SEvalZero {
68*10465441SEvalZero asm volatile("mfc0 %0,$13" : "=r" (_excep_code));
69*10465441SEvalZero asm volatile("mfc0 %0,$14" : "=r" (_excep_addr));
70*10465441SEvalZero
71*10465441SEvalZero _excep_code = (_excep_code & 0x0000007C) >> 2;
72*10465441SEvalZero
73*10465441SEvalZero rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
74*10465441SEvalZero rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
75*10465441SEvalZero switch(_excep_code)
76*10465441SEvalZero {
77*10465441SEvalZero case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
78*10465441SEvalZero case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
79*10465441SEvalZero case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
80*10465441SEvalZero case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
81*10465441SEvalZero case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
82*10465441SEvalZero case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
83*10465441SEvalZero case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
84*10465441SEvalZero case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
85*10465441SEvalZero case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
86*10465441SEvalZero case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
87*10465441SEvalZero case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
88*10465441SEvalZero case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
89*10465441SEvalZero case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
90*10465441SEvalZero case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
91*10465441SEvalZero default : rt_kprintf("unkown exception\r\n");break;
92*10465441SEvalZero }
93*10465441SEvalZero
94*10465441SEvalZero while (1) {
95*10465441SEvalZero // Examine _excep_code to identify the type of exception
96*10465441SEvalZero // Examine _excep_addr to find the address that caused the exception
97*10465441SEvalZero }
98*10465441SEvalZero }
99