1*10465441SEvalZero 2*10465441SEvalZero #ifndef __OPENLOONGSON_SDRAM_CFG_H 3*10465441SEvalZero #define __OPENLOONGSON_SDRAM_CFG_H 4*10465441SEvalZero 5*10465441SEvalZero 6*10465441SEvalZero //#define SD_FREQ (6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM) 7*10465441SEvalZero #define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM) 8*10465441SEvalZero 9*10465441SEvalZero 10*10465441SEvalZero /* 颗粒行数 */ 11*10465441SEvalZero #define ROW_1K 0x7 12*10465441SEvalZero #define ROW_2K 0x0 13*10465441SEvalZero #define ROW_4K 0x1 14*10465441SEvalZero #define ROW_8K 0x2 15*10465441SEvalZero #define ROW_16K 0x3 16*10465441SEvalZero /* 颗粒列数 */ 17*10465441SEvalZero #define COL_256 0x7 18*10465441SEvalZero #define COL_512 0x0 19*10465441SEvalZero #define COL_1K 0x1 20*10465441SEvalZero #define COL_2K 0x2 21*10465441SEvalZero #define COL_4K 0x3 22*10465441SEvalZero /* 颗粒位宽 */ 23*10465441SEvalZero #define WIDTH_8 0x0 24*10465441SEvalZero #define WIDTH_16 0x1 25*10465441SEvalZero #define WIDTH_32 0x2 26*10465441SEvalZero 27*10465441SEvalZero #define TRCD 3 28*10465441SEvalZero #define TCL 3 29*10465441SEvalZero #define TRP 3 30*10465441SEvalZero #define TRFC 8 31*10465441SEvalZero #define TRAS 6 32*10465441SEvalZero #define TREF 0x818 33*10465441SEvalZero #define TWR 2 34*10465441SEvalZero 35*10465441SEvalZero #define DEF_SEL 0x1 36*10465441SEvalZero #define DEF_SEL_N 0x0 37*10465441SEvalZero #define HANG_UP 0x1 38*10465441SEvalZero #define HANG_UP_N 0x0 39*10465441SEvalZero #define CFG_VALID 0x1 40*10465441SEvalZero 41*10465441SEvalZero 42*10465441SEvalZero #if 0 43*10465441SEvalZero // 白菜板8MB 44*10465441SEvalZero /* 45*10465441SEvalZero 以型号为IS42S16400的SDRAM为例, 46*10465441SEvalZero 物理参数为, 47*10465441SEvalZero 容量:8MB 48*10465441SEvalZero 位宽:16位 49*10465441SEvalZero 列宽:8位,即2的8次方,即256 50*10465441SEvalZero 行宽:12位,即2的12次方,即4K 51*10465441SEvalZero 52*10465441SEvalZero 所以, 53*10465441SEvalZero 颗粒的位宽=WIDTH_16 54*10465441SEvalZero 颗粒的列数=COL_256 55*10465441SEvalZero 颗粒的行数=ROW_4K 56*10465441SEvalZero 57*10465441SEvalZero 再结合宏SD_PARA0和芯片手册中寄存器SD_CONFIG,相信一看就能明白 58*10465441SEvalZero 替换宏SD_PARA0中的行宽、列宽和位宽 59*10465441SEvalZero */ 60*10465441SEvalZero #define SDRAM_WIDTH (WIDTH_16) 61*10465441SEvalZero #define SDRAM_COL (COL_256) 62*10465441SEvalZero #define SDRAM_ROW (ROW_4K) 63*10465441SEvalZero 64*10465441SEvalZero #else 65*10465441SEvalZero 66*10465441SEvalZero // 智龙32MByte 67*10465441SEvalZero #define SDRAM_WIDTH (WIDTH_16) 68*10465441SEvalZero #define SDRAM_COL (COL_512) 69*10465441SEvalZero #define SDRAM_ROW (ROW_8K) 70*10465441SEvalZero 71*10465441SEvalZero #endif 72*10465441SEvalZero 73*10465441SEvalZero #define SD_PARA0 (0x7f<<25 | \ 74*10465441SEvalZero (TRAS << 21) | \ 75*10465441SEvalZero (TRFC << 17) | (TRP << 14) | (TCL << 11) | \ 76*10465441SEvalZero (TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \ 77*10465441SEvalZero SDRAM_ROW) 78*10465441SEvalZero 79*10465441SEvalZero #define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) 80*10465441SEvalZero 81*10465441SEvalZero #define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \ 82*10465441SEvalZero (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) 83*10465441SEvalZero 84*10465441SEvalZero 85*10465441SEvalZero #endif 86