xref: /nrf52832-nimble/rt-thread/libcpu/mips/loongson_1c/cache.h (revision 104654410c56c573564690304ae786df310c91fc)
1*10465441SEvalZero /*
2*10465441SEvalZero  * File      : cache.h
3*10465441SEvalZero  * This file is part of RT-Thread RTOS
4*10465441SEvalZero  * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
5*10465441SEvalZero  *
6*10465441SEvalZero  * The license and distribution terms for this file may be
7*10465441SEvalZero  * found in the file LICENSE in this distribution or at
8*10465441SEvalZero  * http://www.rt-thread.org/license/LICENSE
9*10465441SEvalZero  *
10*10465441SEvalZero  * Change Logs:
11*10465441SEvalZero  * Date           Author       Notes
12*10465441SEvalZero  * 2010-07-09     Bernard      first version
13*10465441SEvalZero  * 2011-08-08     lgnq         modified for LS1B
14*10465441SEvalZero  */
15*10465441SEvalZero #ifndef	__CACHE_H__
16*10465441SEvalZero #define	__CACHE_H__
17*10465441SEvalZero 
18*10465441SEvalZero /*
19*10465441SEvalZero  * Cache Operations
20*10465441SEvalZero  */
21*10465441SEvalZero #define Index_Invalidate_I      0x00
22*10465441SEvalZero #define Index_Writeback_Inv_D   0x01
23*10465441SEvalZero #define Index_Invalidate_SI     0x02
24*10465441SEvalZero #define Index_Writeback_Inv_SD  0x03
25*10465441SEvalZero #define Index_Load_Tag_I		0x04
26*10465441SEvalZero #define Index_Load_Tag_D		0x05
27*10465441SEvalZero #define Index_Load_Tag_SI		0x06
28*10465441SEvalZero #define Index_Load_Tag_SD		0x07
29*10465441SEvalZero #define Index_Store_Tag_I		0x08
30*10465441SEvalZero #define Index_Store_Tag_D		0x09
31*10465441SEvalZero #define Index_Store_Tag_SI		0x0A
32*10465441SEvalZero #define Index_Store_Tag_SD		0x0B
33*10465441SEvalZero #define Create_Dirty_Excl_D		0x0d
34*10465441SEvalZero #define Create_Dirty_Excl_SD	0x0f
35*10465441SEvalZero #define Hit_Invalidate_I		0x10
36*10465441SEvalZero #define Hit_Invalidate_D		0x11
37*10465441SEvalZero #define Hit_Invalidate_SI		0x12
38*10465441SEvalZero #define Hit_Invalidate_SD		0x13
39*10465441SEvalZero #define Fill					0x14
40*10465441SEvalZero #define Hit_Writeback_Inv_D		0x15
41*10465441SEvalZero /* 0x16 is unused */
42*10465441SEvalZero #define Hit_Writeback_Inv_SD	0x17
43*10465441SEvalZero #define Hit_Writeback_I			0x18
44*10465441SEvalZero #define Hit_Writeback_D			0x19
45*10465441SEvalZero /* 0x1a is unused */
46*10465441SEvalZero #define Hit_Writeback_SD		0x1b
47*10465441SEvalZero /* 0x1c is unused */
48*10465441SEvalZero /* 0x1e is unused */
49*10465441SEvalZero #define Hit_Set_Virtual_SI		0x1e
50*10465441SEvalZero #define Hit_Set_Virtual_SD		0x1f
51*10465441SEvalZero 
52*10465441SEvalZero #endif
53