1*10465441SEvalZero/* 2*10465441SEvalZero * File : start_gcc.S 3*10465441SEvalZero * This file is part of RT-Thread RTOS 4*10465441SEvalZero * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team 5*10465441SEvalZero * 6*10465441SEvalZero * The license and distribution terms for this file may be 7*10465441SEvalZero * found in the file LICENSE in this distribution or at 8*10465441SEvalZero * http://www.rt-thread.org/license/LICENSE 9*10465441SEvalZero * 10*10465441SEvalZero * Change Logs: 11*10465441SEvalZero * Date Author Notes 12*10465441SEvalZero * 2010-05-17 swkyer first version 13*10465441SEvalZero * 2010-09-04 bernard porting to Jz47xx 14*10465441SEvalZero */ 15*10465441SEvalZero 16*10465441SEvalZero#include "../common/mips.inc" 17*10465441SEvalZero#include "../common/stackframe.h" 18*10465441SEvalZero 19*10465441SEvalZero .section ".start", "ax" 20*10465441SEvalZero .set noreorder 21*10465441SEvalZero 22*10465441SEvalZero /* the program entry */ 23*10465441SEvalZero .globl _start 24*10465441SEvalZero_start: 25*10465441SEvalZero .set noreorder 26*10465441SEvalZero la ra, _start 27*10465441SEvalZero 28*10465441SEvalZero /* disable interrupt */ 29*10465441SEvalZero mfc0 t0, CP0_STATUS 30*10465441SEvalZero and t0, 0xfffffffe # By default it will be disabled. 31*10465441SEvalZero mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. 32*10465441SEvalZero nop 33*10465441SEvalZero 34*10465441SEvalZero /* disable cache */ 35*10465441SEvalZero mfc0 t0, CP0_CONFIG 36*10465441SEvalZero and t0, 0xfffffff8 37*10465441SEvalZero or t0, 0x2 # disable,!default value is not it! 38*10465441SEvalZero mtc0 t0, CP0_CONFIG # Set CPU to disable cache. 39*10465441SEvalZero nop 40*10465441SEvalZero 41*10465441SEvalZero /* setup stack pointer */ 42*10465441SEvalZero li sp, SYSTEM_STACK 43*10465441SEvalZero la gp, _gp 44*10465441SEvalZero 45*10465441SEvalZero /* clear bss */ 46*10465441SEvalZero la t0, __bss_start 47*10465441SEvalZero la t1, __bss_end 48*10465441SEvalZero_clr_bss_loop: 49*10465441SEvalZero sw zero, 0(t0) 50*10465441SEvalZero bne t0, t1, _clr_bss_loop 51*10465441SEvalZero addiu t0, t0, 4 52*10465441SEvalZero 53*10465441SEvalZero /* jump to RT-Thread RTOS */ 54*10465441SEvalZero jal rtthread_startup 55*10465441SEvalZero nop 56*10465441SEvalZero 57*10465441SEvalZero /* restart, never die */ 58*10465441SEvalZero j _start 59*10465441SEvalZero nop 60*10465441SEvalZero .set reorder 61*10465441SEvalZero 62*10465441SEvalZero .globl cp0_get_cause 63*10465441SEvalZerocp0_get_cause: 64*10465441SEvalZero mfc0 v0, CP0_CAUSE 65*10465441SEvalZero jr ra 66*10465441SEvalZero nop 67*10465441SEvalZero 68*10465441SEvalZero .globl cp0_get_status 69*10465441SEvalZerocp0_get_status: 70*10465441SEvalZero mfc0 v0, CP0_STATUS 71*10465441SEvalZero jr ra 72*10465441SEvalZero nop 73*10465441SEvalZero 74*10465441SEvalZero .globl cp0_get_hi 75*10465441SEvalZerocp0_get_hi: 76*10465441SEvalZero mfhi v0 77*10465441SEvalZero jr ra 78*10465441SEvalZero nop 79*10465441SEvalZero 80*10465441SEvalZero .globl cp0_get_lo 81*10465441SEvalZerocp0_get_lo: 82*10465441SEvalZero mflo v0 83*10465441SEvalZero jr ra 84*10465441SEvalZero nop 85*10465441SEvalZero 86*10465441SEvalZero .extern tlb_refill_handler 87*10465441SEvalZero .extern cache_error_handler 88*10465441SEvalZero 89*10465441SEvalZero /* Exception Handler */ 90*10465441SEvalZero 91*10465441SEvalZero /* 0x0 - TLB refill handler */ 92*10465441SEvalZero .section .vectors.1, "ax", %progbits 93*10465441SEvalZero .global tlb_refill_exception 94*10465441SEvalZero .type tlb_refill_exception,@function 95*10465441SEvalZerotlb_refill_exception: 96*10465441SEvalZero j tlb_refill_handler 97*10465441SEvalZero nop 98*10465441SEvalZero 99*10465441SEvalZero /* 0x100 - Cache error handler */ 100*10465441SEvalZero .section .vectors.2, "ax", %progbits 101*10465441SEvalZero j cache_error_handler 102*10465441SEvalZero nop 103*10465441SEvalZero 104*10465441SEvalZero /* 0x180 - Exception/Interrupt handler */ 105*10465441SEvalZero .section .vectors.3, "ax", %progbits 106*10465441SEvalZero .global general_exception 107*10465441SEvalZero .type general_exception,@function 108*10465441SEvalZerogeneral_exception: 109*10465441SEvalZero j _general_exception_handler 110*10465441SEvalZero nop 111*10465441SEvalZero 112*10465441SEvalZero /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ 113*10465441SEvalZero .section .vectors.4, "ax", %progbits 114*10465441SEvalZero .global irq_exception 115*10465441SEvalZero .type irq_exception,@function 116*10465441SEvalZeroirq_exception: 117*10465441SEvalZero j _irq_handler 118*10465441SEvalZero nop 119*10465441SEvalZero 120*10465441SEvalZero .section .vectors, "ax", %progbits 121*10465441SEvalZero .extern mips_irq_handle 122*10465441SEvalZero 123*10465441SEvalZero /* general exception handler */ 124*10465441SEvalZero_general_exception_handler: 125*10465441SEvalZero .set noreorder 126*10465441SEvalZero la k0, mips_irq_handle 127*10465441SEvalZero jr k0 128*10465441SEvalZero nop 129*10465441SEvalZero .set reorder 130*10465441SEvalZero 131*10465441SEvalZero /* interrupt handler */ 132*10465441SEvalZero_irq_handler: 133*10465441SEvalZero .set noreorder 134*10465441SEvalZero la k0, mips_irq_handle 135*10465441SEvalZero jr k0 136*10465441SEvalZero nop 137*10465441SEvalZero .set reorder 138