1*10465441SEvalZero /*
2*10465441SEvalZero * File : mipscfg.c
3*10465441SEvalZero * This file is part of RT-Thread RTOS
4*10465441SEvalZero * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
5*10465441SEvalZero *
6*10465441SEvalZero * The license and distribution terms for this file may be
7*10465441SEvalZero * found in the file LICENSE in this distribution or at
8*10465441SEvalZero * http://www.rt-thread.org/license/LICENSE
9*10465441SEvalZero *
10*10465441SEvalZero * Change Logs:
11*10465441SEvalZero * Date Author Notes
12*10465441SEvalZero * 2010-05-27 swkyer first version
13*10465441SEvalZero */
14*10465441SEvalZero #include <rtthread.h>
15*10465441SEvalZero #include "../common/mipsregs.h"
16*10465441SEvalZero #include "../common/mipscfg.h"
17*10465441SEvalZero
18*10465441SEvalZero mips32_core_cfg_t g_mips_core =
19*10465441SEvalZero {
20*10465441SEvalZero 16, /* icache_line_size */
21*10465441SEvalZero 256, /* icache_lines_per_way */
22*10465441SEvalZero 4, /* icache_ways */
23*10465441SEvalZero 16, /* dcache_line_size */
24*10465441SEvalZero 256, /* dcache_lines_per_way */
25*10465441SEvalZero 4, /* dcache_ways */
26*10465441SEvalZero 16, /* max_tlb_entries */
27*10465441SEvalZero };
28*10465441SEvalZero
m_pow(rt_uint16_t b,rt_uint16_t n)29*10465441SEvalZero static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
30*10465441SEvalZero {
31*10465441SEvalZero rt_uint16_t rets = 1;
32*10465441SEvalZero
33*10465441SEvalZero while (n--)
34*10465441SEvalZero rets *= b;
35*10465441SEvalZero
36*10465441SEvalZero return rets;
37*10465441SEvalZero }
38*10465441SEvalZero
m_log2(rt_uint16_t b)39*10465441SEvalZero static rt_uint16_t m_log2(rt_uint16_t b)
40*10465441SEvalZero {
41*10465441SEvalZero rt_uint16_t rets = 0;
42*10465441SEvalZero
43*10465441SEvalZero while (b != 1)
44*10465441SEvalZero {
45*10465441SEvalZero b /= 2;
46*10465441SEvalZero rets++;
47*10465441SEvalZero }
48*10465441SEvalZero
49*10465441SEvalZero return rets;
50*10465441SEvalZero }
51*10465441SEvalZero
52*10465441SEvalZero /**
53*10465441SEvalZero * read core attribute
54*10465441SEvalZero */
mips32_cfg_init(void)55*10465441SEvalZero void mips32_cfg_init(void)
56*10465441SEvalZero {
57*10465441SEvalZero rt_uint16_t val;
58*10465441SEvalZero rt_uint32_t cp0_config1;
59*10465441SEvalZero
60*10465441SEvalZero cp0_config1 = read_c0_config();
61*10465441SEvalZero if (cp0_config1 & 0x80000000)
62*10465441SEvalZero {
63*10465441SEvalZero cp0_config1 = read_c0_config1();
64*10465441SEvalZero
65*10465441SEvalZero val = (cp0_config1 & (7<<22))>>22;
66*10465441SEvalZero g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
67*10465441SEvalZero val = (cp0_config1 & (7<<19))>>19;
68*10465441SEvalZero g_mips_core.icache_line_size = 2 * m_pow(2, val);
69*10465441SEvalZero val = (cp0_config1 & (7<<16))>>16;
70*10465441SEvalZero g_mips_core.icache_ways = val + 1;
71*10465441SEvalZero
72*10465441SEvalZero val = (cp0_config1 & (7<<13))>>13;
73*10465441SEvalZero g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
74*10465441SEvalZero val = (cp0_config1 & (7<<10))>>10;
75*10465441SEvalZero g_mips_core.dcache_line_size = 2 * m_pow(2, val);
76*10465441SEvalZero val = (cp0_config1 & (7<<7))>>7;
77*10465441SEvalZero g_mips_core.dcache_ways = val + 1;
78*10465441SEvalZero
79*10465441SEvalZero val = (cp0_config1 & (0x3F<<25))>>25;
80*10465441SEvalZero g_mips_core.max_tlb_entries = val + 1;
81*10465441SEvalZero }
82*10465441SEvalZero }
83