xref: /nrf52832-nimble/rt-thread/libcpu/mips/common/mipscfg.h (revision 104654410c56c573564690304ae786df310c91fc)
1*10465441SEvalZero /*
2*10465441SEvalZero  * File      : mipscfg.h
3*10465441SEvalZero  * This file is part of RT-Thread RTOS
4*10465441SEvalZero  * COPYRIGHT (C) 2010, RT-Thread Development Team
5*10465441SEvalZero  *
6*10465441SEvalZero  * The license and distribution terms for this file may be
7*10465441SEvalZero  * found in the file LICENSE in this distribution or at
8*10465441SEvalZero  * http://www.rt-thread.org/license/LICENSE
9*10465441SEvalZero  *
10*10465441SEvalZero  * Change Logs:
11*10465441SEvalZero  * Date           Author       Notes
12*10465441SEvalZero  * 2010-05-27     swkyer       first version
13*10465441SEvalZero  */
14*10465441SEvalZero #ifndef __MIPSCFG_H__
15*10465441SEvalZero #define __MIPSCFG_H__
16*10465441SEvalZero 
17*10465441SEvalZero 
18*10465441SEvalZero typedef struct mips32_core_cfg
19*10465441SEvalZero {
20*10465441SEvalZero     rt_uint16_t icache_line_size;
21*10465441SEvalZero     rt_uint16_t icache_lines_per_way;
22*10465441SEvalZero     rt_uint16_t icache_ways;
23*10465441SEvalZero     rt_uint16_t dcache_line_size;
24*10465441SEvalZero     rt_uint16_t dcache_lines_per_way;
25*10465441SEvalZero     rt_uint16_t dcache_ways;
26*10465441SEvalZero 
27*10465441SEvalZero     rt_uint16_t max_tlb_entries;	/* number of tlb entry */
28*10465441SEvalZero } mips32_core_cfg_t;
29*10465441SEvalZero 
30*10465441SEvalZero extern mips32_core_cfg_t g_mips_core;
31*10465441SEvalZero 
32*10465441SEvalZero #endif /* end of __MIPSCFG_H__ */
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