xref: /nrf52832-nimble/rt-thread/libcpu/mips/common/mips.inc (revision 104654410c56c573564690304ae786df310c91fc)
1*10465441SEvalZero/*
2*10465441SEvalZero * File      : mips.inc
3*10465441SEvalZero * This file is part of RT-Thread RTOS
4*10465441SEvalZero * COPYRIGHT (C) 2010, RT-Thread Development Team
5*10465441SEvalZero *
6*10465441SEvalZero * The license and distribution terms for this file may be
7*10465441SEvalZero * found in the file LICENSE in this distribution or at
8*10465441SEvalZero * http://www.rt-thread.org/license/LICENSE
9*10465441SEvalZero *
10*10465441SEvalZero * Change Logs:
11*10465441SEvalZero * Date           Author       Notes
12*10465441SEvalZero * 2010-05-17     sangwei      first version
13*10465441SEvalZero */
14*10465441SEvalZero#ifndef __MIPS_INC__
15*10465441SEvalZero#define __MIPS_INC__
16*10465441SEvalZero
17*10465441SEvalZero#define zero    $0		/* wired zero */
18*10465441SEvalZero// #define at      $1
19*10465441SEvalZero#define v0      $2		/* return value */
20*10465441SEvalZero#define v1      $3
21*10465441SEvalZero#define a0      $4		/* argument registers */
22*10465441SEvalZero#define a1      $5
23*10465441SEvalZero#define a2      $6
24*10465441SEvalZero#define a3      $7
25*10465441SEvalZero#define t0      $8		/* caller saved */
26*10465441SEvalZero#define t1      $9
27*10465441SEvalZero#define t2      $10
28*10465441SEvalZero#define t3      $11
29*10465441SEvalZero#define t4      $12
30*10465441SEvalZero#define t5      $13
31*10465441SEvalZero#define t6      $14
32*10465441SEvalZero#define t7      $15
33*10465441SEvalZero#define s0      $16		/* callee saved */
34*10465441SEvalZero#define s1      $17
35*10465441SEvalZero#define s2      $18
36*10465441SEvalZero#define s3      $19
37*10465441SEvalZero#define s4      $20
38*10465441SEvalZero#define s5      $21
39*10465441SEvalZero#define s6      $22
40*10465441SEvalZero#define s7      $23
41*10465441SEvalZero#define t8      $24		/* caller saved */
42*10465441SEvalZero#define t9      $25
43*10465441SEvalZero#define jp      $25     /* PIC jump register */
44*10465441SEvalZero#define k0      $26     /* kernel scratch */
45*10465441SEvalZero#define k1      $27
46*10465441SEvalZero#define gp      $28     /* global pointer */
47*10465441SEvalZero#define sp      $29     /* stack pointer */
48*10465441SEvalZero#define fp      $30     /* frame pointer */
49*10465441SEvalZero#define s8		$30		/* same like fp! */
50*10465441SEvalZero#define ra      $31     /* return address */
51*10465441SEvalZero
52*10465441SEvalZero#endif /* end of __MIPS_INC__   */
53