1*10465441SEvalZero/* 2*10465441SEvalZero * File : contex_ck802.S 3*10465441SEvalZero * This file is part of RT-Thread RTOS 4*10465441SEvalZero * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team 5*10465441SEvalZero * 6*10465441SEvalZero * This program is free software; you can redistribute it and/or modify 7*10465441SEvalZero * it under the terms of the GNU General Public License as published by 8*10465441SEvalZero * the Free Software Foundation; either version 2 of the License, or 9*10465441SEvalZero * (at your option) any later version. 10*10465441SEvalZero * 11*10465441SEvalZero * This program is distributed in the hope that it will be useful, 12*10465441SEvalZero * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*10465441SEvalZero * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*10465441SEvalZero * GNU General Public License for more details. 15*10465441SEvalZero * 16*10465441SEvalZero * You should have received a copy of the GNU General Public License along 17*10465441SEvalZero * with this program; if not, write to the Free Software Foundation, Inc., 18*10465441SEvalZero * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19*10465441SEvalZero * 20*10465441SEvalZero * Change Logs: 21*10465441SEvalZero * Date Author Notes 22*10465441SEvalZero * 2017-01-01 Urey first version 23*10465441SEvalZero * 2018-06-05 tanek clean code 24*10465441SEvalZero */ 25*10465441SEvalZero 26*10465441SEvalZero.file "contex_ck802.S" 27*10465441SEvalZero 28*10465441SEvalZero#undef VIC_TSPDR 29*10465441SEvalZero#define VIC_TSPDR 0XE000EC08 30*10465441SEvalZero 31*10465441SEvalZero.global rt_thread_switch_interrupt_flag 32*10465441SEvalZero.global rt_interrupt_from_thread 33*10465441SEvalZero.global rt_interrupt_to_thread 34*10465441SEvalZero 35*10465441SEvalZero.text 36*10465441SEvalZero.align 2 37*10465441SEvalZero 38*10465441SEvalZero/* 39*10465441SEvalZero * rt_base_t rt_hw_interrupt_disable(void); 40*10465441SEvalZero */ 41*10465441SEvalZero.global rt_hw_interrupt_disable 42*10465441SEvalZero.type rt_hw_interrupt_disable, %function 43*10465441SEvalZerort_hw_interrupt_disable: 44*10465441SEvalZeromfcr r0, psr 45*10465441SEvalZeropsrclr ie 46*10465441SEvalZerorts 47*10465441SEvalZero 48*10465441SEvalZero/* 49*10465441SEvalZero * void rt_hw_interrupt_enable(rt_base_t psr); 50*10465441SEvalZero */ 51*10465441SEvalZero.global rt_hw_interrupt_enable 52*10465441SEvalZero.type rt_hw_interrupt_enable, %function 53*10465441SEvalZerort_hw_interrupt_enable: 54*10465441SEvalZeromtcr r0, psr 55*10465441SEvalZerorts 56*10465441SEvalZero 57*10465441SEvalZero/* 58*10465441SEvalZero * void rt_hw_context_switch_to(rt_uint32 to); 59*10465441SEvalZero * R0 --> to 60*10465441SEvalZero */ 61*10465441SEvalZero.global rt_hw_context_switch_to 62*10465441SEvalZero.type rt_hw_context_switch_to, %function 63*10465441SEvalZerort_hw_context_switch_to: 64*10465441SEvalZerolrw r2, rt_interrupt_to_thread 65*10465441SEvalZerostw r0, (r2) 66*10465441SEvalZero 67*10465441SEvalZero/* set form thread = 0 */ 68*10465441SEvalZerolrw r2, rt_interrupt_from_thread 69*10465441SEvalZeromovi r0, 0 70*10465441SEvalZerostw r0, (r2) 71*10465441SEvalZero 72*10465441SEvalZeropsrclr ie 73*10465441SEvalZerojbr __tspend_handler_nosave 74*10465441SEvalZero 75*10465441SEvalZero/* 76*10465441SEvalZero * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); 77*10465441SEvalZero * r0 --> from 78*10465441SEvalZero * r1 --> to 79*10465441SEvalZero */ 80*10465441SEvalZero.global rt_hw_context_switch_interrupt 81*10465441SEvalZero.type rt_hw_context_switch_interrupt, %function 82*10465441SEvalZerort_hw_context_switch_interrupt: 83*10465441SEvalZerolrw r2, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ 84*10465441SEvalZerostw r0, (r2) 85*10465441SEvalZero 86*10465441SEvalZerolrw r2, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ 87*10465441SEvalZerostw r1, (r2) 88*10465441SEvalZero 89*10465441SEvalZerolrw r0, VIC_TSPDR 90*10465441SEvalZerobgeni r1, 0 91*10465441SEvalZerostw r1, (r0) 92*10465441SEvalZerorts 93*10465441SEvalZero 94*10465441SEvalZero/* 95*10465441SEvalZero * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) 96*10465441SEvalZero * r0 --> from 97*10465441SEvalZero * r1 --> to 98*10465441SEvalZero */ 99*10465441SEvalZero.global rt_hw_context_switch 100*10465441SEvalZero.type rt_hw_context_switch, %function 101*10465441SEvalZerort_hw_context_switch: 102*10465441SEvalZerolrw r2, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ 103*10465441SEvalZerostw r0, (r2) 104*10465441SEvalZero 105*10465441SEvalZerolrw r2, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ 106*10465441SEvalZerostw r1, (r2) 107*10465441SEvalZero 108*10465441SEvalZerolrw r0, VIC_TSPDR 109*10465441SEvalZerobgeni r1, 0 110*10465441SEvalZerostw r1, (r0) 111*10465441SEvalZerorts 112*10465441SEvalZero 113*10465441SEvalZero.global PendSV_Handler 114*10465441SEvalZero.type PendSV_Handler, %function 115*10465441SEvalZeroPendSV_Handler: 116*10465441SEvalZerosubi sp, 68 117*10465441SEvalZerostm r0-r13, (sp) 118*10465441SEvalZerostw r15, (sp, 56) 119*10465441SEvalZeromfcr r0, epsr 120*10465441SEvalZerostw r0, (sp, 60) 121*10465441SEvalZeromfcr r0, epc 122*10465441SEvalZerostw r0, (sp, 64) 123*10465441SEvalZero 124*10465441SEvalZerolrw r0, rt_interrupt_from_thread 125*10465441SEvalZeroldw r1, (r0) 126*10465441SEvalZerostw sp, (r1) 127*10465441SEvalZero 128*10465441SEvalZero__tspend_handler_nosave: 129*10465441SEvalZerolrw r6, rt_interrupt_to_thread 130*10465441SEvalZerolrw r7, rt_interrupt_from_thread 131*10465441SEvalZeroldw r8, (r6) 132*10465441SEvalZerostw r8, (r7) 133*10465441SEvalZero 134*10465441SEvalZeroldw sp, (r8) 135*10465441SEvalZero 136*10465441SEvalZero#ifdef CONFIG_STACK_GUARD 137*10465441SEvalZeromfcr r3, cr<0, 4> 138*10465441SEvalZerobseti r3, 0 139*10465441SEvalZerobseti r3, 1 140*10465441SEvalZeromtcr r3, cr<0, 4> 141*10465441SEvalZero#endif 142*10465441SEvalZero 143*10465441SEvalZeroldw r0, (sp, 64) 144*10465441SEvalZeromtcr r0, epc 145*10465441SEvalZeroldw r0, (sp, 60) 146*10465441SEvalZerobseti r0, 6 147*10465441SEvalZeromtcr r0, epsr 148*10465441SEvalZeroldw r15, (sp, 56) 149*10465441SEvalZeroldm r0-r13, (sp) 150*10465441SEvalZeroaddi sp, 68 151*10465441SEvalZerorte 152*10465441SEvalZero 153