1;/*****************************************************************************/ 2;/* S3C44B0X.S: Startup file for Samsung S3C44B0X */ 3;/*****************************************************************************/ 4;/* <<< Use Configuration Wizard in Context Menu >>> */ 5;/*****************************************************************************/ 6;/* This file is part of the uVision/ARM development tools. */ 7;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ 8;/* This software may only be used under the terms of a valid, current, */ 9;/* end user licence from KEIL for a compatible version of KEIL software */ 10;/* development tools. Nothing else gives you the right to use this software. */ 11;/*****************************************************************************/ 12 13 14; *** Startup Code (executed after Reset) *** 15 16 17; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs 18 19Mode_USR EQU 0x10 20Mode_FIQ EQU 0x11 21Mode_IRQ EQU 0x12 22Mode_SVC EQU 0x13 23Mode_ABT EQU 0x17 24Mode_UND EQU 0x1B 25Mode_SYS EQU 0x1F 26 27I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 28F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 29 30 31;// <h> Stack Configuration (Stack Sizes in Bytes) 32;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> 33;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> 34;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> 35;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> 36;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> 37;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> 38;// </h> 39 40UND_Stack_Size EQU 0x00000000 41SVC_Stack_Size EQU 0x00000100 42ABT_Stack_Size EQU 0x00000000 43FIQ_Stack_Size EQU 0x00000000 44IRQ_Stack_Size EQU 0x00000100 45USR_Stack_Size EQU 0x00000100 46 47ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ 48 FIQ_Stack_Size + IRQ_Stack_Size) 49 50 AREA STACK, NOINIT, READWRITE, ALIGN=3 51 52Stack_Mem SPACE USR_Stack_Size 53__initial_sp SPACE ISR_Stack_Size 54Stack_Top 55 56 57;// <h> Heap Configuration 58;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> 59;// </h> 60 61Heap_Size EQU 0x00000000 62 63 AREA HEAP, NOINIT, READWRITE, ALIGN=3 64__heap_base 65Heap_Mem SPACE Heap_Size 66__heap_limit 67 68 69; CPU Wrapper and Bus Priorities definitions 70CPUW_BASE EQU 0x01C00000 ; CPU Wrapper Base Address 71SYSCFG_OFS EQU 0x00 ; SYSCFG Offset 72NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset 73NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset 74BUSP_BASE EQU 0x01C40000 ; Bus Priority Base Address 75SBUSCON_OFS EQU 0x00 ; SBUSCON Offset 76 77;// <e> CPU Wrapper and Bus Priorities 78;// <h> CPU Wrapper 79;// <o1.0> SE: Stall Enable 80;// <o1.1..2> CM: Cache Mode 81;// <0=> Disable Cache (8kB SRAM) 82;// <1=> Half Cache Enable (4kB Cache, 4kB SRAM) 83;// <2=> Reserved 84;// <3=> Full Cache Enable (8kB Cache) 85;// <o1.3> WE: Write Buffer Enable 86;// <o1.4> RSE: Read Stall Enable 87;// <o1.5> DA: Data Abort <0=> Enable <1=> Disable 88;// <h> Non-cacheable Area 0 89;// <o2.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> 90;// <i> SA = (Start Address) / 4k 91;// <o2.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> 92;// <i> SE = (End Address + 1) / 4k 93;// </h> 94;// <h> Non-cacheable Area 1 95;// <o3.0..15> Start Address <0x0-0x0FFFF000:0x1000><#/0x1000> 96;// <i> SA = (Start Address) / 4k 97;// <o3.16..31> End Address + 1 <0x0-0x10000000:0x1000><#/0x1000> 98;// <i> SE = (End Address + 1) / 4k 99;// </h> 100;// </h> 101;// <h> Bus Priorities 102;// <o4.31> FIX: Fixed Priorities 103;// <o4.6..7> LCD_DMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th 104;// <o4.4..5> ZDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th 105;// <o4.2..3> BDMA <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th 106;// <o4.0..1> nBREQ <0=> 1st <1=> 2nd <2=> 3rd <3=> 4th 107;// </h> 108;// </e> 109SYS_SETUP EQU 0 110SYSCFG_Val EQU 0x00000001 111NCACHBE0_Val EQU 0x00000000 112NCACHBE1_Val EQU 0x00000000 113SBUSCON_Val EQU 0x80001B1B 114 115 116;// <e> Vectored Interrupt Mode (for IRQ) 117;// <o1.25> EINT0 <i> External Interrupt 0 118;// <o1.24> EINT1 <i> External Interrupt 1 119;// <o1.23> EINT2 <i> External Interrupt 2 120;// <o1.22> EINT3 <i> External Interrupt 3 121;// <o1.21> EINT4567 <i> External Interrupt 4/5/6/7 122;// <o1.20> TICK <i> RTC Time Tick Interrupt 123;// <o1.19> ZDMA0 <i> General DMA0 Interrupt 124;// <o1.18> ZDMA1 <i> General DMA1 Interrupt 125;// <o1.17> BDMA0 <i> Bridge DMA0 Interrupt 126;// <o1.16> BDMA1 <i> Bridge DMA1 Interrupt 127;// <o1.15> WDT <i> Watchdog Timer Interrupt 128;// <o1.14> UERR01 <i> UART0/1 Error Interrupt 129;// <o1.13> TIMER0 <i> Timer0 Interrupt 130;// <o1.12> TIMER1 <i> Timer1 Interrupt 131;// <o1.11> TIMER2 <i> Timer2 Interrupt 132;// <o1.10> TIMER3 <i> Timer3 Interrupt 133;// <o1.9> TIMER4 <i> Timer4 Interrupt 134;// <o1.8> TIMER5 <i> Timer5 Interrupt 135;// <o1.7> URXD0 <i> UART0 Rx Interrupt 136;// <o1.6> URXD1 <i> UART1 Rx Interrupt 137;// <o1.5> IIC <i> IIC Interrupt 138;// <o1.4> SIO <i> SIO Interrupt 139;// <o1.3> UTXD0 <i> UART0 Tx Interrupt 140;// <o1.2> UTXD1 <i> UART1 Tx Interrupt 141;// <o1.1> RTC <i> RTC Alarm Interrupt 142;// <o1.0> ADC <i> ADC EOC Interrupt 143;// </e> 144VIM_SETUP EQU 0 145VIM_CFG EQU 0x00000000 146 147 148; Clock Management definitions 149CLK_BASE EQU 0x01D80000 ; Clock Base Address 150PLLCON_OFS EQU 0x00 ; PLLCON Offset 151CLKCON_OFS EQU 0x04 ; CLKCON Offset 152CLKSLOW_OFS EQU 0x08 ; CLKSLOW Offset 153LOCKTIME_OFS EQU 0x0C ; LOCKTIME Offset 154 155;// <e> Clock Management 156;// <h> PLL Settings 157;// <i> Fpllo = (m * Fin) / (p * 2^s), 20MHz < Fpllo < 66MHz 158;// <o1.12..19> MDIV: Main divider <0x0-0xFF> 159;// <i> m = MDIV + 8 160;// <o1.4..9> PDIV: Pre-divider <0x0-0x3F> 161;// <i> p = PDIV + 2, 1MHz <= Fin/p < 2MHz 162;// <o1.0..1> SDIV: Post Divider <0x0-0x03> 163;// <i> s = SDIV, Fpllo * 2^s < 170MHz 164;// <o4.0..11> LTIME CNT: PLL Lock Time Count <0x0-0x0FFF> 165;// </h> 166;// <h> Master Clock 167;// <i> PLL Clock: Fout = Fpllo 168;// <i> Slow Clock: Fout = Fin / (2 * SLOW_VAL), SLOW_VAL > 0 169;// <i> Slow Clock: Fout = Fin, SLOW_VAL = 0 170;// <o3.5> PLL_OFF: PLL Off 171;// <i> PLL is turned Off only when SLOW_BIT = 1 172;// <o3.4> SLOW_BIT: Slow Clock 173;// <o3.0..3> SLOW_VAL: Slow Clock divider <0x0-0x0F> 174;// </h> 175;// <h> Clock Generation 176;// <o2.14> IIS <0=> Disable <1=> Enable 177;// <o2.13> IIC <0=> Disable <1=> Enable 178;// <o2.12> ADC <0=> Disable <1=> Enable 179;// <o2.11> RTC <0=> Disable <1=> Enable 180;// <o2.10> GPIO <0=> Disable <1=> Enable 181;// <o2.9> UART1 <0=> Disable <1=> Enable 182;// <o2.8> UART0 <0=> Disable <1=> Enable 183;// <o2.7> BDMA0,1 <0=> Disable <1=> Enable 184;// <o2.6> LCDC <0=> Disable <1=> Enable 185;// <o2.5> SIO <0=> Disable <1=> Enable 186;// <o2.4> ZDMA0,1 <0=> Disable <1=> Enable 187;// <o2.3> PWMTIMER <0=> Disable <1=> Enable 188;// </h> 189;// </e> 190CLK_SETUP EQU 1 191PLLCON_Val EQU 0x00038080 192CLKCON_Val EQU 0x00007FF8 193CLKSLOW_Val EQU 0x00000009 194LOCKTIME_Val EQU 0x00000FFF 195 196 197; Watchdog Timer definitions 198WT_BASE EQU 0x01D30000 ; WT Base Address 199WTCON_OFS EQU 0x00 ; WTCON Offset 200WTDAT_OFS EQU 0x04 ; WTDAT Offset 201WTCNT_OFS EQU 0x08 ; WTCNT Offset 202 203;// <e> Watchdog Timer 204;// <o1.5> Watchdog Timer Enable/Disable 205;// <o1.0> Reset Enable/Disable 206;// <o1.2> Interrupt Enable/Disable 207;// <o1.3..4> Clock Select 208;// <0=> 1/16 <1=> 1/32 <2=> 1/64 <3=> 1/128 209;// <i> Clock Division Factor 210;// <o1.8..15> Prescaler Value <0x0-0xFF> 211;// <o2.0..15> Time-out Value <0x0-0xFFFF> 212;// </e> 213WT_SETUP EQU 1 214WTCON_Val EQU 0x00008000 215WTDAT_Val EQU 0x00008000 216 217 218; Memory Controller definitions 219MC_BASE EQU 0x01C80000 ; Memory Controller Base Address 220 221;// <e> Memory Controller 222MC_SETUP EQU 1 223 224;// <h> Bank 0 225;// <o0.0..1> PMC: Page Mode Configuration 226;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 227;// <o0.2..3> Tpac: Page Mode Access Cycle 228;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 229;// <o0.4..5> Tcah: Address Holding Time after nGCSn 230;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 231;// <o0.6..7> Toch: Chip Select Hold on nOE 232;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 233;// <o0.8..10> Tacc: Access Cycle 234;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 235;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 236;// <o0.11..12> Tcos: Chip Select Set-up nOE 237;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 238;// <o0.13..14> Tacs: Address Set-up before nGCSn 239;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 240;// </h> 241;// 242;// <h> Bank 1 243;// <o8.4..5> DW: Data Bus Width 244;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 245;// <o8.6> WS: WAIT Status 246;// <0=> WAIT Disable 247;// <1=> WAIT Enable 248;// <o8.7> ST: SRAM Type 249;// <0=> Not using UB/LB 250;// <1=> Using UB/LB 251;// <o1.0..1> PMC: Page Mode Configuration 252;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 253;// <o1.2..3> Tpac: Page Mode Access Cycle 254;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 255;// <o1.4..5> Tcah: Address Holding Time after nGCSn 256;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 257;// <o1.6..7> Toch: Chip Select Hold on nOE 258;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 259;// <o1.8..10> Tacc: Access Cycle 260;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 261;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 262;// <o1.11..12> Tcos: Chip Select Set-up nOE 263;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 264;// <o1.13..14> Tacs: Address Set-up before nGCSn 265;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 266;// </h> 267;// 268;// <h> Bank 2 269;// <o8.8..9> DW: Data Bus Width 270;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 271;// <o8.10> WS: WAIT Status 272;// <0=> WAIT Disable 273;// <1=> WAIT Enable 274;// <o8.11> ST: SRAM Type 275;// <0=> Not using UB/LB 276;// <1=> Using UB/LB 277;// <o2.0..1> PMC: Page Mode Configuration 278;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 279;// <o2.2..3> Tpac: Page Mode Access Cycle 280;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 281;// <o2.4..5> Tcah: Address Holding Time after nGCSn 282;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 283;// <o2.6..7> Toch: Chip Select Hold on nOE 284;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 285;// <o2.8..10> Tacc: Access Cycle 286;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 287;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 288;// <o2.11..12> Tcos: Chip Select Set-up nOE 289;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 290;// <o2.13..14> Tacs: Address Set-up before nGCSn 291;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 292;// </h> 293;// 294;// <h> Bank 3 295;// <o8.12..13> DW: Data Bus Width 296;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 297;// <o8.14> WS: WAIT Status 298;// <0=> WAIT Disable 299;// <1=> WAIT Enable 300;// <o8.15> ST: SRAM Type 301;// <0=> Not using UB/LB 302;// <1=> Using UB/LB 303;// <o3.0..1> PMC: Page Mode Configuration 304;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 305;// <o3.2..3> Tpac: Page Mode Access Cycle 306;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 307;// <o3.4..5> Tcah: Address Holding Time after nGCSn 308;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 309;// <o3.6..7> Toch: Chip Select Hold on nOE 310;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 311;// <o3.8..10> Tacc: Access Cycle 312;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 313;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 314;// <o3.11..12> Tcos: Chip Select Set-up nOE 315;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 316;// <o3.13..14> Tacs: Address Set-up before nGCSn 317;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 318;// </h> 319;// 320;// <h> Bank 4 321;// <o8.16..17> DW: Data Bus Width 322;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 323;// <o8.18> WS: WAIT Status 324;// <0=> WAIT Disable 325;// <1=> WAIT Enable 326;// <o8.19> ST: SRAM Type 327;// <0=> Not using UB/LB 328;// <1=> Using UB/LB 329;// <o4.0..1> PMC: Page Mode Configuration 330;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 331;// <o4.2..3> Tpac: Page Mode Access Cycle 332;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 333;// <o4.4..5> Tcah: Address Holding Time after nGCSn 334;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 335;// <o4.6..7> Toch: Chip Select Hold on nOE 336;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 337;// <o4.8..10> Tacc: Access Cycle 338;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 339;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 340;// <o4.11..12> Tcos: Chip Select Set-up nOE 341;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 342;// <o4.13..14> Tacs: Address Set-up before nGCSn 343;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 344;// </h> 345;// 346;// <h> Bank 5 347;// <o8.20..21> DW: Data Bus Width 348;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 349;// <o8.22> WS: WAIT Status 350;// <0=> WAIT Disable 351;// <1=> WAIT Enable 352;// <o8.23> ST: SRAM Type 353;// <0=> Not using UB/LB 354;// <1=> Using UB/LB 355;// <o5.0..1> PMC: Page Mode Configuration 356;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 357;// <o5.2..3> Tpac: Page Mode Access Cycle 358;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 359;// <o5.4..5> Tcah: Address Holding Time after nGCSn 360;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 361;// <o5.6..7> Toch: Chip Select Hold on nOE 362;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 363;// <o5.8..10> Tacc: Access Cycle 364;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 365;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 366;// <o5.11..12> Tcos: Chip Select Set-up nOE 367;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 368;// <o5.13..14> Tacs: Address Set-up before nGCSn 369;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 370;// </h> 371;// 372;// <h> Bank 6 373;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map 374;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M 375;// <o8.24..25> DW: Data Bus Width 376;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 377;// <o8.26> WS: WAIT Status 378;// <0=> WAIT Disable 379;// <1=> WAIT Enable 380;// <o8.27> ST: SRAM Type 381;// <0=> Not using UB/LB 382;// <1=> Using UB/LB 383;// <o6.15..16> MT: Memory Type 384;// <0=> ROM or SRAM 385;// <1=> FP DRAMP 386;// <2=> EDO DRAM 387;// <3=> SDRAM 388;// <h> ROM or SRAM 389;// <o6.0..1> PMC: Page Mode Configuration 390;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 391;// <o6.2..3> Tpac: Page Mode Access Cycle 392;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 393;// <o6.4..5> Tcah: Address Holding Time after nGCSn 394;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 395;// <o6.6..7> Toch: Chip Select Hold on nOE 396;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 397;// <o6.8..10> Tacc: Access Cycle 398;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 399;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 400;// <o6.11..12> Tcos: Chip Select Set-up nOE 401;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 402;// <o6.13..14> Tacs: Address Set-up before nGCSn 403;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 404;// </h> 405;// <h> FP DRAM or EDO DRAM 406;// <o6.0..1> CAN: Columnn Address Number 407;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit 408;// <o6.2> Tcp: CAS Pre-charge 409;// <0=> 1 clk <1=> 2 clks 410;// <o6.3> Tcas: CAS Pulse Width 411;// <0=> 1 clk <1=> 2 clks 412;// <o6.4..5> Trcd: RAS to CAS Delay 413;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 414;// </h> 415;// <h> SDRAM 416;// <o6.0..1> SCAN: Columnn Address Number 417;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd 418;// <o6.2..3> Trcd: RAS to CAS Delay 419;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd 420;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7) 421;// <0=> Normal 422;// <1=> Reduced Power 423;// <o11.0..2> BL: Burst Length 424;// <0=> 1 425;// <o11.3> BT: Burst Type 426;// <0=> Sequential 427;// <o11.4..6> CL: CAS Latency 428;// <0=> 1 clk <1=> 2 clks <2=> 3 clks 429;// <o11.7..8> TM: Test Mode 430;// <0=> Mode Register Set 431;// <o11.9> WBL: Write Burst Length 432;// <0=> 0 433;// </h> 434;// </h> 435;// 436;// <h> Bank 7 437;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map 438;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M 439;// <o8.28..29> DW: Data Bus Width 440;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd 441;// <o8.30> WS: WAIT Status 442;// <0=> WAIT Disable 443;// <1=> WAIT Enable 444;// <o8.31> ST: SRAM Type 445;// <0=> Not using UB/LB 446;// <1=> Using UB/LB 447;// <o7.15..16> MT: Memory Type 448;// <0=> ROM or SRAM 449;// <1=> FP DRAMP 450;// <2=> EDO DRAM 451;// <3=> SDRAM 452;// <h> ROM or SRAM 453;// <o7.0..1> PMC: Page Mode Configuration 454;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data 455;// <o7.2..3> Tpac: Page Mode Access Cycle 456;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks 457;// <o7.4..5> Tcah: Address Holding Time after nGCSn 458;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 459;// <o7.6..7> Toch: Chip Select Hold on nOE 460;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 461;// <o7.8..10> Tacc: Access Cycle 462;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 463;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks 464;// <o7.11..12> Tcos: Chip Select Set-up nOE 465;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 466;// <o7.13..14> Tacs: Address Set-up before nGCSn 467;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks 468;// </h> 469;// <h> FP DRAM or EDO DRAM 470;// <o7.0..1> CAN: Columnn Address Number 471;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit 472;// <o7.2> Tcp: CAS Pre-charge 473;// <0=> 1 clk <1=> 2 clks 474;// <o7.3> Tcas: CAS Pulse Width 475;// <0=> 1 clk <1=> 2 clks 476;// <o7.4..5> Trcd: RAS to CAS Delay 477;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks 478;// </h> 479;// <h> SDRAM 480;// <o7.0..1> SCAN: Columnn Address Number 481;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd 482;// <o7.2..3> Trcd: RAS to CAS Delay 483;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd 484;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7) 485;// <0=> Normal 486;// <1=> Reduced Power 487;// <o12.0..2> BL: Burst Length 488;// <0=> 1 489;// <o12.3> BT: Burst Type 490;// <0=> Sequential 491;// <o12.4..6> CL: CAS Latency 492;// <0=> 1 clk <1=> 2 clks <2=> 3 clks 493;// <o12.7..8> TM: Test Mode 494;// <0=> Mode Register Set 495;// <o12.9> WBL: Write Burst Length 496;// <0=> 0 497;// </h> 498;// </h> 499;// 500;// <h> Refresh 501;// <o9.23> REFEN: DRAM/SDRAM Refresh 502;// <0=> Disable <1=> Enable 503;// <o9.22> TREFMD: DRAM/SDRAM Refresh Mode 504;// <0=> CBR/Auto Refresh 505;// <1=> Self Refresh 506;// <o9.20..21> Trp: DRAM/SDRAM RAS Pre-charge Time 507;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM) 508;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM) 509;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM) 510;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM) 511;// <o9.18..19> Trc: SDRAM RC Min Time 512;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks 513;// <o9.16..17> Tchr: DRAM CAS Hold Time 514;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks 515;// <o9.0..10> Refresh Counter <0x0-0x07FF> 516;// <i> Refresh Period = (2^11 - Refresh Count + 1) / MCLK 517;// </h> 518BANKCON0_Val EQU 0x00000700 519BANKCON1_Val EQU 0x00000700 520BANKCON2_Val EQU 0x00000700 521BANKCON3_Val EQU 0x00000700 522BANKCON4_Val EQU 0x00000700 523BANKCON5_Val EQU 0x00000700 524BANKCON6_Val EQU 0x00018008 525BANKCON7_Val EQU 0x00018008 526BWSCON_Val EQU 0x00000000 527REFRESH_Val EQU 0x00AC0000 528BANKSIZE_Val EQU 0x00000000 529MRSRB6_Val EQU 0x00000000 530MRSRB7_Val EQU 0x00000000 531 532;// </e> End of MC 533 534 535; I/O Ports definitions 536PIO_BASE EQU 0x01D20000 ; PIO Base Address 537PCONA_OFS EQU 0x00 ; PCONA Offset 538PCONB_OFS EQU 0x08 ; PCONB Offset 539PCONC_OFS EQU 0x10 ; PCONC Offset 540PCOND_OFS EQU 0x1C ; PCOND Offset 541PCONE_OFS EQU 0x28 ; PCONE Offset 542PCONF_OFS EQU 0x34 ; PCONF Offset 543PCONG_OFS EQU 0x40 ; PCONG Offset 544PUPC_OFS EQU 0x18 ; PUPC Offset 545PUPD_OFS EQU 0x24 ; PUPD Offset 546PUPE_OFS EQU 0x30 ; PUPE Offset 547PUPF_OFS EQU 0x3C ; PUPF Offset 548PUPG_OFS EQU 0x48 ; PUPG Offset 549SPUCR_OFS EQU 0x4C ; SPUCR Offset 550 551;// <e> I/O Configuration 552PIO_SETUP EQU 0 553 554;// <e> Port A 555;// <o1.0> PA0 <0=> Output <1=> ADDR0 556;// <o1.1> PA1 <0=> Output <1=> ADDR16 557;// <o1.2> PA2 <0=> Output <1=> ADDR17 558;// <o1.3> PA3 <0=> Output <1=> ADDR18 559;// <o1.4> PA4 <0=> Output <1=> ADDR19 560;// <o1.5> PA5 <0=> Output <1=> ADDR20 561;// <o1.6> PA6 <0=> Output <1=> ADDR21 562;// <o1.7> PA7 <0=> Output <1=> ADDR22 563;// <o1.8> PA8 <0=> Output <1=> ADDR23 564;// <o1.9> PA9 <0=> Output <1=> ADDR24 565;// </e> 566PIOA_SETUP EQU 1 567PCONA_Val EQU 0x000003FF 568 569;// <e> Port B 570;// <o1.0> PB0 <0=> Output <1=> SCKE 571;// <o1.1> PB1 <0=> Output <1=> CKLK 572;// <o1.2> PB2 <0=> Output <1=> nSCAS/nCAS2 573;// <o1.3> PB3 <0=> Output <1=> nSRAS/nCAS3 574;// <o1.4> PB4 <0=> Output <1=> nWBE2/nBE2/DQM2 575;// <o1.5> PB5 <0=> Output <1=> nWBE3/nBE3/DQM3 576;// <o1.6> PB6 <0=> Output <1=> nGCS1 577;// <o1.7> PB7 <0=> Output <1=> nGCS2 578;// <o1.8> PB8 <0=> Output <1=> nGCS3 579;// <o1.9> PB9 <0=> Output <1=> nGCS4 580;// <o1.10> PB10 <0=> Output <1=> nGCS5 581;// </e> 582PIOB_SETUP EQU 1 583PCONB_Val EQU 0x000007FF 584 585;// <e> Port C 586;// <o1.0..1> PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK 587;// <o1.2..3> PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO 588;// <o1.4..5> PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI 589;// <o1.6..7> PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK 590;// <o1.8..9> PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7 591;// <o1.10..11> PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6 592;// <o1.12..13> PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5 593;// <o1.14..15> PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4 594;// <o1.16..17> PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1 595;// <o1.18..19> PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1 596;// <o1.20..21> PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1 597;// <o1.22..23> PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1 598;// <o1.24..25> PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1 599;// <o1.26..27> PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1 600;// <o1.28..29> PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0 601;// <o1.30..31> PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0 602;// <h> Pull-up Resistors 603;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled 604;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled 605;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled 606;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled 607;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled 608;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled 609;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled 610;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled 611;// <o2.8> PC8 Pull-up <0=> Enabled <1=> Disabled 612;// <o2.9> PC9 Pull-up <0=> Enabled <1=> Disabled 613;// <o2.10> PC10 Pull-up <0=> Enabled <1=> Disabled 614;// <o2.11> PC11 Pull-up <0=> Enabled <1=> Disabled 615;// <o2.12> PC12 Pull-up <0=> Enabled <1=> Disabled 616;// <o2.13> PC13 Pull-up <0=> Enabled <1=> Disabled 617;// <o2.14> PC14 Pull-up <0=> Enabled <1=> Disabled 618;// <o2.15> PC15 Pull-up <0=> Enabled <1=> Disabled 619;// </h> 620;// </e> 621PIOC_SETUP EQU 1 622PCONC_Val EQU 0xAAAAAAAA 623PUPC_Val EQU 0x00000000 624 625;// <e> Port D 626;// <o1.0..1> PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved 627;// <o1.2..3> PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved 628;// <o1.4..5> PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved 629;// <o1.6..7> PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved 630;// <o1.8..9> PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved 631;// <o1.10..11> PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved 632;// <o1.12..13> PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved 633;// <o1.14..15> PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved 634;// <h> Pull-up Resistors 635;// <o2.0> PD0 Pull-up <0=> Enabled <1=> Disabled 636;// <o2.1> PD1 Pull-up <0=> Enabled <1=> Disabled 637;// <o2.2> PD2 Pull-up <0=> Enabled <1=> Disabled 638;// <o2.3> PD3 Pull-up <0=> Enabled <1=> Disabled 639;// <o2.4> PD4 Pull-up <0=> Enabled <1=> Disabled 640;// <o2.5> PD5 Pull-up <0=> Enabled <1=> Disabled 641;// <o2.6> PD6 Pull-up <0=> Enabled <1=> Disabled 642;// <o2.7> PD7 Pull-up <0=> Enabled <1=> Disabled 643;// </h> 644;// </e> 645PIOD_SETUP EQU 1 646PCOND_Val EQU 0x00000000 647PUPD_Val EQU 0x00000000 648 649;// <e> Port E 650;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout 651;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved 652;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved 653;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved 654;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK 655;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK 656;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6 657;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7 658;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved 659;// <h> Pull-up Resistors 660;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled 661;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled 662;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled 663;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled 664;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled 665;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled 666;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled 667;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled 668;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled 669;// </h> 670;// </e> 671PIOE_SETUP EQU 1 672PCONE_Val EQU 0x00000000 673PUPE_Val EQU 0x00000000 674 675;// <e> Port F 676;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved 677;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved 678;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved 679;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0 680;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0 681;// <o1.10..12> PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD 682;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved 683;// <o1.13..15> PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY 684;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved 685;// <o1.16..18> PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD 686;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved 687;// <o1.19..21> PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK 688;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved 689;// <h> Pull-up Resistors 690;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled 691;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled 692;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled 693;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled 694;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled 695;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled 696;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled 697;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled 698;// <o2.8> PF8 Pull-up <0=> Enabled <1=> Disabled 699;// </h> 700;// </e> 701PIOF_SETUP EQU 1 702PCONF_Val EQU 0x00000000 703PUPF_Val EQU 0x00000000 704 705;// <e> Port G 706;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0 707;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1 708;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2 709;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3 710;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4 711;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5 712;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6 713;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7 714;// <h> Pull-up Resistors 715;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled 716;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled 717;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled 718;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled 719;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled 720;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled 721;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled 722;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled 723;// </h> 724;// </e> 725PIOG_SETUP EQU 1 726PCONG_Val EQU 0x00000000 727PUPG_Val EQU 0x00000000 728 729;// <e> Special Pull-up 730;// <o1.0> SPUCR0: DATA[7:0] Pull-up Resistor 731;// <0=> Enabled <1=> Disabled 732;// <o1.1> SPUCR1: DATA[15:8] Pull-up Resistor 733;// <0=> Enabled <1=> Disabled 734;// <o1.2> HZ@STOP 735;// <0=> Prevoius state of PAD 736;// <1=> HZ @ Stop 737;// </e> 738PSPU_SETUP EQU 1 739SPUCR_Val EQU 0x00000004 740 741;// </e> 742 743 744 PRESERVE8 745 746 747; Area Definition and Entry Point 748; Startup Code must be linked first at Address at which it expects to run. 749 750 AREA RESET, CODE, READONLY 751 ARM 752 753 754; Exception Vectors 755; Mapped to Address 0. 756; Absolute addressing mode must be used. 757; Dummy Handlers are implemented as infinite loops which can be modified. 758 759Vectors LDR PC, Reset_Addr 760 LDR PC, Undef_Addr 761 LDR PC, SWI_Addr 762 LDR PC, PAbt_Addr 763 LDR PC, DAbt_Addr 764 NOP ; Reserved Vector 765 LDR PC, IRQ_Addr 766 LDR PC, FIQ_Addr 767 768Reset_Addr DCD Reset_Handler 769Undef_Addr DCD Undef_Handler 770SWI_Addr DCD SWI_Handler 771PAbt_Addr DCD PAbt_Handler 772DAbt_Addr DCD DAbt_Handler 773 DCD 0 ; Reserved Address 774IRQ_Addr DCD IRQ_Handler 775FIQ_Addr DCD FIQ_Handler 776 777Undef_Handler B Undef_Handler 778SWI_Handler B SWI_Handler 779PAbt_Handler B PAbt_Handler 780DAbt_Handler B DAbt_Handler 781FIQ_Handler B FIQ_Handler 782 783 784; CPU Wrapper and Bus Priorities Configuration 785 IF SYS_SETUP <> 0 786SYS_CFG 787 DCD CPUW_BASE 788 DCD BUSP_BASE 789 DCD SYSCFG_Val 790 DCD NCACHBE0_Val 791 DCD NCACHBE1_Val 792 DCD SBUSCON_Val 793 ENDIF 794 795 796; Memory Controller Configuration 797 IF MC_SETUP <> 0 798MC_CFG 799 DCD BWSCON_Val 800 DCD BANKCON0_Val 801 DCD BANKCON1_Val 802 DCD BANKCON2_Val 803 DCD BANKCON3_Val 804 DCD BANKCON4_Val 805 DCD BANKCON5_Val 806 DCD BANKCON6_Val 807 DCD BANKCON7_Val 808 DCD REFRESH_Val 809 DCD BANKSIZE_Val 810 DCD MRSRB6_Val 811 DCD MRSRB7_Val 812 ENDIF 813 814 815; Clock Management Configuration 816 IF CLK_SETUP <> 0 817CLK_CFG 818 DCD CLK_BASE 819 DCD PLLCON_Val 820 DCD CLKCON_Val 821 DCD CLKSLOW_Val 822 DCD LOCKTIME_Val 823 ENDIF 824 825 826; I/O Configuration 827 IF PIO_SETUP <> 0 828PIO_CFG 829 DCD PCONA_Val 830 DCD PCONB_Val 831 DCD PCONC_Val 832 DCD PCOND_Val 833 DCD PCONE_Val 834 DCD PCONF_Val 835 DCD PCONG_Val 836 DCD PUPC_Val 837 DCD PUPD_Val 838 DCD PUPE_Val 839 DCD PUPF_Val 840 DCD PUPG_Val 841 DCD SPUCR_Val 842 ENDIF 843 844 845; Reset Handler 846 847 EXPORT Reset_Handler 848Reset_Handler 849 850 851 IF SYS_SETUP <> 0 852 ADR R8, SYS_CFG 853 LDMIA R8, {R0-R5} 854 STMIA R0, {R2-R4} 855 STR R5, [R1] 856 ENDIF 857 858 859 IF MC_SETUP <> 0 860 ADR R14, MC_CFG 861 LDMIA R14, {R0-R12} 862 LDR R14, =MC_BASE 863 STMIA R14, {R0-R12} 864 ENDIF 865 866 867 IF CLK_SETUP <> 0 868 ADR R8, CLK_CFG 869 LDMIA R8, {R0-R4} 870 STR R4, [R0, #LOCKTIME_OFS] 871 STR R1, [R0, #PLLCON_OFS] 872 STR R3, [R0, #CLKSLOW_OFS] 873 STR R2, [R0, #CLKCON_OFS] 874 ENDIF 875 876 877 IF WT_SETUP <> 0 878 LDR R0, =WT_BASE 879 LDR R1, =WTCON_Val 880 LDR R2, =WTDAT_Val 881 STR R2, [R0, #WTCNT_OFS] 882 STR R2, [R0, #WTDAT_OFS] 883 STR R1, [R0, #WTCON_OFS] 884 ENDIF 885 886 887 IF PIO_SETUP <> 0 888 ADR R14, PIO_CFG 889 LDMIA R14, {R0-R12} 890 LDR R14, =PIO_BASE 891 892 IF PIOA_SETUP <> 0 893 STR R0, [R14, #PCONA_OFS] 894 ENDIF 895 896 IF PIOB_SETUP <> 0 897 STR R1, [R14, #PCONB_OFS] 898 ENDIF 899 900 IF PIOC_SETUP <> 0 901 STR R2, [R14, #PCONC_OFS] 902 STR R7, [R14, #PUPC_OFS] 903 ENDIF 904 905 IF PIOD_SETUP <> 0 906 STR R3, [R14, #PCOND_OFS] 907 STR R8, [R14, #PUPD_OFS] 908 ENDIF 909 910 IF PIOE_SETUP <> 0 911 STR R4, [R14, #PCONE_OFS] 912 STR R9, [R14, #PUPE_OFS] 913 ENDIF 914 915 IF PIOF_SETUP <> 0 916 STR R5, [R14, #PCONF_OFS] 917 STR R10,[R14, #PUPF_OFS] 918 ENDIF 919 920 IF PIOG_SETUP <> 0 921 STR R6, [R14, #PCONG_OFS] 922 STR R11,[R14, #PUPG_OFS] 923 ENDIF 924 925 IF PSPU_SETUP <> 0 926 STR R12,[R14, #SPUCR_OFS] 927 ENDIF 928 929 ENDIF 930 931 932; Setup Stack for each mode 933 934 LDR R0, =Stack_Top 935 936; Enter Undefined Instruction Mode and set its Stack Pointer 937 MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit 938 MOV SP, R0 939 SUB R0, R0, #UND_Stack_Size 940 941; Enter Abort Mode and set its Stack Pointer 942 MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 943 MOV SP, R0 944 SUB R0, R0, #ABT_Stack_Size 945 946; Enter FIQ Mode and set its Stack Pointer 947 MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit 948 MOV SP, R0 949 SUB R0, R0, #FIQ_Stack_Size 950 951; Enter IRQ Mode and set its Stack Pointer 952 MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit 953 MOV SP, R0 954 SUB R0, R0, #IRQ_Stack_Size 955 956; Enter Supervisor Mode and set its Stack Pointer 957 MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit 958 MOV SP, R0 959 SUB R0, R0, #SVC_Stack_Size 960 961; Enter User Mode and set its Stack Pointer 962 ; MSR CPSR_c, #Mode_USR 963 IF :DEF:__MICROLIB 964 965 EXPORT __initial_sp 966 967 ELSE 968 969 ; MOV SP, R0 970 ; SUB SL, SP, #USR_Stack_Size 971 972 ENDIF 973 974 975; Enter the C code 976 977 IMPORT __main 978 LDR R0, =__main 979 BX R0 980 981 IMPORT rt_interrupt_enter 982 IMPORT rt_interrupt_leave 983 IMPORT rt_thread_switch_interrupt_flag 984 IMPORT rt_interrupt_from_thread 985 IMPORT rt_interrupt_to_thread 986 IMPORT rt_hw_trap_irq 987 988IRQ_Handler PROC 989 EXPORT IRQ_Handler 990 STMFD sp!, {r0-r12,lr} 991 BL rt_interrupt_enter 992 BL rt_hw_trap_irq 993 BL rt_interrupt_leave 994 995 ; if rt_thread_switch_interrupt_flag set, jump to 996 ; rt_hw_context_switch_interrupt_do and don't return 997 LDR r0, =rt_thread_switch_interrupt_flag 998 LDR r1, [r0] 999 CMP r1, #1 1000 BEQ rt_hw_context_switch_interrupt_do 1001 1002 LDMFD sp!, {r0-r12,lr} 1003 SUBS pc, lr, #4 1004 ENDP 1005 1006; /* 1007; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) 1008; */ 1009rt_hw_context_switch_interrupt_do PROC 1010 EXPORT rt_hw_context_switch_interrupt_do 1011 MOV r1, #0 ; clear flag 1012 STR r1, [r0] 1013 1014 LDMFD sp!, {r0-r12,lr}; reload saved registers 1015 STMFD sp!, {r0-r3} ; save r0-r3 1016 MOV r1, sp 1017 ADD sp, sp, #16 ; restore sp 1018 SUB r2, lr, #4 ; save old task's pc to r2 1019 1020 MRS r3, spsr ; get cpsr of interrupt thread 1021 1022 ; switch to SVC mode and no interrupt 1023 MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC 1024 1025 STMFD sp!, {r2} ; push old task's pc 1026 STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 1027 MOV r4, r1 ; Special optimised code below 1028 MOV r5, r3 1029 LDMFD r4!, {r0-r3} 1030 STMFD sp!, {r0-r3} ; push old task's r3-r0 1031 STMFD sp!, {r5} ; push old task's cpsr 1032 MRS r4, spsr 1033 STMFD sp!, {r4} ; push old task's spsr 1034 1035 LDR r4, =rt_interrupt_from_thread 1036 LDR r5, [r4] 1037 STR sp, [r5] ; store sp in preempted tasks's TCB 1038 1039 LDR r6, =rt_interrupt_to_thread 1040 LDR r6, [r6] 1041 LDR sp, [r6] ; get new task's stack pointer 1042 1043 LDMFD sp!, {r4} ; pop new task's spsr 1044 MSR spsr_cxsf, r4 1045 LDMFD sp!, {r4} ; pop new task's psr 1046 MSR cpsr_cxsf, r4 1047 1048 LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc 1049 ENDP 1050 1051 IF :DEF:__MICROLIB 1052 1053 EXPORT __heap_base 1054 EXPORT __heap_limit 1055 1056 ELSE 1057; User Initial Stack & Heap 1058 AREA |.text|, CODE, READONLY 1059 1060 IMPORT __use_two_region_memory 1061 EXPORT __user_initial_stackheap 1062__user_initial_stackheap 1063 1064 LDR R0, = Heap_Mem 1065 LDR R1, =(Stack_Mem + USR_Stack_Size) 1066 LDR R2, = (Heap_Mem + Heap_Size) 1067 LDR R3, = Stack_Mem 1068 BX LR 1069 ENDIF 1070 1071 1072 END 1073