1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2006-03-13 Bernard first version 9 */ 10 11 #include <rthw.h> 12 #include <rtthread.h> 13 #include "s3c24x0.h" 14 15 /** 16 * @addtogroup S3C24X0 17 */ 18 /*@{*/ 19 20 #define ICACHE_MASK (rt_uint32_t)(1 << 12) 21 #define DCACHE_MASK (rt_uint32_t)(1 << 2) 22 23 #ifdef __GNUC__ 24 rt_inline rt_uint32_t cp15_rd(void) 25 { 26 rt_uint32_t i; 27 28 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); 29 return i; 30 } 31 32 rt_inline void cache_enable(rt_uint32_t bit) 33 { 34 __asm__ __volatile__( \ 35 "mrc p15,0,r0,c1,c0,0\n\t" \ 36 "orr r0,r0,%0\n\t" \ 37 "mcr p15,0,r0,c1,c0,0" \ 38 : \ 39 :"r" (bit) \ 40 :"memory"); 41 } 42 43 rt_inline void cache_disable(rt_uint32_t bit) 44 { 45 __asm__ __volatile__( \ 46 "mrc p15,0,r0,c1,c0,0\n\t" \ 47 "bic r0,r0,%0\n\t" \ 48 "mcr p15,0,r0,c1,c0,0" \ 49 : \ 50 :"r" (bit) \ 51 :"memory"); 52 } 53 #endif 54 55 #ifdef __CC_ARM 56 rt_inline rt_uint32_t cp15_rd(void) 57 { 58 rt_uint32_t i; 59 60 __asm 61 { 62 mrc p15, 0, i, c1, c0, 0 63 } 64 65 return i; 66 } 67 68 rt_inline void cache_enable(rt_uint32_t bit) 69 { 70 rt_uint32_t value; 71 72 __asm 73 { 74 mrc p15, 0, value, c1, c0, 0 75 orr value, value, bit 76 mcr p15, 0, value, c1, c0, 0 77 } 78 } 79 80 rt_inline void cache_disable(rt_uint32_t bit) 81 { 82 rt_uint32_t value; 83 84 __asm 85 { 86 mrc p15, 0, value, c1, c0, 0 87 bic value, value, bit 88 mcr p15, 0, value, c1, c0, 0 89 } 90 } 91 #endif 92 93 /** 94 * enable I-Cache 95 * 96 */ 97 void rt_hw_cpu_icache_enable() 98 { 99 cache_enable(ICACHE_MASK); 100 } 101 102 /** 103 * disable I-Cache 104 * 105 */ 106 void rt_hw_cpu_icache_disable() 107 { 108 cache_disable(ICACHE_MASK); 109 } 110 111 /** 112 * return the status of I-Cache 113 * 114 */ 115 rt_base_t rt_hw_cpu_icache_status() 116 { 117 return (cp15_rd() & ICACHE_MASK); 118 } 119 120 /** 121 * enable D-Cache 122 * 123 */ 124 void rt_hw_cpu_dcache_enable() 125 { 126 cache_enable(DCACHE_MASK); 127 } 128 129 /** 130 * disable D-Cache 131 * 132 */ 133 void rt_hw_cpu_dcache_disable() 134 { 135 cache_disable(DCACHE_MASK); 136 } 137 138 /** 139 * return the status of D-Cache 140 * 141 */ 142 rt_base_t rt_hw_cpu_dcache_status() 143 { 144 return (cp15_rd() & DCACHE_MASK); 145 } 146 147 /** 148 * reset cpu by dog's time-out 149 * 150 */ 151 void rt_hw_cpu_reset() 152 { 153 /* Disable all interrupt except the WDT */ 154 INTMSK = (~((rt_uint32_t)1 << INTWDT)); 155 156 /* Disable watchdog */ 157 WTCON = 0x0000; 158 159 /* Initialize watchdog timer count register */ 160 WTCNT = 0x0001; 161 162 /* Enable watchdog timer; assert reset at timer timeout */ 163 WTCON = 0x0021; 164 165 while(1); /* loop forever and wait for reset to happen */ 166 167 /* NEVER REACHED */ 168 } 169 170 /** 171 * shutdown CPU 172 * 173 */ 174 void rt_hw_cpu_shutdown() 175 { 176 rt_uint32_t level; 177 rt_kprintf("shutdown...\n"); 178 179 level = rt_hw_interrupt_disable(); 180 while (level) 181 { 182 RT_ASSERT(0); 183 } 184 } 185 186 /*@}*/ 187