1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2011-01-13 weety 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero/*! 12*10465441SEvalZero * \addtogroup DM36X 13*10465441SEvalZero */ 14*10465441SEvalZero/*@{*/ 15*10465441SEvalZero 16*10465441SEvalZero#define NOINT 0xc0 17*10465441SEvalZero 18*10465441SEvalZero 19*10465441SEvalZero/* 20*10465441SEvalZero * rt_base_t rt_hw_interrupt_disable(); 21*10465441SEvalZero */ 22*10465441SEvalZero.globl rt_hw_interrupt_disable 23*10465441SEvalZerort_hw_interrupt_disable: 24*10465441SEvalZero mrs r0, cpsr 25*10465441SEvalZero orr r1, r0, #NOINT 26*10465441SEvalZero msr cpsr_c, r1 27*10465441SEvalZero bx lr 28*10465441SEvalZero 29*10465441SEvalZero/* 30*10465441SEvalZero * void rt_hw_interrupt_enable(rt_base_t level); 31*10465441SEvalZero */ 32*10465441SEvalZero.globl rt_hw_interrupt_enable 33*10465441SEvalZerort_hw_interrupt_enable: 34*10465441SEvalZero msr cpsr, r0 35*10465441SEvalZero bx lr 36*10465441SEvalZero 37*10465441SEvalZero/* 38*10465441SEvalZero * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); 39*10465441SEvalZero * r0 --> from 40*10465441SEvalZero * r1 --> to 41*10465441SEvalZero */ 42*10465441SEvalZero.globl rt_hw_context_switch 43*10465441SEvalZerort_hw_context_switch: 44*10465441SEvalZero stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) 45*10465441SEvalZero stmfd sp!, {r0-r12, lr} @ push lr & register file 46*10465441SEvalZero 47*10465441SEvalZero mrs r4, cpsr 48*10465441SEvalZero tst lr, #0x01 49*10465441SEvalZero orrne r4, r4, #0x20 @ it's thumb code 50*10465441SEvalZero 51*10465441SEvalZero stmfd sp!, {r4} @ push cpsr 52*10465441SEvalZero 53*10465441SEvalZero str sp, [r0] @ store sp in preempted tasks TCB 54*10465441SEvalZero ldr sp, [r1] @ get new task stack pointer 55*10465441SEvalZero 56*10465441SEvalZero ldmfd sp!, {r4} @ pop new task cpsr to spsr 57*10465441SEvalZero msr spsr_cxsf, r4 58*10465441SEvalZero_do_switch: 59*10465441SEvalZero ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr 60*10465441SEvalZero 61*10465441SEvalZero/* 62*10465441SEvalZero * void rt_hw_context_switch_to(rt_uint32 to); 63*10465441SEvalZero * r0 --> to 64*10465441SEvalZero */ 65*10465441SEvalZero.globl rt_hw_context_switch_to 66*10465441SEvalZerort_hw_context_switch_to: 67*10465441SEvalZero ldr sp, [r0] @ get new task stack pointer 68*10465441SEvalZero 69*10465441SEvalZero ldmfd sp!, {r4} @ pop new task spsr 70*10465441SEvalZero msr spsr_cxsf, r4 71*10465441SEvalZero 72*10465441SEvalZero bic r4, r4, #0x20 @ must be ARM mode 73*10465441SEvalZero msr cpsr_cxsf, r4 74*10465441SEvalZero ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc 75*10465441SEvalZero 76*10465441SEvalZero/* 77*10465441SEvalZero * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); 78*10465441SEvalZero */ 79*10465441SEvalZero.globl rt_thread_switch_interrupt_flag 80*10465441SEvalZero.globl rt_interrupt_from_thread 81*10465441SEvalZero.globl rt_interrupt_to_thread 82*10465441SEvalZero.globl rt_hw_context_switch_interrupt 83*10465441SEvalZerort_hw_context_switch_interrupt: 84*10465441SEvalZero ldr r2, =rt_thread_switch_interrupt_flag 85*10465441SEvalZero ldr r3, [r2] 86*10465441SEvalZero cmp r3, #1 87*10465441SEvalZero beq _reswitch 88*10465441SEvalZero mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 89*10465441SEvalZero str r3, [r2] 90*10465441SEvalZero ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread 91*10465441SEvalZero str r0, [r2] 92*10465441SEvalZero_reswitch: 93*10465441SEvalZero ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread 94*10465441SEvalZero str r1, [r2] 95*10465441SEvalZero bx lr 96