1;------------------------------------------------------------------------------- 2; sys_core.asm 3; 4; (c) Texas Instruments 2009-2013, All rights reserved. 5; 6 7 .text 8 .arm 9 10 .ref _c_int00 11 12 .def _reset 13 .asmfunc 14_reset 15;------------------------------------------------------------------------------- 16; Initialize CPU Registers 17; After reset, the CPU is in the Supervisor mode (M = 10011) 18 mov r0, lr 19 mov r1, #0x0000 20 mov r2, #0x0000 21 mov r3, #0x0000 22 mov r4, #0x0000 23 mov r5, #0x0000 24 mov r6, #0x0000 25 mov r7, #0x0000 26 mov r8, #0x0000 27 mov r9, #0x0000 28 mov r10, #0x0000 29 mov r11, #0x0000 30 mov r12, #0x0000 31 mov r13, #0x0000 32 mrs r1, cpsr 33 msr spsr_cxsf, r1 34 ; Switch to FIQ mode (M = 10001) 35 cps #17 36 mov lr, r0 37 mov r8, #0x0000 38 mov r9, #0x0000 39 mov r10, #0x0000 40 mov r11, #0x0000 41 mov r12, #0x0000 42 mrs r1, cpsr 43 msr spsr_cxsf, r1 44 ; Switch to IRQ mode (M = 10010) 45 cps #18 46 mov lr, r0 47 mrs r1,cpsr 48 msr spsr_cxsf, r1 49 ; Switch to Abort mode (M = 10111) 50 cps #23 51 mov lr, r0 52 mrs r1,cpsr 53 msr spsr_cxsf, r1 54 ; Switch to Undefined Instruction Mode (M = 11011) 55 cps #27 56 mov lr, r0 57 mrs r1,cpsr 58 msr spsr_cxsf, r1 59 ; Switch to System Mode ( Shares User Mode registers ) (M = 11111) 60 cps #31 61 mov lr, r0 62 mrs r1,cpsr 63 msr spsr_cxsf, r1 64 ; Switch back to Supervisor Mode (M = 10011) 65 cps #19 66 67 ; Turn on FPV coprocessor 68 mrc p15, #0x00, r2, c1, c0, #0x02 69 orr r2, r2, #0xF00000 70 mcr p15, #0x00, r2, c1, c0, #0x02 71 72 .if (RT_VFP_LAZY_STACKING) = 0 73 fmrx r2, fpexc 74 orr r2, r2, #0x40000000 75 fmxr fpexc, r2 76 77 fmdrr d0, r1, r1 78 fmdrr d1, r1, r1 79 fmdrr d2, r1, r1 80 fmdrr d3, r1, r1 81 fmdrr d4, r1, r1 82 fmdrr d5, r1, r1 83 fmdrr d6, r1, r1 84 fmdrr d7, r1, r1 85 fmdrr d8, r1, r1 86 fmdrr d9, r1, r1 87 fmdrr d10, r1, r1 88 fmdrr d11, r1, r1 89 fmdrr d12, r1, r1 90 fmdrr d13, r1, r1 91 fmdrr d14, r1, r1 92 fmdrr d15, r1, r1 93 .endif 94 95;------------------------------------------------------------------------------- 96; Initialize Stack Pointers 97 cps #17 98 ldr sp, fiqSp 99 cps #18 100 ldr sp, irqSp 101 cps #23 102 ldr sp, abortSp 103 cps #27 104 ldr sp, undefSp 105 cps #31 106 ldr sp, userSp 107 cps #19 108 ldr sp, svcSp 109 110 bl next1 111next1 112 bl next2 113next2 114 bl next3 115next3 116 bl next4 117next4 118 ldr lr, int00ad 119 bx lr 120 121int00ad .word _c_int00 122userSp .word 0x08000000+0x00001000 123svcSp .word 0x08000000+0x00001000+0x00000100 124fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100 125irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100 126abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100 127undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100 128 129 .endasmfunc 130 131;------------------------------------------------------------------------------- 132; Enable RAM ECC Support 133 134 .def _coreEnableRamEcc_ 135 .asmfunc 136 137_coreEnableRamEcc_ 138 139 stmfd sp!, {r0} 140 mrc p15, #0x00, r0, c1, c0, #0x01 141 orr r0, r0, #0x0C000000 142 mcr p15, #0x00, r0, c1, c0, #0x01 143 ldmfd sp!, {r0} 144 bx lr 145 146 .endasmfunc 147 148 149;------------------------------------------------------------------------------- 150; Disable RAM ECC Support 151 152 .def _coreDisableRamEcc_ 153 .asmfunc 154 155_coreDisableRamEcc_ 156 157 stmfd sp!, {r0} 158 mrc p15, #0x00, r0, c1, c0, #0x01 159 bic r0, r0, #0x0C000000 160 mcr p15, #0x00, r0, c1, c0, #0x01 161 ldmfd sp!, {r0} 162 bx lr 163 164 .endasmfunc 165 166 167;------------------------------------------------------------------------------- 168; Enable Flash ECC Support 169 170 .def _coreEnableFlashEcc_ 171 .asmfunc 172 173_coreEnableFlashEcc_ 174 175 stmfd sp!, {r0} 176 mrc p15, #0x00, r0, c1, c0, #0x01 177 orr r0, r0, #0x02000000 178 dmb 179 mcr p15, #0x00, r0, c1, c0, #0x01 180 ldmfd sp!, {r0} 181 bx lr 182 183 .endasmfunc 184 185 186;------------------------------------------------------------------------------- 187; Disable Flash ECC Support 188 189 .def _coreDisableFlashEcc_ 190 .asmfunc 191 192_coreDisableFlashEcc_ 193 194 stmfd sp!, {r0} 195 mrc p15, #0x00, r0, c1, c0, #0x01 196 bic r0, r0, #0x02000000 197 mcr p15, #0x00, r0, c1, c0, #0x01 198 ldmfd sp!, {r0} 199 bx lr 200 201 .endasmfunc 202 203;------------------------------------------------------------------------------- 204; Get data fault status register 205 206 .def _coreGetDataFault_ 207 .asmfunc 208 209_coreGetDataFault_ 210 211 mrc p15, #0, r0, c5, c0, #0 212 bx lr 213 214 .endasmfunc 215 216 217;------------------------------------------------------------------------------- 218; Clear data fault status register 219 220 .def _coreClearDataFault_ 221 .asmfunc 222 223_coreClearDataFault_ 224 225 stmfd sp!, {r0} 226 mov r0, #0 227 mcr p15, #0, r0, c5, c0, #0 228 ldmfd sp!, {r0} 229 bx lr 230 231 .endasmfunc 232 233 234;------------------------------------------------------------------------------- 235; Get instruction fault status register 236 237 .def _coreGetInstructionFault_ 238 .asmfunc 239 240_coreGetInstructionFault_ 241 242 mrc p15, #0, r0, c5, c0, #1 243 bx lr 244 245 .endasmfunc 246 247 248;------------------------------------------------------------------------------- 249; Clear instruction fault status register 250 251 .def _coreClearInstructionFault_ 252 .asmfunc 253 254_coreClearInstructionFault_ 255 256 stmfd sp!, {r0} 257 mov r0, #0 258 mcr p15, #0, r0, c5, c0, #1 259 ldmfd sp!, {r0} 260 bx lr 261 262 .endasmfunc 263 264 265;------------------------------------------------------------------------------- 266; Get data fault address register 267 268 .def _coreGetDataFaultAddress_ 269 .asmfunc 270 271_coreGetDataFaultAddress_ 272 273 mrc p15, #0, r0, c6, c0, #0 274 bx lr 275 276 .endasmfunc 277 278 279;------------------------------------------------------------------------------- 280; Clear data fault address register 281 282 .def _coreClearDataFaultAddress_ 283 .asmfunc 284 285_coreClearDataFaultAddress_ 286 287 stmfd sp!, {r0} 288 mov r0, #0 289 mcr p15, #0, r0, c6, c0, #0 290 ldmfd sp!, {r0} 291 bx lr 292 293 .endasmfunc 294 295 296;------------------------------------------------------------------------------- 297; Get instruction fault address register 298 299 .def _coreGetInstructionFaultAddress_ 300 .asmfunc 301 302_coreGetInstructionFaultAddress_ 303 304 mrc p15, #0, r0, c6, c0, #2 305 bx lr 306 307 .endasmfunc 308 309 310;------------------------------------------------------------------------------- 311; Clear instruction fault address register 312 313 .def _coreClearInstructionFaultAddress_ 314 .asmfunc 315 316_coreClearInstructionFaultAddress_ 317 318 stmfd sp!, {r0} 319 mov r0, #0 320 mcr p15, #0, r0, c6, c0, #2 321 ldmfd sp!, {r0} 322 bx lr 323 324 .endasmfunc 325 326 327;------------------------------------------------------------------------------- 328; Get auxiliary data fault status register 329 330 .def _coreGetAuxiliaryDataFault_ 331 .asmfunc 332 333_coreGetAuxiliaryDataFault_ 334 335 mrc p15, #0, r0, c5, c1, #0 336 bx lr 337 338 .endasmfunc 339 340 341;------------------------------------------------------------------------------- 342; Clear auxiliary data fault status register 343 344 .def _coreClearAuxiliaryDataFault_ 345 .asmfunc 346 347_coreClearAuxiliaryDataFault_ 348 349 stmfd sp!, {r0} 350 mov r0, #0 351 mcr p15, #0, r0, c5, c1, #0 352 ldmfd sp!, {r0} 353 bx lr 354 355 .endasmfunc 356 357 358;------------------------------------------------------------------------------- 359; Get auxiliary instruction fault status register 360 361 .def _coreGetAuxiliaryInstructionFault_ 362 .asmfunc 363 364_coreGetAuxiliaryInstructionFault_ 365 366 mrc p15, #0, r0, c5, c1, #1 367 bx lr 368 369 .endasmfunc 370 371;------------------------------------------------------------------------------- 372; Clear auxiliary instruction fault status register 373 374 .def _coreClearAuxiliaryInstructionFault_ 375 .asmfunc 376 377_coreClearAuxiliaryInstructionFault_ 378 379 stmfd sp!, {r0} 380 mov r0, #0 381 mrc p15, #0, r0, c5, c1, #1 382 ldmfd sp!, {r0} 383 bx lr 384 385 .endasmfunc 386 387;------------------------------------------------------------------------------- 388; Clear ESM CCM errorss 389 390 .def _esmCcmErrorsClear_ 391 .asmfunc 392 393_esmCcmErrorsClear_ 394 395 stmfd sp!, {r0-r2} 396 ldr r0, ESMSR1_REG ; load the ESMSR1 status register address 397 ldr r2, ESMSR1_ERR_CLR 398 str r2, [r0] ; clear the ESMSR1 register 399 400 ldr r0, ESMSR2_REG ; load the ESMSR2 status register address 401 ldr r2, ESMSR2_ERR_CLR 402 str r2, [r0] ; clear the ESMSR2 register 403 404 ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address 405 ldr r2, ESMSSR2_ERR_CLR 406 str r2, [r0] ; clear the ESMSSR2 register 407 408 ldr r0, ESMKEY_REG ; load the ESMKEY register address 409 mov r2, #0x5 ; load R2 with 0x5 410 str r2, [r0] ; clear the ESMKEY register 411 412 ldr r0, VIM_INTREQ ; load the INTREQ register address 413 ldr r2, VIM_INT_CLR 414 str r2, [r0] ; clear the INTREQ register 415 ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address 416 ldr r2, CCMR4_ERR_CLR 417 str r2, [r0] ; clear the CCMR4 status register 418 ldmfd sp!, {r0-r2} 419 bx lr 420 421ESMSR1_REG .word 0xFFFFF518 422ESMSR2_REG .word 0xFFFFF51C 423ESMSR3_REG .word 0xFFFFF520 424ESMKEY_REG .word 0xFFFFF538 425ESMSSR2_REG .word 0xFFFFF53C 426CCMR4_STAT_REG .word 0xFFFFF600 427ERR_CLR_WRD .word 0xFFFFFFFF 428CCMR4_ERR_CLR .word 0x00010000 429ESMSR1_ERR_CLR .word 0x80000000 430ESMSR2_ERR_CLR .word 0x00000004 431ESMSSR2_ERR_CLR .word 0x00000004 432VIM_INT_CLR .word 0x00000001 433VIM_INTREQ .word 0xFFFFFE20 434 435 .endasmfunc 436 437;------------------------------------------------------------------------------- 438; Work Around for Errata CORTEX-R4#57: 439; 440; Errata Description: 441; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags 442; Workaround: 443; Disable out-of-order single-precision floating point 444; multiply-accumulate instruction completion 445 446 .def _errata_CORTEXR4_57_ 447 .asmfunc 448 449_errata_CORTEXR4_57_ 450 451 push {r0} 452 mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register 453 orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS) 454 mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register 455 pop {r0} 456 bx lr 457 .endasmfunc 458 459;------------------------------------------------------------------------------- 460; Work Around for Errata CORTEX-R4#66: 461; 462; Errata Description: 463; Register Corruption During A Load-Multiple Instruction At 464; an Exception Vector 465; Workaround: 466; Disable out-of-order completion for divide instructions in 467; Auxiliary Control register 468 469 .def _errata_CORTEXR4_66_ 470 .asmfunc 471 472_errata_CORTEXR4_66_ 473 474 push {r0} 475 mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register 476 orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion 477 ; for divide instructions.) 478 mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register 479 pop {r0} 480 bx lr 481 .endasmfunc 482 483 .def turnon_VFP 484 .asmfunc 485turnon_VFP 486 ; Enable FPV 487 STMDB sp!, {r0} 488 fmrx r0, fpexc 489 orr r0, r0, #0x40000000 490 fmxr fpexc, r0 491 LDMIA sp!, {r0} 492 subs pc, lr, #4 493 .endasmfunc 494 495_push_svc_reg .macro 496 sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */ 497 stmia sp, {r0 - r12} ;/* Calling r0-r12 */ 498 mov r0, sp 499 mrs r6, spsr ;/* Save CPSR */ 500 str lr, [r0, #15*4] ;/* Push PC */ 501 str r6, [r0, #16*4] ;/* Push CPSR */ 502 cps #0x13 503 str sp, [r0, #13*4] ;/* Save calling SP */ 504 str lr, [r0, #14*4] ;/* Save calling PC */ 505 .endm 506 507 .ref rt_hw_trap_svc 508 .def vector_svc 509 .asmfunc 510vector_svc: 511 _push_svc_reg 512 bl rt_hw_trap_svc 513 sub pc, pc, #-4 514 .endasmfunc 515 516 .ref rt_hw_trap_pabt 517 .def vector_pabort 518 .asmfunc 519vector_pabort: 520 _push_svc_reg 521 bl rt_hw_trap_pabt 522 sub pc, pc, #-4 523 .endasmfunc 524 525 .ref rt_hw_trap_dabt 526 .def vector_dabort 527 .asmfunc 528vector_dabort: 529 _push_svc_reg 530 bl rt_hw_trap_dabt 531 sub pc, pc, #-4 532 .endasmfunc 533 534 .ref rt_hw_trap_resv 535 .def vector_resv 536 .asmfunc 537vector_resv: 538 _push_svc_reg 539 bl rt_hw_trap_resv 540 sub pc, pc, #-4 541 .endasmfunc 542 543;------------------------------------------------------------------------------- 544; C++ construct table pointers 545 546 .def __TI_PINIT_Base, __TI_PINIT_Limit 547 .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit 548 549__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base 550__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit 551 552;------------------------------------------------------------------------------- 553