xref: /nrf52832-nimble/rt-thread/libcpu/arm/cortex-a/pmu.c (revision 104654410c56c573564690304ae786df310c91fc) 
1*10465441SEvalZero /*
2*10465441SEvalZero  * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero  *
4*10465441SEvalZero  * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero  *
6*10465441SEvalZero  * Change Logs:
7*10465441SEvalZero  * Date           Author       Notes
8*10465441SEvalZero  */
9*10465441SEvalZero #include <rtthread.h>
10*10465441SEvalZero #include "pmu.h"
11*10465441SEvalZero 
rt_hw_pmu_dump_feature(void)12*10465441SEvalZero void rt_hw_pmu_dump_feature(void)
13*10465441SEvalZero {
14*10465441SEvalZero     unsigned long reg;
15*10465441SEvalZero 
16*10465441SEvalZero     reg = rt_hw_pmu_get_control();
17*10465441SEvalZero     rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
18*10465441SEvalZero                reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
19*10465441SEvalZero     RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
20*10465441SEvalZero }
21