1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2012-01-10 bernard porting to AM1808 9 */ 10 11 #include <rtthread.h> 12 #include <rthw.h> 13 #include <board.h> 14 15 #include "cp15.h" 16 17 #define DESC_SEC (0x2) 18 #define CB (3<<2) //cache_on, write_back 19 #define CNB (2<<2) //cache_on, write_through 20 #define NCB (1<<2) //cache_off,WR_BUF on 21 #define NCNB (0<<2) //cache_off,WR_BUF off 22 #define AP_RW (3<<10) //supervisor=RW, user=RW 23 #define AP_RO (2<<10) //supervisor=RW, user=RO 24 #define XN (1<<4) // eXecute Never 25 26 #define DOMAIN_FAULT (0x0) 27 #define DOMAIN_CHK (0x1) 28 #define DOMAIN_NOTCHK (0x3) 29 #define DOMAIN0 (0x0<<5) 30 #define DOMAIN1 (0x1<<5) 31 32 #define DOMAIN0_ATTR (DOMAIN_CHK<<0) 33 #define DOMAIN1_ATTR (DOMAIN_FAULT<<2) 34 35 /* Read/Write, cache, write back */ 36 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) 37 /* Read/Write, cache, write through */ 38 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) 39 /* Read/Write without cache and write buffer */ 40 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) 41 /* Read/Write without cache and write buffer, no execute */ 42 #define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) 43 /* Read/Write without cache and write buffer */ 44 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) 45 46 /* dump 2nd level page table */ 47 void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) 48 { 49 int i; 50 int fcnt = 0; 51 52 for (i = 0; i < 256; i++) 53 { 54 rt_uint32_t pte2 = ptb[i]; 55 if ((pte2 & 0x3) == 0) 56 { 57 if (fcnt == 0) 58 rt_kprintf(" "); 59 rt_kprintf("%04x: ", i); 60 fcnt++; 61 if (fcnt == 16) 62 { 63 rt_kprintf("fault\n"); 64 fcnt = 0; 65 } 66 continue; 67 } 68 if (fcnt != 0) 69 { 70 rt_kprintf("fault\n"); 71 fcnt = 0; 72 } 73 74 rt_kprintf(" %04x: %x: ", i, pte2); 75 if ((pte2 & 0x3) == 0x1) 76 { 77 rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", 78 ((pte2 >> 7) | (pte2 >> 4))& 0xf, 79 (pte2 >> 15) & 0x1, 80 ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); 81 } 82 else 83 { 84 rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", 85 ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, 86 ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); 87 } 88 } 89 } 90 91 void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) 92 { 93 int i; 94 int fcnt = 0; 95 96 rt_kprintf("page table@%p\n", ptb); 97 for (i = 0; i < 1024*4; i++) 98 { 99 rt_uint32_t pte1 = ptb[i]; 100 if ((pte1 & 0x3) == 0) 101 { 102 rt_kprintf("%03x: ", i); 103 fcnt++; 104 if (fcnt == 16) 105 { 106 rt_kprintf("fault\n"); 107 fcnt = 0; 108 } 109 continue; 110 } 111 if (fcnt != 0) 112 { 113 rt_kprintf("fault\n"); 114 fcnt = 0; 115 } 116 117 rt_kprintf("%03x: %08x: ", i, pte1); 118 if ((pte1 & 0x3) == 0x3) 119 { 120 rt_kprintf("LPAE\n"); 121 } 122 else if ((pte1 & 0x3) == 0x1) 123 { 124 rt_kprintf("pte,ns:%d,domain:%d\n", 125 (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); 126 /* 127 *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) 128 * - 0x80000000 + 0xC0000000)); 129 */ 130 } 131 else if (pte1 & (1 << 18)) 132 { 133 rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", 134 (pte1 >> 19) & 0x1, 135 ((pte1 >> 13) | (pte1 >> 10))& 0xf, 136 (pte1 >> 4) & 0x1, 137 ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); 138 } 139 else 140 { 141 rt_kprintf("section,ns:%d,ap:%x," 142 "xn:%d,texcb:%02x,domain:%d\n", 143 (pte1 >> 19) & 0x1, 144 ((pte1 >> 13) | (pte1 >> 10))& 0xf, 145 (pte1 >> 4) & 0x1, 146 (((pte1 & (0x7 << 12)) >> 10) | 147 ((pte1 & 0x0c) >> 2)) & 0x1f, 148 (pte1 >> 5) & 0xf); 149 } 150 } 151 } 152 153 /* level1 page table, each entry for 1MB memory. */ 154 volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); 155 void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, 156 rt_uint32_t vaddrEnd, 157 rt_uint32_t paddrStart, 158 rt_uint32_t attr) 159 { 160 volatile rt_uint32_t *pTT; 161 volatile int i, nSec; 162 pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); 163 nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); 164 for(i = 0; i <= nSec; i++) 165 { 166 *pTT = attr | (((paddrStart >> 20) + i) << 20); 167 pTT++; 168 } 169 } 170 171 unsigned long rt_hw_set_domain_register(unsigned long domain_val) 172 { 173 unsigned long old_domain; 174 175 asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); 176 asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); 177 178 return old_domain; 179 } 180 181 void rt_hw_mmu_init(void) 182 { 183 rt_hw_cpu_dcache_disable(); 184 rt_hw_cpu_icache_disable(); 185 rt_cpu_mmu_disable(); 186 187 /* set page table */ 188 /* 4G 1:1 memory */ 189 rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB); 190 /* IO memory region */ 191 rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN); 192 193 /*rt_hw_cpu_dump_page_table(MMUTable);*/ 194 rt_hw_set_domain_register(0x55555555); 195 196 rt_cpu_tlb_set(MMUTable); 197 198 rt_cpu_mmu_enable(); 199 200 rt_hw_cpu_icache_enable(); 201 rt_hw_cpu_dcache_enable(); 202 } 203 204