1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-07-06 Bernard first version 9 * 2014-04-03 Grissiom port to VMM 10 */ 11 12 #include <rthw.h> 13 #include <rtthread.h> 14 15 #include <irq_numbers.h> 16 #include <interrupt.h> 17 18 #include <gic.h> 19 #include "cp15.h" 20 21 #define MAX_HANDLERS IMX_INTERRUPT_COUNT 22 23 extern volatile rt_uint8_t rt_interrupt_nest; 24 25 /* exception and interrupt handler table */ 26 struct rt_irq_desc isr_table[MAX_HANDLERS]; 27 28 rt_uint32_t rt_interrupt_from_thread; 29 rt_uint32_t rt_interrupt_to_thread; 30 rt_uint32_t rt_thread_switch_interrupt_flag; 31 32 extern void rt_cpu_vector_set_base(unsigned int addr); 33 extern int system_vectors; 34 35 /* keep compatible with platform SDK */ 36 void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) 37 { 38 rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown"); 39 } 40 41 void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) 42 { 43 gic_set_irq_priority(irq_id, priority); 44 gic_set_irq_security(irq_id, false); // set IRQ as non-secure 45 gic_set_cpu_target(irq_id, cpu_id, true); 46 gic_enable_irq(irq_id, true); 47 } 48 49 void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) 50 { 51 gic_enable_irq(irq_id, false); 52 gic_set_cpu_target(irq_id, cpu_id, false); 53 } 54 55 static void rt_hw_vector_init(void) 56 { 57 int sctrl; 58 unsigned int *src = (unsigned int *)&system_vectors; 59 60 /* C12-C0 is only active when SCTLR.V = 0 */ 61 asm volatile ("mrc p15, #0, %0, c1, c0, #0" 62 :"=r" (sctrl)); 63 sctrl &= ~(1 << 13); 64 asm volatile ("mcr p15, #0, %0, c1, c0, #0" 65 : 66 :"r" (sctrl)); 67 68 asm volatile ("mcr p15, #0, %0, c12, c0, #0" 69 : 70 :"r" (src)); 71 } 72 73 /** 74 * This function will initialize hardware interrupt 75 */ 76 void rt_hw_interrupt_init(void) 77 { 78 rt_hw_vector_init(); 79 gic_init(); 80 81 /* init interrupt nest, and context in thread sp */ 82 rt_interrupt_nest = 0; 83 rt_interrupt_from_thread = 0; 84 rt_interrupt_to_thread = 0; 85 rt_thread_switch_interrupt_flag = 0; 86 } 87 88 /** 89 * This function will mask a interrupt. 90 * @param vector the interrupt number 91 */ 92 void rt_hw_interrupt_mask(int vector) 93 { 94 disable_interrupt(vector, 0); 95 } 96 97 /** 98 * This function will un-mask a interrupt. 99 * @param vector the interrupt number 100 */ 101 void rt_hw_interrupt_umask(int vector) 102 { 103 enable_interrupt(vector, 0, 0); 104 } 105 106 /** 107 * This function will install a interrupt service routine to a interrupt. 108 * @param vector the interrupt number 109 * @param new_handler the interrupt service routine to be installed 110 * @param old_handler the old interrupt service routine 111 */ 112 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 113 void *param, const char *name) 114 { 115 rt_isr_handler_t old_handler = RT_NULL; 116 117 if (vector < MAX_HANDLERS) 118 { 119 old_handler = isr_table[vector].handler; 120 121 if (handler != RT_NULL) 122 { 123 #ifdef RT_USING_INTERRUPT_INFO 124 rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); 125 #endif /* RT_USING_INTERRUPT_INFO */ 126 isr_table[vector].handler = handler; 127 isr_table[vector].param = param; 128 } 129 // arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); 130 } 131 132 return old_handler; 133 } 134 135 /** 136 * Trigger a software IRQ 137 * 138 * Since we are running in single core, the target CPU are always CPU0. 139 */ 140 void rt_hw_interrupt_trigger(int vector) 141 { 142 // arm_gic_trigger(0, 1, vector); 143 } 144 145 void rt_hw_interrupt_clear(int vector) 146 { 147 gic_write_end_of_irq(vector); 148 } 149