1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2013-07-05 Bernard the first version 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero.globl rt_cpu_get_smp_id 12*10465441SEvalZerort_cpu_get_smp_id: 13*10465441SEvalZero mrc p15, #0, r0, c0, c0, #5 14*10465441SEvalZero bx lr 15*10465441SEvalZero 16*10465441SEvalZero.globl rt_cpu_vector_set_base 17*10465441SEvalZerort_cpu_vector_set_base: 18*10465441SEvalZero mcr p15, #0, r0, c12, c0, #0 19*10465441SEvalZero dsb 20*10465441SEvalZero bx lr 21*10465441SEvalZero 22*10465441SEvalZero.globl rt_hw_cpu_dcache_enable 23*10465441SEvalZerort_hw_cpu_dcache_enable: 24*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 25*10465441SEvalZero orr r0, r0, #0x00000004 26*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 27*10465441SEvalZero bx lr 28*10465441SEvalZero 29*10465441SEvalZero.globl rt_hw_cpu_icache_enable 30*10465441SEvalZerort_hw_cpu_icache_enable: 31*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 32*10465441SEvalZero orr r0, r0, #0x00001000 33*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 34*10465441SEvalZero bx lr 35*10465441SEvalZero 36*10465441SEvalZero_FLD_MAX_WAY: 37*10465441SEvalZero .word 0x3ff 38*10465441SEvalZero_FLD_MAX_IDX: 39*10465441SEvalZero .word 0x7ff 40*10465441SEvalZero 41*10465441SEvalZero.globl rt_cpu_dcache_clean_flush 42*10465441SEvalZerort_cpu_dcache_clean_flush: 43*10465441SEvalZero push {r4-r11} 44*10465441SEvalZero dmb 45*10465441SEvalZero mrc p15, #1, r0, c0, c0, #1 @ read clid register 46*10465441SEvalZero ands r3, r0, #0x7000000 @ get level of coherency 47*10465441SEvalZero mov r3, r3, lsr #23 48*10465441SEvalZero beq finished 49*10465441SEvalZero mov r10, #0 50*10465441SEvalZeroloop1: 51*10465441SEvalZero add r2, r10, r10, lsr #1 52*10465441SEvalZero mov r1, r0, lsr r2 53*10465441SEvalZero and r1, r1, #7 54*10465441SEvalZero cmp r1, #2 55*10465441SEvalZero blt skip 56*10465441SEvalZero mcr p15, #2, r10, c0, c0, #0 57*10465441SEvalZero isb 58*10465441SEvalZero mrc p15, #1, r1, c0, c0, #0 59*10465441SEvalZero and r2, r1, #7 60*10465441SEvalZero add r2, r2, #4 61*10465441SEvalZero ldr r4, _FLD_MAX_WAY 62*10465441SEvalZero ands r4, r4, r1, lsr #3 63*10465441SEvalZero clz r5, r4 64*10465441SEvalZero ldr r7, _FLD_MAX_IDX 65*10465441SEvalZero ands r7, r7, r1, lsr #13 66*10465441SEvalZeroloop2: 67*10465441SEvalZero mov r9, r4 68*10465441SEvalZeroloop3: 69*10465441SEvalZero orr r11, r10, r9, lsl r5 70*10465441SEvalZero orr r11, r11, r7, lsl r2 71*10465441SEvalZero mcr p15, #0, r11, c7, c14, #2 72*10465441SEvalZero subs r9, r9, #1 73*10465441SEvalZero bge loop3 74*10465441SEvalZero subs r7, r7, #1 75*10465441SEvalZero bge loop2 76*10465441SEvalZeroskip: 77*10465441SEvalZero add r10, r10, #2 78*10465441SEvalZero cmp r3, r10 79*10465441SEvalZero bgt loop1 80*10465441SEvalZero 81*10465441SEvalZerofinished: 82*10465441SEvalZero dsb 83*10465441SEvalZero isb 84*10465441SEvalZero pop {r4-r11} 85*10465441SEvalZero bx lr 86*10465441SEvalZero 87*10465441SEvalZero.globl rt_hw_cpu_dcache_disable 88*10465441SEvalZerort_hw_cpu_dcache_disable: 89*10465441SEvalZero push {r4-r11, lr} 90*10465441SEvalZero bl rt_cpu_dcache_clean_flush 91*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 92*10465441SEvalZero bic r0, r0, #0x00000004 93*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 94*10465441SEvalZero pop {r4-r11, lr} 95*10465441SEvalZero bx lr 96*10465441SEvalZero 97*10465441SEvalZero.globl rt_hw_cpu_icache_disable 98*10465441SEvalZerort_hw_cpu_icache_disable: 99*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 100*10465441SEvalZero bic r0, r0, #0x00001000 101*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 102*10465441SEvalZero bx lr 103*10465441SEvalZero 104*10465441SEvalZero.globl rt_cpu_mmu_disable 105*10465441SEvalZerort_cpu_mmu_disable: 106*10465441SEvalZero mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 107*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 108*10465441SEvalZero bic r0, r0, #1 109*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit 110*10465441SEvalZero dsb 111*10465441SEvalZero bx lr 112*10465441SEvalZero 113*10465441SEvalZero.globl rt_cpu_mmu_enable 114*10465441SEvalZerort_cpu_mmu_enable: 115*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 116*10465441SEvalZero orr r0, r0, #0x001 117*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit 118*10465441SEvalZero dsb 119*10465441SEvalZero bx lr 120*10465441SEvalZero 121*10465441SEvalZero.globl rt_cpu_tlb_set 122*10465441SEvalZerort_cpu_tlb_set: 123*10465441SEvalZero mcr p15, #0, r0, c2, c0, #0 124*10465441SEvalZero dmb 125*10465441SEvalZero bx lr 126