1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero */ 9*10465441SEvalZero #ifndef __ARMV7_H__ 10*10465441SEvalZero #define __ARMV7_H__ 11*10465441SEvalZero 12*10465441SEvalZero /* the exception stack without VFP registers */ 13*10465441SEvalZero struct rt_hw_exp_stack 14*10465441SEvalZero { 15*10465441SEvalZero unsigned long r0; 16*10465441SEvalZero unsigned long r1; 17*10465441SEvalZero unsigned long r2; 18*10465441SEvalZero unsigned long r3; 19*10465441SEvalZero unsigned long r4; 20*10465441SEvalZero unsigned long r5; 21*10465441SEvalZero unsigned long r6; 22*10465441SEvalZero unsigned long r7; 23*10465441SEvalZero unsigned long r8; 24*10465441SEvalZero unsigned long r9; 25*10465441SEvalZero unsigned long r10; 26*10465441SEvalZero unsigned long fp; 27*10465441SEvalZero unsigned long ip; 28*10465441SEvalZero unsigned long sp; 29*10465441SEvalZero unsigned long lr; 30*10465441SEvalZero unsigned long pc; 31*10465441SEvalZero unsigned long cpsr; 32*10465441SEvalZero }; 33*10465441SEvalZero 34*10465441SEvalZero struct rt_hw_stack 35*10465441SEvalZero { 36*10465441SEvalZero unsigned long cpsr; 37*10465441SEvalZero unsigned long r0; 38*10465441SEvalZero unsigned long r1; 39*10465441SEvalZero unsigned long r2; 40*10465441SEvalZero unsigned long r3; 41*10465441SEvalZero unsigned long r4; 42*10465441SEvalZero unsigned long r5; 43*10465441SEvalZero unsigned long r6; 44*10465441SEvalZero unsigned long r7; 45*10465441SEvalZero unsigned long r8; 46*10465441SEvalZero unsigned long r9; 47*10465441SEvalZero unsigned long r10; 48*10465441SEvalZero unsigned long fp; 49*10465441SEvalZero unsigned long ip; 50*10465441SEvalZero unsigned long lr; 51*10465441SEvalZero unsigned long pc; 52*10465441SEvalZero }; 53*10465441SEvalZero 54*10465441SEvalZero #define USERMODE 0x10 55*10465441SEvalZero #define FIQMODE 0x11 56*10465441SEvalZero #define IRQMODE 0x12 57*10465441SEvalZero #define SVCMODE 0x13 58*10465441SEvalZero #define MONITORMODE 0x16 59*10465441SEvalZero #define ABORTMODE 0x17 60*10465441SEvalZero #define HYPMODE 0x1b 61*10465441SEvalZero #define UNDEFMODE 0x1b 62*10465441SEvalZero #define MODEMASK 0x1f 63*10465441SEvalZero #define NOINT 0xc0 64*10465441SEvalZero 65*10465441SEvalZero #define T_Bit (1<<5) 66*10465441SEvalZero #define F_Bit (1<<6) 67*10465441SEvalZero #define I_Bit (1<<7) 68*10465441SEvalZero #define A_Bit (1<<8) 69*10465441SEvalZero #define E_Bit (1<<9) 70*10465441SEvalZero #define J_Bit (1<<24) 71*10465441SEvalZero 72*10465441SEvalZero #endif 73