1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-09-15 Bernard first version 9 */ 10 11 #include <rthw.h> 12 #include <rtthread.h> 13 #include "am33xx.h" 14 15 /** 16 * @addtogroup AM33xx 17 */ 18 /*@{*/ 19 20 #define ICACHE_MASK (rt_uint32_t)(1 << 12) 21 #define DCACHE_MASK (rt_uint32_t)(1 << 2) 22 23 #if defined(__CC_ARM) 24 rt_inline rt_uint32_t cp15_rd(void) 25 { 26 rt_uint32_t i; 27 28 __asm 29 { 30 mrc p15, 0, i, c1, c0, 0 31 } 32 33 return i; 34 } 35 36 rt_inline void cache_enable(rt_uint32_t bit) 37 { 38 rt_uint32_t value; 39 40 __asm 41 { 42 mrc p15, 0, value, c1, c0, 0 43 orr value, value, bit 44 mcr p15, 0, value, c1, c0, 0 45 } 46 } 47 48 rt_inline void cache_disable(rt_uint32_t bit) 49 { 50 rt_uint32_t value; 51 52 __asm 53 { 54 mrc p15, 0, value, c1, c0, 0 55 bic value, value, bit 56 mcr p15, 0, value, c1, c0, 0 57 } 58 } 59 #elif defined(__GNUC__) 60 rt_inline rt_uint32_t cp15_rd(void) 61 { 62 rt_uint32_t i; 63 64 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); 65 return i; 66 } 67 68 rt_inline void cache_enable(rt_uint32_t bit) 69 { 70 __asm__ __volatile__( \ 71 "mrc p15,0,r0,c1,c0,0\n\t" \ 72 "orr r0,r0,%0\n\t" \ 73 "mcr p15,0,r0,c1,c0,0" \ 74 : \ 75 :"r" (bit) \ 76 :"memory"); 77 } 78 79 rt_inline void cache_disable(rt_uint32_t bit) 80 { 81 __asm__ __volatile__( \ 82 "mrc p15,0,r0,c1,c0,0\n\t" \ 83 "bic r0,r0,%0\n\t" \ 84 "mcr p15,0,r0,c1,c0,0" \ 85 : \ 86 :"r" (bit) \ 87 :"memory"); 88 } 89 #endif 90 91 92 #if defined(__CC_ARM)|(__GNUC__) 93 /** 94 * enable I-Cache 95 * 96 */ 97 void rt_hw_cpu_icache_enable() 98 { 99 cache_enable(ICACHE_MASK); 100 } 101 102 /** 103 * disable I-Cache 104 * 105 */ 106 void rt_hw_cpu_icache_disable() 107 { 108 cache_disable(ICACHE_MASK); 109 } 110 111 /** 112 * return the status of I-Cache 113 * 114 */ 115 rt_base_t rt_hw_cpu_icache_status() 116 { 117 return (cp15_rd() & ICACHE_MASK); 118 } 119 120 /** 121 * enable D-Cache 122 * 123 */ 124 void rt_hw_cpu_dcache_enable() 125 { 126 cache_enable(DCACHE_MASK); 127 } 128 129 /** 130 * disable D-Cache 131 * 132 */ 133 void rt_hw_cpu_dcache_disable() 134 { 135 cache_disable(DCACHE_MASK); 136 } 137 138 /** 139 * return the status of D-Cache 140 * 141 */ 142 rt_base_t rt_hw_cpu_dcache_status() 143 { 144 return (cp15_rd() & DCACHE_MASK); 145 } 146 #endif 147 148 /** 149 * shutdown CPU 150 * 151 */ 152 void rt_hw_cpu_shutdown() 153 { 154 rt_uint32_t level; 155 rt_kprintf("shutdown...\n"); 156 157 level = rt_hw_interrupt_disable(); 158 while (level) 159 { 160 RT_ASSERT(0); 161 } 162 } 163 164 /*@}*/ 165