1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2015-04-06 zchong change to iar compiler from convert from cp15_gcc.S 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero SECTION .text:CODE:NOROOT(2) 12*10465441SEvalZero 13*10465441SEvalZero ARM 14*10465441SEvalZero 15*10465441SEvalZero EXPORT rt_cpu_vector_set_base 16*10465441SEvalZerort_cpu_vector_set_base: 17*10465441SEvalZero MCR p15, #0, r0, c12, c0, #0 18*10465441SEvalZero DSB 19*10465441SEvalZero BX lr 20*10465441SEvalZero 21*10465441SEvalZero EXPORT rt_cpu_vector_get_base 22*10465441SEvalZerort_cpu_vector_get_base: 23*10465441SEvalZero MRC p15, #0, r0, c12, c0, #0 24*10465441SEvalZero BX lr 25*10465441SEvalZero 26*10465441SEvalZero EXPORT rt_cpu_get_sctlr 27*10465441SEvalZerort_cpu_get_sctlr: 28*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 29*10465441SEvalZero BX lr 30*10465441SEvalZero 31*10465441SEvalZero EXPORT rt_cpu_dcache_enable 32*10465441SEvalZerort_cpu_dcache_enable: 33*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 34*10465441SEvalZero ORR r0, r0, #0x00000004 35*10465441SEvalZero MCR p15, #0, r0, c1, c0, #0 36*10465441SEvalZero BX lr 37*10465441SEvalZero 38*10465441SEvalZero EXPORT rt_cpu_icache_enable 39*10465441SEvalZerort_cpu_icache_enable: 40*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 41*10465441SEvalZero ORR r0, r0, #0x00001000 42*10465441SEvalZero MCR p15, #0, r0, c1, c0, #0 43*10465441SEvalZero BX lr 44*10465441SEvalZero 45*10465441SEvalZero;_FLD_MAX_WAY DEFINE 0x3ff 46*10465441SEvalZero;_FLD_MAX_IDX DEFINE 0x7ff 47*10465441SEvalZero 48*10465441SEvalZero 49*10465441SEvalZero EXPORT rt_cpu_dcache_clean_flush 50*10465441SEvalZerort_cpu_dcache_clean_flush: 51*10465441SEvalZero PUSH {r4-r11} 52*10465441SEvalZero DMB 53*10465441SEvalZero MRC p15, #1, r0, c0, c0, #1 ; read clid register 54*10465441SEvalZero ANDS r3, r0, #0x7000000 ; get level of coherency 55*10465441SEvalZero MOV r3, r3, lsr #23 56*10465441SEvalZero BEQ finished 57*10465441SEvalZero MOV r10, #0 58*10465441SEvalZeroloop1: 59*10465441SEvalZero ADD r2, r10, r10, lsr #1 60*10465441SEvalZero MOV r1, r0, lsr r2 61*10465441SEvalZero AND r1, r1, #7 62*10465441SEvalZero CMP r1, #2 63*10465441SEvalZero BLT skip 64*10465441SEvalZero MCR p15, #2, r10, c0, c0, #0 65*10465441SEvalZero ISB 66*10465441SEvalZero MRC p15, #1, r1, c0, c0, #0 67*10465441SEvalZero AND r2, r1, #7 68*10465441SEvalZero ADD r2, r2, #4 69*10465441SEvalZero ;LDR r4, _FLD_MAX_WAY 70*10465441SEvalZero LDR r4, =0x3FF 71*10465441SEvalZero ANDS r4, r4, r1, lsr #3 72*10465441SEvalZero CLZ r5, r4 73*10465441SEvalZero ;LDR r7, _FLD_MAX_IDX 74*10465441SEvalZero LDR r7, =0x7FF 75*10465441SEvalZero ANDS r7, r7, r1, lsr #13 76*10465441SEvalZeroloop2: 77*10465441SEvalZero MOV r9, r4 78*10465441SEvalZeroloop3: 79*10465441SEvalZero ORR r11, r10, r9, lsl r5 80*10465441SEvalZero ORR r11, r11, r7, lsl r2 81*10465441SEvalZero MCR p15, #0, r11, c7, c14, #2 82*10465441SEvalZero SUBS r9, r9, #1 83*10465441SEvalZero BGE loop3 84*10465441SEvalZero SUBS r7, r7, #1 85*10465441SEvalZero BGE loop2 86*10465441SEvalZeroskip: 87*10465441SEvalZero ADD r10, r10, #2 88*10465441SEvalZero CMP r3, r10 89*10465441SEvalZero BGT loop1 90*10465441SEvalZero 91*10465441SEvalZerofinished: 92*10465441SEvalZero DSB 93*10465441SEvalZero ISB 94*10465441SEvalZero POP {r4-r11} 95*10465441SEvalZero BX lr 96*10465441SEvalZero 97*10465441SEvalZero 98*10465441SEvalZero EXPORT rt_cpu_dcache_disable 99*10465441SEvalZerort_cpu_dcache_disable: 100*10465441SEvalZero PUSH {r4-r11, lr} 101*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 102*10465441SEvalZero BIC r0, r0, #0x00000004 103*10465441SEvalZero MCR p15, #0, r0, c1, c0, #0 104*10465441SEvalZero BL rt_cpu_dcache_clean_flush 105*10465441SEvalZero POP {r4-r11, lr} 106*10465441SEvalZero BX lr 107*10465441SEvalZero 108*10465441SEvalZero 109*10465441SEvalZero EXPORT rt_cpu_icache_disable 110*10465441SEvalZerort_cpu_icache_disable: 111*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 112*10465441SEvalZero BIC r0, r0, #0x00001000 113*10465441SEvalZero MCR p15, #0, r0, c1, c0, #0 114*10465441SEvalZero BX lr 115*10465441SEvalZero 116*10465441SEvalZero EXPORT rt_cpu_mmu_disable 117*10465441SEvalZerort_cpu_mmu_disable: 118*10465441SEvalZero MCR p15, #0, r0, c8, c7, #0 ; invalidate tlb 119*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 120*10465441SEvalZero BIC r0, r0, #1 121*10465441SEvalZero MCR p15, #0, r0, c1, c0, #0 ; clear mmu bit 122*10465441SEvalZero DSB 123*10465441SEvalZero BX lr 124*10465441SEvalZero 125*10465441SEvalZero EXPORT rt_cpu_mmu_enable 126*10465441SEvalZerort_cpu_mmu_enable: 127*10465441SEvalZero MRC p15, #0, r0, c1, c0, #0 128*10465441SEvalZero ORR r0, r0, #0x001 129*10465441SEvalZero MCR p15, #0, r0, c1, c0, #0 ; set mmu enable bit 130*10465441SEvalZero DSB 131*10465441SEvalZero BX lr 132*10465441SEvalZero 133*10465441SEvalZero EXPORT rt_cpu_tlb_set 134*10465441SEvalZerort_cpu_tlb_set: 135*10465441SEvalZero MCR p15, #0, r0, c2, c0, #0 136*10465441SEvalZero DMB 137*10465441SEvalZero BX lr 138*10465441SEvalZero 139*10465441SEvalZero END 140