1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero */ 9*10465441SEvalZero #ifndef __RT_SERIAL_H__ 10*10465441SEvalZero #define __RT_SERIAL_H__ 11*10465441SEvalZero 12*10465441SEvalZero #ifndef AT91C_BASE_US0 13*10465441SEvalZero #define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address 14*10465441SEvalZero #endif 15*10465441SEvalZero 16*10465441SEvalZero #ifndef AT91C_BASE_US1 17*10465441SEvalZero #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address 18*10465441SEvalZero #endif 19*10465441SEvalZero 20*10465441SEvalZero #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ 21*10465441SEvalZero #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ 22*10465441SEvalZero #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ 23*10465441SEvalZero #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ 24*10465441SEvalZero #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ 25*10465441SEvalZero #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ 26*10465441SEvalZero #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ 27*10465441SEvalZero #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ 28*10465441SEvalZero #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ 29*10465441SEvalZero 30*10465441SEvalZero #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ 31*10465441SEvalZero #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ 32*10465441SEvalZero #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ 33*10465441SEvalZero #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ 34*10465441SEvalZero #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ 35*10465441SEvalZero #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ 36*10465441SEvalZero #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ 37*10465441SEvalZero #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ 38*10465441SEvalZero 39*10465441SEvalZero #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ 40*10465441SEvalZero #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ 41*10465441SEvalZero #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ 42*10465441SEvalZero #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ 43*10465441SEvalZero 44*10465441SEvalZero #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ 45*10465441SEvalZero #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ 46*10465441SEvalZero #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ 47*10465441SEvalZero #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ 48*10465441SEvalZero 49*10465441SEvalZero #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ 50*10465441SEvalZero #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ 51*10465441SEvalZero #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ 52*10465441SEvalZero #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ 53*10465441SEvalZero #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ 54*10465441SEvalZero #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ 55*10465441SEvalZero 56*10465441SEvalZero #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ 57*10465441SEvalZero #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ 58*10465441SEvalZero #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ 59*10465441SEvalZero 60*10465441SEvalZero #define MCK 48054857 61*10465441SEvalZero #define BR 115200 /* Baud Rate */ 62*10465441SEvalZero #define BRD (MCK/16/BR) /* Baud Rate Divisor */ 63*10465441SEvalZero 64*10465441SEvalZero #endif 65