1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2006-08-23 Bernard first version 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero #ifndef __AT91SAM7S_H__ 12*10465441SEvalZero #define __AT91SAM7S_H__ 13*10465441SEvalZero 14*10465441SEvalZero #ifdef __cplusplus 15*10465441SEvalZero extern "C" { 16*10465441SEvalZero #endif 17*10465441SEvalZero 18*10465441SEvalZero #define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ 19*10465441SEvalZero 20*10465441SEvalZero /* ========== Register definition for TC0 peripheral ========== */ 21*10465441SEvalZero #define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ 22*10465441SEvalZero #define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ 23*10465441SEvalZero #define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ 24*10465441SEvalZero #define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ 25*10465441SEvalZero #define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ 26*10465441SEvalZero #define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ 27*10465441SEvalZero #define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ 28*10465441SEvalZero #define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ 29*10465441SEvalZero #define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ 30*10465441SEvalZero #define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ 31*10465441SEvalZero 32*10465441SEvalZero /* ========== Register definition for TC1 peripheral ========== */ 33*10465441SEvalZero #define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ 34*10465441SEvalZero #define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ 35*10465441SEvalZero #define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ 36*10465441SEvalZero #define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ 37*10465441SEvalZero #define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ 38*10465441SEvalZero #define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ 39*10465441SEvalZero #define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ 40*10465441SEvalZero #define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ 41*10465441SEvalZero #define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ 42*10465441SEvalZero #define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ 43*10465441SEvalZero 44*10465441SEvalZero /* ========== Register definition for TC2 peripheral ========== */ 45*10465441SEvalZero #define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ 46*10465441SEvalZero #define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ 47*10465441SEvalZero #define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ 48*10465441SEvalZero #define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ 49*10465441SEvalZero #define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ 50*10465441SEvalZero #define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ 51*10465441SEvalZero #define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ 52*10465441SEvalZero #define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ 53*10465441SEvalZero #define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ 54*10465441SEvalZero #define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ 55*10465441SEvalZero 56*10465441SEvalZero /* ========== Register definition for PITC peripheral ========== */ 57*10465441SEvalZero #define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ 58*10465441SEvalZero #define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ 59*10465441SEvalZero #define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ 60*10465441SEvalZero #define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ 61*10465441SEvalZero 62*10465441SEvalZero /* ========== Register definition for UDP peripheral ========== */ 63*10465441SEvalZero #define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ 64*10465441SEvalZero #define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ 65*10465441SEvalZero #define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ 66*10465441SEvalZero #define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ 67*10465441SEvalZero #define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ 68*10465441SEvalZero #define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ 69*10465441SEvalZero #define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ 70*10465441SEvalZero #define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ 71*10465441SEvalZero #define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ 72*10465441SEvalZero #define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ 73*10465441SEvalZero #define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) 74*10465441SEvalZero #define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ 75*10465441SEvalZero #define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) 76*10465441SEvalZero #define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ 77*10465441SEvalZero 78*10465441SEvalZero /* ========== Register definition for US0 peripheral ========== */ 79*10465441SEvalZero #define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ 80*10465441SEvalZero #define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ 81*10465441SEvalZero #define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ 82*10465441SEvalZero #define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ 83*10465441SEvalZero #define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ 84*10465441SEvalZero #define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ 85*10465441SEvalZero #define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ 86*10465441SEvalZero #define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ 87*10465441SEvalZero #define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ 88*10465441SEvalZero #define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ 89*10465441SEvalZero #define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ 90*10465441SEvalZero #define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ 91*10465441SEvalZero #define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ 92*10465441SEvalZero #define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ 93*10465441SEvalZero 94*10465441SEvalZero /* ========== Register definition for AIC peripheral ========== */ 95*10465441SEvalZero #define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ 96*10465441SEvalZero #define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) 97*10465441SEvalZero #define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ 98*10465441SEvalZero #define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) 99*10465441SEvalZero #define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ 100*10465441SEvalZero #define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ 101*10465441SEvalZero #define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ 102*10465441SEvalZero #define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ 103*10465441SEvalZero #define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ 104*10465441SEvalZero #define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ 105*10465441SEvalZero #define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ 106*10465441SEvalZero #define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ 107*10465441SEvalZero #define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ 108*10465441SEvalZero #define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ 109*10465441SEvalZero #define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ 110*10465441SEvalZero #define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ 111*10465441SEvalZero #define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ 112*10465441SEvalZero #define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ 113*10465441SEvalZero #define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ 114*10465441SEvalZero #define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ 115*10465441SEvalZero 116*10465441SEvalZero 117*10465441SEvalZero /* ========== Register definition for DBGU peripheral ========== */ 118*10465441SEvalZero #define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ 119*10465441SEvalZero #define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ 120*10465441SEvalZero #define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ 121*10465441SEvalZero #define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ 122*10465441SEvalZero #define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ 123*10465441SEvalZero #define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ 124*10465441SEvalZero #define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ 125*10465441SEvalZero #define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ 126*10465441SEvalZero #define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ 127*10465441SEvalZero #define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ 128*10465441SEvalZero #define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ 129*10465441SEvalZero #define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ 130*10465441SEvalZero 131*10465441SEvalZero /* ========== Register definition for PIO peripheral ========== */ 132*10465441SEvalZero #define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ 133*10465441SEvalZero #define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ 134*10465441SEvalZero #define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ 135*10465441SEvalZero #define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ 136*10465441SEvalZero #define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ 137*10465441SEvalZero #define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ 138*10465441SEvalZero #define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ 139*10465441SEvalZero #define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ 140*10465441SEvalZero #define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ 141*10465441SEvalZero #define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ 142*10465441SEvalZero #define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ 143*10465441SEvalZero #define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ 144*10465441SEvalZero #define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ 145*10465441SEvalZero #define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ 146*10465441SEvalZero #define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ 147*10465441SEvalZero #define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ 148*10465441SEvalZero #define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ 149*10465441SEvalZero #define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ 150*10465441SEvalZero #define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ 151*10465441SEvalZero #define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ 152*10465441SEvalZero #define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ 153*10465441SEvalZero #define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ 154*10465441SEvalZero #define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ 155*10465441SEvalZero #define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ 156*10465441SEvalZero #define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ 157*10465441SEvalZero #define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ 158*10465441SEvalZero #define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ 159*10465441SEvalZero #define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ 160*10465441SEvalZero #define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ 161*10465441SEvalZero 162*10465441SEvalZero // ========== Register definition for PIOA peripheral ========== 163*10465441SEvalZero #define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register 164*10465441SEvalZero #define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register 165*10465441SEvalZero #define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register 166*10465441SEvalZero #define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register 167*10465441SEvalZero #define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register 168*10465441SEvalZero #define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register 169*10465441SEvalZero #define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register 170*10465441SEvalZero #define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register 171*10465441SEvalZero #define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register 172*10465441SEvalZero #define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register 173*10465441SEvalZero #define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register 174*10465441SEvalZero #define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register 175*10465441SEvalZero #define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register 176*10465441SEvalZero #define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register 177*10465441SEvalZero #define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr 178*10465441SEvalZero #define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register 179*10465441SEvalZero #define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register 180*10465441SEvalZero #define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register 181*10465441SEvalZero #define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register 182*10465441SEvalZero #define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register 183*10465441SEvalZero #define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register 184*10465441SEvalZero #define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register 185*10465441SEvalZero #define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register 186*10465441SEvalZero #define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register 187*10465441SEvalZero #define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register 188*10465441SEvalZero #define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register 189*10465441SEvalZero #define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register 190*10465441SEvalZero #define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register 191*10465441SEvalZero #define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register 192*10465441SEvalZero // ========== Register definition for PIOB peripheral ========== 193*10465441SEvalZero #define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register 194*10465441SEvalZero #define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register 195*10465441SEvalZero #define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register 196*10465441SEvalZero #define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register 197*10465441SEvalZero #define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register 198*10465441SEvalZero #define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register 199*10465441SEvalZero #define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register 200*10465441SEvalZero #define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register 201*10465441SEvalZero #define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register 202*10465441SEvalZero #define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register 203*10465441SEvalZero #define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register 204*10465441SEvalZero #define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register 205*10465441SEvalZero #define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register 206*10465441SEvalZero #define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr 207*10465441SEvalZero #define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register 208*10465441SEvalZero #define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register 209*10465441SEvalZero #define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register 210*10465441SEvalZero #define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register 211*10465441SEvalZero #define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register 212*10465441SEvalZero #define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register 213*10465441SEvalZero #define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register 214*10465441SEvalZero #define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register 215*10465441SEvalZero #define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register 216*10465441SEvalZero #define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register 217*10465441SEvalZero #define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register 218*10465441SEvalZero #define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register 219*10465441SEvalZero #define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register 220*10465441SEvalZero #define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register 221*10465441SEvalZero #define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register 222*10465441SEvalZero 223*10465441SEvalZero /* ========== Register definition for PMC peripheral ========== */ 224*10465441SEvalZero #define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ 225*10465441SEvalZero #define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ 226*10465441SEvalZero #define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ 227*10465441SEvalZero #define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ 228*10465441SEvalZero #define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ 229*10465441SEvalZero #define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ 230*10465441SEvalZero #define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ 231*10465441SEvalZero #define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ 232*10465441SEvalZero #define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ 233*10465441SEvalZero #define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ 234*10465441SEvalZero #define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ 235*10465441SEvalZero #define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ 236*10465441SEvalZero #define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ 237*10465441SEvalZero #define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ 238*10465441SEvalZero #define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ 239*10465441SEvalZero 240*10465441SEvalZero /******************************************************************************/ 241*10465441SEvalZero /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ 242*10465441SEvalZero /******************************************************************************/ 243*10465441SEvalZero #define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 244*10465441SEvalZero #define AT91C_ID_SYS 1 /* System Peripheral */ 245*10465441SEvalZero #define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ 246*10465441SEvalZero #define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ 247*10465441SEvalZero #define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ 248*10465441SEvalZero #define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ 249*10465441SEvalZero #define AT91C_ID_US0 6 /* USART 0 */ 250*10465441SEvalZero #define AT91C_ID_US1 7 /* USART 1 */ 251*10465441SEvalZero #define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ 252*10465441SEvalZero #define AT91C_ID_TWI 9 /* Two-Wire Interface */ 253*10465441SEvalZero #define AT91C_ID_PWMC 10 /* PWM Controller */ 254*10465441SEvalZero #define AT91C_ID_UDP 11 /* USB Device Port */ 255*10465441SEvalZero #define AT91C_ID_TC0 12 /* Timer Counter 0 */ 256*10465441SEvalZero #define AT91C_ID_TC1 13 /* Timer Counter 1 */ 257*10465441SEvalZero #define AT91C_ID_TC2 14 /* Timer Counter 2 */ 258*10465441SEvalZero #define AT91C_ID_15 15 /* Reserved */ 259*10465441SEvalZero #define AT91C_ID_16 16 /* Reserved */ 260*10465441SEvalZero #define AT91C_ID_17 17 /* Reserved */ 261*10465441SEvalZero #define AT91C_ID_18 18 /* Reserved */ 262*10465441SEvalZero #define AT91C_ID_19 19 /* Reserved */ 263*10465441SEvalZero #define AT91C_ID_20 20 /* Reserved */ 264*10465441SEvalZero #define AT91C_ID_21 21 /* Reserved */ 265*10465441SEvalZero #define AT91C_ID_22 22 /* Reserved */ 266*10465441SEvalZero #define AT91C_ID_23 23 /* Reserved */ 267*10465441SEvalZero #define AT91C_ID_24 24 /* Reserved */ 268*10465441SEvalZero #define AT91C_ID_25 25 /* Reserved */ 269*10465441SEvalZero #define AT91C_ID_26 26 /* Reserved */ 270*10465441SEvalZero #define AT91C_ID_27 27 /* Reserved */ 271*10465441SEvalZero #define AT91C_ID_28 28 /* Reserved */ 272*10465441SEvalZero #define AT91C_ID_29 29 /* Reserved */ 273*10465441SEvalZero #define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ 274*10465441SEvalZero #define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ 275*10465441SEvalZero #define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ 276*10465441SEvalZero 277*10465441SEvalZero /*****************************/ 278*10465441SEvalZero /* CPU Mode */ 279*10465441SEvalZero /*****************************/ 280*10465441SEvalZero #define USERMODE 0x10 281*10465441SEvalZero #define FIQMODE 0x11 282*10465441SEvalZero #define IRQMODE 0x12 283*10465441SEvalZero #define SVCMODE 0x13 284*10465441SEvalZero #define ABORTMODE 0x17 285*10465441SEvalZero #define UNDEFMODE 0x1b 286*10465441SEvalZero #define MODEMASK 0x1f 287*10465441SEvalZero #define NOINT 0xc0 288*10465441SEvalZero 289*10465441SEvalZero #ifdef __cplusplus 290*10465441SEvalZero } 291*10465441SEvalZero #endif 292*10465441SEvalZero 293*10465441SEvalZero #endif 294