1*10465441SEvalZeroconfig ARCH_CPU_64BIT 2*10465441SEvalZero bool 3*10465441SEvalZero 4*10465441SEvalZeroconfig ARCH_ARM 5*10465441SEvalZero bool 6*10465441SEvalZero 7*10465441SEvalZeroconfig ARCH_ARM_CORTEX_M 8*10465441SEvalZero bool 9*10465441SEvalZero select ARCH_ARM 10*10465441SEvalZero 11*10465441SEvalZeroconfig ARCH_ARM_CORTEX_FPU 12*10465441SEvalZero bool 13*10465441SEvalZero 14*10465441SEvalZeroconfig ARCH_ARM_CORTEX_M0 15*10465441SEvalZero bool 16*10465441SEvalZero select ARCH_ARM_CORTEX_M 17*10465441SEvalZero 18*10465441SEvalZeroconfig ARCH_ARM_CORTEX_M3 19*10465441SEvalZero bool 20*10465441SEvalZero select ARCH_ARM_CORTEX_M 21*10465441SEvalZero 22*10465441SEvalZeroconfig ARCH_ARM_MPU 23*10465441SEvalZero bool 24*10465441SEvalZero depends on ARCH_ARM 25*10465441SEvalZero 26*10465441SEvalZeroconfig ARCH_ARM_CORTEX_M4 27*10465441SEvalZero bool 28*10465441SEvalZero select ARCH_ARM_CORTEX_M 29*10465441SEvalZero 30*10465441SEvalZeroconfig ARCH_ARM_CORTEX_M7 31*10465441SEvalZero bool 32*10465441SEvalZero select ARCH_ARM_CORTEX_M 33*10465441SEvalZero 34*10465441SEvalZeroconfig ARCH_ARM_CORTEX_R 35*10465441SEvalZero bool 36*10465441SEvalZero select ARCH_ARM 37*10465441SEvalZero 38*10465441SEvalZeroconfig ARCH_ARM_MMU 39*10465441SEvalZero bool 40*10465441SEvalZero depends on ARCH_ARM 41*10465441SEvalZero 42*10465441SEvalZeroconfig ARCH_ARM_ARM9 43*10465441SEvalZero bool 44*10465441SEvalZero select ARCH_ARM 45*10465441SEvalZero 46*10465441SEvalZeroconfig ARCH_ARM_ARM11 47*10465441SEvalZero bool 48*10465441SEvalZero select ARCH_ARM 49*10465441SEvalZero 50*10465441SEvalZeroconfig ARCH_ARM_CORTEX_A 51*10465441SEvalZero bool 52*10465441SEvalZero select ARCH_ARM 53*10465441SEvalZero 54*10465441SEvalZeroconfig ARCH_ARM_CORTEX_A5 55*10465441SEvalZero bool 56*10465441SEvalZero select ARCH_ARM_CORTEX_A 57*10465441SEvalZero 58*10465441SEvalZeroconfig ARCH_ARM_CORTEX_A7 59*10465441SEvalZero bool 60*10465441SEvalZero select ARCH_ARM_CORTEX_A 61*10465441SEvalZero 62*10465441SEvalZeroconfig ARCH_ARM_CORTEX_A8 63*10465441SEvalZero bool 64*10465441SEvalZero select ARCH_ARM_CORTEX_A 65*10465441SEvalZero 66*10465441SEvalZeroconfig ARCH_ARM_CORTEX_A9 67*10465441SEvalZero bool 68*10465441SEvalZero select ARCH_ARM_CORTEX_A 69*10465441SEvalZero 70*10465441SEvalZeroconfig ARCH_MIPS 71*10465441SEvalZero bool 72*10465441SEvalZero 73*10465441SEvalZeroconfig ARCH_MIPS_XBURST 74*10465441SEvalZero bool 75*10465441SEvalZero select ARCH_MIPS 76*10465441SEvalZero 77*10465441SEvalZeroconfig ARCH_ANDES 78*10465441SEvalZero bool 79*10465441SEvalZero 80*10465441SEvalZeroconfig ARCH_CSKY 81*10465441SEvalZero bool 82*10465441SEvalZero 83*10465441SEvalZeroconfig ARCH_POWERPC 84*10465441SEvalZero bool 85*10465441SEvalZero 86*10465441SEvalZeroconfig ARCH_RISCV 87*10465441SEvalZero bool 88*10465441SEvalZero 89*10465441SEvalZeroconfig ARCH_RISCV_FPU 90*10465441SEvalZero bool 91*10465441SEvalZero 92*10465441SEvalZeroconfig ARCH_RISCV32 93*10465441SEvalZero select ARCH_RISCV 94*10465441SEvalZero bool 95*10465441SEvalZero 96*10465441SEvalZeroconfig ARCH_RISCV64 97*10465441SEvalZero select ARCH_RISCV 98*10465441SEvalZero select ARCH_CPU_64BIT 99*10465441SEvalZero bool 100*10465441SEvalZero 101*10465441SEvalZeroconfig ARCH_IA32 102*10465441SEvalZero bool 103*10465441SEvalZero 104*10465441SEvalZeroconfig ARCH_TIDSP 105*10465441SEvalZero bool 106*10465441SEvalZero 107*10465441SEvalZeroconfig ARCH_TIDSP_C28X 108*10465441SEvalZero bool 109*10465441SEvalZero select ARCH_TIDSP 110*10465441SEvalZero select ARCH_CPU_STACK_GROWS_UPWARD 111*10465441SEvalZero 112*10465441SEvalZeroconfig ARCH_HOST_SIMULATOR 113*10465441SEvalZero bool 114*10465441SEvalZero 115*10465441SEvalZeroconfig ARCH_CPU_STACK_GROWS_UPWARD 116*10465441SEvalZero bool 117*10465441SEvalZero default n 118