1*10465441SEvalZero /*
2*10465441SEvalZero * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
3*10465441SEvalZero * Copyright (C) 2013 Armink <[email protected]>
4*10465441SEvalZero * All rights reserved.
5*10465441SEvalZero *
6*10465441SEvalZero * Redistribution and use in source and binary forms, with or without
7*10465441SEvalZero * modification, are permitted provided that the following conditions
8*10465441SEvalZero * are met:
9*10465441SEvalZero * 1. Redistributions of source code must retain the above copyright
10*10465441SEvalZero * notice, this list of conditions and the following disclaimer.
11*10465441SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*10465441SEvalZero * notice, this list of conditions and the following disclaimer in the
13*10465441SEvalZero * documentation and/or other materials provided with the distribution.
14*10465441SEvalZero * 3. The name of the author may not be used to endorse or promote products
15*10465441SEvalZero * derived from this software without specific prior written permission.
16*10465441SEvalZero *
17*10465441SEvalZero * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18*10465441SEvalZero * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19*10465441SEvalZero * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20*10465441SEvalZero * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21*10465441SEvalZero * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22*10465441SEvalZero * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23*10465441SEvalZero * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24*10465441SEvalZero * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25*10465441SEvalZero * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26*10465441SEvalZero * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27*10465441SEvalZero *
28*10465441SEvalZero * File: $Id: mbfunccoils_m.c,v 1.60 2013/10/12 15:10:12 Armink Add Master Functions
29*10465441SEvalZero */
30*10465441SEvalZero
31*10465441SEvalZero /* ----------------------- System includes ----------------------------------*/
32*10465441SEvalZero #include "stdlib.h"
33*10465441SEvalZero #include "string.h"
34*10465441SEvalZero
35*10465441SEvalZero /* ----------------------- Platform includes --------------------------------*/
36*10465441SEvalZero #include "port.h"
37*10465441SEvalZero
38*10465441SEvalZero /* ----------------------- Modbus includes ----------------------------------*/
39*10465441SEvalZero #include "mb.h"
40*10465441SEvalZero #include "mb_m.h"
41*10465441SEvalZero #include "mbframe.h"
42*10465441SEvalZero #include "mbproto.h"
43*10465441SEvalZero #include "mbconfig.h"
44*10465441SEvalZero
45*10465441SEvalZero /* ----------------------- Defines ------------------------------------------*/
46*10465441SEvalZero #define MB_PDU_REQ_READ_ADDR_OFF ( MB_PDU_DATA_OFF + 0 )
47*10465441SEvalZero #define MB_PDU_REQ_READ_COILCNT_OFF ( MB_PDU_DATA_OFF + 2 )
48*10465441SEvalZero #define MB_PDU_REQ_READ_SIZE ( 4 )
49*10465441SEvalZero #define MB_PDU_FUNC_READ_COILCNT_OFF ( MB_PDU_DATA_OFF + 0 )
50*10465441SEvalZero #define MB_PDU_FUNC_READ_VALUES_OFF ( MB_PDU_DATA_OFF + 1 )
51*10465441SEvalZero #define MB_PDU_FUNC_READ_SIZE_MIN ( 1 )
52*10465441SEvalZero
53*10465441SEvalZero #define MB_PDU_REQ_WRITE_ADDR_OFF ( MB_PDU_DATA_OFF )
54*10465441SEvalZero #define MB_PDU_REQ_WRITE_VALUE_OFF ( MB_PDU_DATA_OFF + 2 )
55*10465441SEvalZero #define MB_PDU_REQ_WRITE_SIZE ( 4 )
56*10465441SEvalZero #define MB_PDU_FUNC_WRITE_ADDR_OFF ( MB_PDU_DATA_OFF )
57*10465441SEvalZero #define MB_PDU_FUNC_WRITE_VALUE_OFF ( MB_PDU_DATA_OFF + 2 )
58*10465441SEvalZero #define MB_PDU_FUNC_WRITE_SIZE ( 4 )
59*10465441SEvalZero
60*10465441SEvalZero #define MB_PDU_REQ_WRITE_MUL_ADDR_OFF ( MB_PDU_DATA_OFF )
61*10465441SEvalZero #define MB_PDU_REQ_WRITE_MUL_COILCNT_OFF ( MB_PDU_DATA_OFF + 2 )
62*10465441SEvalZero #define MB_PDU_REQ_WRITE_MUL_BYTECNT_OFF ( MB_PDU_DATA_OFF + 4 )
63*10465441SEvalZero #define MB_PDU_REQ_WRITE_MUL_VALUES_OFF ( MB_PDU_DATA_OFF + 5 )
64*10465441SEvalZero #define MB_PDU_REQ_WRITE_MUL_SIZE_MIN ( 5 )
65*10465441SEvalZero #define MB_PDU_REQ_WRITE_MUL_COILCNT_MAX ( 0x07B0 )
66*10465441SEvalZero #define MB_PDU_FUNC_WRITE_MUL_ADDR_OFF ( MB_PDU_DATA_OFF )
67*10465441SEvalZero #define MB_PDU_FUNC_WRITE_MUL_COILCNT_OFF ( MB_PDU_DATA_OFF + 2 )
68*10465441SEvalZero #define MB_PDU_FUNC_WRITE_MUL_SIZE ( 5 )
69*10465441SEvalZero
70*10465441SEvalZero /* ----------------------- Static functions ---------------------------------*/
71*10465441SEvalZero eMBException prveMBError2Exception( eMBErrorCode eErrorCode );
72*10465441SEvalZero
73*10465441SEvalZero /* ----------------------- Start implementation -----------------------------*/
74*10465441SEvalZero #if MB_MASTER_RTU_ENABLED > 0 || MB_MASTER_ASCII_ENABLED > 0
75*10465441SEvalZero #if MB_FUNC_READ_COILS_ENABLED > 0
76*10465441SEvalZero
77*10465441SEvalZero /**
78*10465441SEvalZero * This function will request read coil.
79*10465441SEvalZero *
80*10465441SEvalZero * @param ucSndAddr salve address
81*10465441SEvalZero * @param usCoilAddr coil start address
82*10465441SEvalZero * @param usNCoils coil total number
83*10465441SEvalZero * @param lTimeOut timeout (-1 will waiting forever)
84*10465441SEvalZero *
85*10465441SEvalZero * @return error code
86*10465441SEvalZero */
87*10465441SEvalZero eMBMasterReqErrCode
eMBMasterReqReadCoils(UCHAR ucSndAddr,USHORT usCoilAddr,USHORT usNCoils,LONG lTimeOut)88*10465441SEvalZero eMBMasterReqReadCoils( UCHAR ucSndAddr, USHORT usCoilAddr, USHORT usNCoils ,LONG lTimeOut )
89*10465441SEvalZero {
90*10465441SEvalZero UCHAR *ucMBFrame;
91*10465441SEvalZero eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR;
92*10465441SEvalZero
93*10465441SEvalZero if ( ucSndAddr > MB_MASTER_TOTAL_SLAVE_NUM ) eErrStatus = MB_MRE_ILL_ARG;
94*10465441SEvalZero else if ( xMBMasterRunResTake( lTimeOut ) == FALSE ) eErrStatus = MB_MRE_MASTER_BUSY;
95*10465441SEvalZero else
96*10465441SEvalZero {
97*10465441SEvalZero vMBMasterGetPDUSndBuf(&ucMBFrame);
98*10465441SEvalZero vMBMasterSetDestAddress(ucSndAddr);
99*10465441SEvalZero ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_READ_COILS;
100*10465441SEvalZero ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF] = usCoilAddr >> 8;
101*10465441SEvalZero ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF + 1] = usCoilAddr;
102*10465441SEvalZero ucMBFrame[MB_PDU_REQ_READ_COILCNT_OFF ] = usNCoils >> 8;
103*10465441SEvalZero ucMBFrame[MB_PDU_REQ_READ_COILCNT_OFF + 1] = usNCoils;
104*10465441SEvalZero vMBMasterSetPDUSndLength( MB_PDU_SIZE_MIN + MB_PDU_REQ_READ_SIZE );
105*10465441SEvalZero ( void ) xMBMasterPortEventPost( EV_MASTER_FRAME_SENT );
106*10465441SEvalZero eErrStatus = eMBMasterWaitRequestFinish( );
107*10465441SEvalZero
108*10465441SEvalZero }
109*10465441SEvalZero return eErrStatus;
110*10465441SEvalZero }
111*10465441SEvalZero
112*10465441SEvalZero eMBException
eMBMasterFuncReadCoils(UCHAR * pucFrame,USHORT * usLen)113*10465441SEvalZero eMBMasterFuncReadCoils( UCHAR * pucFrame, USHORT * usLen )
114*10465441SEvalZero {
115*10465441SEvalZero UCHAR *ucMBFrame;
116*10465441SEvalZero USHORT usRegAddress;
117*10465441SEvalZero USHORT usCoilCount;
118*10465441SEvalZero UCHAR ucByteCount;
119*10465441SEvalZero
120*10465441SEvalZero eMBException eStatus = MB_EX_NONE;
121*10465441SEvalZero eMBErrorCode eRegStatus;
122*10465441SEvalZero
123*10465441SEvalZero /* If this request is broadcast, and it's read mode. This request don't need execute. */
124*10465441SEvalZero if ( xMBMasterRequestIsBroadcast() )
125*10465441SEvalZero {
126*10465441SEvalZero eStatus = MB_EX_NONE;
127*10465441SEvalZero }
128*10465441SEvalZero else if ( *usLen >= MB_PDU_SIZE_MIN + MB_PDU_FUNC_READ_SIZE_MIN )
129*10465441SEvalZero {
130*10465441SEvalZero vMBMasterGetPDUSndBuf(&ucMBFrame);
131*10465441SEvalZero usRegAddress = ( USHORT )( ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF] << 8 );
132*10465441SEvalZero usRegAddress |= ( USHORT )( ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF + 1] );
133*10465441SEvalZero usRegAddress++;
134*10465441SEvalZero
135*10465441SEvalZero usCoilCount = ( USHORT )( ucMBFrame[MB_PDU_REQ_READ_COILCNT_OFF] << 8 );
136*10465441SEvalZero usCoilCount |= ( USHORT )( ucMBFrame[MB_PDU_REQ_READ_COILCNT_OFF + 1] );
137*10465441SEvalZero
138*10465441SEvalZero /* Test if the quantity of coils is a multiple of 8. If not last
139*10465441SEvalZero * byte is only partially field with unused coils set to zero. */
140*10465441SEvalZero if( ( usCoilCount & 0x0007 ) != 0 )
141*10465441SEvalZero {
142*10465441SEvalZero ucByteCount = ( UCHAR )( usCoilCount / 8 + 1 );
143*10465441SEvalZero }
144*10465441SEvalZero else
145*10465441SEvalZero {
146*10465441SEvalZero ucByteCount = ( UCHAR )( usCoilCount / 8 );
147*10465441SEvalZero }
148*10465441SEvalZero
149*10465441SEvalZero /* Check if the number of registers to read is valid. If not
150*10465441SEvalZero * return Modbus illegal data value exception.
151*10465441SEvalZero */
152*10465441SEvalZero if( ( usCoilCount >= 1 ) &&
153*10465441SEvalZero ( ucByteCount == pucFrame[MB_PDU_FUNC_READ_COILCNT_OFF] ) )
154*10465441SEvalZero {
155*10465441SEvalZero /* Make callback to fill the buffer. */
156*10465441SEvalZero eRegStatus = eMBMasterRegCoilsCB( &pucFrame[MB_PDU_FUNC_READ_VALUES_OFF], usRegAddress, usCoilCount, MB_REG_READ );
157*10465441SEvalZero
158*10465441SEvalZero /* If an error occured convert it into a Modbus exception. */
159*10465441SEvalZero if( eRegStatus != MB_ENOERR )
160*10465441SEvalZero {
161*10465441SEvalZero eStatus = prveMBError2Exception( eRegStatus );
162*10465441SEvalZero }
163*10465441SEvalZero }
164*10465441SEvalZero else
165*10465441SEvalZero {
166*10465441SEvalZero eStatus = MB_EX_ILLEGAL_DATA_VALUE;
167*10465441SEvalZero }
168*10465441SEvalZero }
169*10465441SEvalZero else
170*10465441SEvalZero {
171*10465441SEvalZero /* Can't be a valid read coil register request because the length
172*10465441SEvalZero * is incorrect. */
173*10465441SEvalZero eStatus = MB_EX_ILLEGAL_DATA_VALUE;
174*10465441SEvalZero }
175*10465441SEvalZero return eStatus;
176*10465441SEvalZero }
177*10465441SEvalZero #endif
178*10465441SEvalZero
179*10465441SEvalZero #if MB_FUNC_WRITE_COIL_ENABLED > 0
180*10465441SEvalZero
181*10465441SEvalZero /**
182*10465441SEvalZero * This function will request write one coil.
183*10465441SEvalZero *
184*10465441SEvalZero * @param ucSndAddr salve address
185*10465441SEvalZero * @param usCoilAddr coil start address
186*10465441SEvalZero * @param usCoilData data to be written
187*10465441SEvalZero * @param lTimeOut timeout (-1 will waiting forever)
188*10465441SEvalZero *
189*10465441SEvalZero * @return error code
190*10465441SEvalZero *
191*10465441SEvalZero * @see eMBMasterReqWriteMultipleCoils
192*10465441SEvalZero */
193*10465441SEvalZero eMBMasterReqErrCode
eMBMasterReqWriteCoil(UCHAR ucSndAddr,USHORT usCoilAddr,USHORT usCoilData,LONG lTimeOut)194*10465441SEvalZero eMBMasterReqWriteCoil( UCHAR ucSndAddr, USHORT usCoilAddr, USHORT usCoilData, LONG lTimeOut )
195*10465441SEvalZero {
196*10465441SEvalZero UCHAR *ucMBFrame;
197*10465441SEvalZero eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR;
198*10465441SEvalZero
199*10465441SEvalZero if ( ucSndAddr > MB_MASTER_TOTAL_SLAVE_NUM ) eErrStatus = MB_MRE_ILL_ARG;
200*10465441SEvalZero else if ( ( usCoilData != 0xFF00 ) && ( usCoilData != 0x0000 ) ) eErrStatus = MB_MRE_ILL_ARG;
201*10465441SEvalZero else if ( xMBMasterRunResTake( lTimeOut ) == FALSE ) eErrStatus = MB_MRE_MASTER_BUSY;
202*10465441SEvalZero else
203*10465441SEvalZero {
204*10465441SEvalZero vMBMasterGetPDUSndBuf(&ucMBFrame);
205*10465441SEvalZero vMBMasterSetDestAddress(ucSndAddr);
206*10465441SEvalZero ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_WRITE_SINGLE_COIL;
207*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_ADDR_OFF] = usCoilAddr >> 8;
208*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_ADDR_OFF + 1] = usCoilAddr;
209*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_VALUE_OFF ] = usCoilData >> 8;
210*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_VALUE_OFF + 1] = usCoilData;
211*10465441SEvalZero vMBMasterSetPDUSndLength( MB_PDU_SIZE_MIN + MB_PDU_REQ_WRITE_SIZE );
212*10465441SEvalZero ( void ) xMBMasterPortEventPost( EV_MASTER_FRAME_SENT );
213*10465441SEvalZero eErrStatus = eMBMasterWaitRequestFinish( );
214*10465441SEvalZero }
215*10465441SEvalZero return eErrStatus;
216*10465441SEvalZero }
217*10465441SEvalZero
218*10465441SEvalZero eMBException
eMBMasterFuncWriteCoil(UCHAR * pucFrame,USHORT * usLen)219*10465441SEvalZero eMBMasterFuncWriteCoil( UCHAR * pucFrame, USHORT * usLen )
220*10465441SEvalZero {
221*10465441SEvalZero USHORT usRegAddress;
222*10465441SEvalZero UCHAR ucBuf[2];
223*10465441SEvalZero
224*10465441SEvalZero eMBException eStatus = MB_EX_NONE;
225*10465441SEvalZero eMBErrorCode eRegStatus;
226*10465441SEvalZero
227*10465441SEvalZero if( *usLen == ( MB_PDU_FUNC_WRITE_SIZE + MB_PDU_SIZE_MIN ) )
228*10465441SEvalZero {
229*10465441SEvalZero usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_ADDR_OFF] << 8 );
230*10465441SEvalZero usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_ADDR_OFF + 1] );
231*10465441SEvalZero usRegAddress++;
232*10465441SEvalZero
233*10465441SEvalZero if( ( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF + 1] == 0x00 ) &&
234*10465441SEvalZero ( ( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF] == 0xFF ) ||
235*10465441SEvalZero ( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF] == 0x00 ) ) )
236*10465441SEvalZero {
237*10465441SEvalZero ucBuf[1] = 0;
238*10465441SEvalZero if( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF] == 0xFF )
239*10465441SEvalZero {
240*10465441SEvalZero ucBuf[0] = 1;
241*10465441SEvalZero }
242*10465441SEvalZero else
243*10465441SEvalZero {
244*10465441SEvalZero ucBuf[0] = 0;
245*10465441SEvalZero }
246*10465441SEvalZero eRegStatus =
247*10465441SEvalZero eMBMasterRegCoilsCB( &ucBuf[0], usRegAddress, 1, MB_REG_WRITE );
248*10465441SEvalZero
249*10465441SEvalZero /* If an error occured convert it into a Modbus exception. */
250*10465441SEvalZero if( eRegStatus != MB_ENOERR )
251*10465441SEvalZero {
252*10465441SEvalZero eStatus = prveMBError2Exception( eRegStatus );
253*10465441SEvalZero }
254*10465441SEvalZero }
255*10465441SEvalZero else
256*10465441SEvalZero {
257*10465441SEvalZero eStatus = MB_EX_ILLEGAL_DATA_VALUE;
258*10465441SEvalZero }
259*10465441SEvalZero }
260*10465441SEvalZero else
261*10465441SEvalZero {
262*10465441SEvalZero /* Can't be a valid write coil register request because the length
263*10465441SEvalZero * is incorrect. */
264*10465441SEvalZero eStatus = MB_EX_ILLEGAL_DATA_VALUE;
265*10465441SEvalZero }
266*10465441SEvalZero return eStatus;
267*10465441SEvalZero }
268*10465441SEvalZero
269*10465441SEvalZero #endif
270*10465441SEvalZero
271*10465441SEvalZero #if MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED > 0
272*10465441SEvalZero
273*10465441SEvalZero /**
274*10465441SEvalZero * This function will request write multiple coils.
275*10465441SEvalZero *
276*10465441SEvalZero * @param ucSndAddr salve address
277*10465441SEvalZero * @param usCoilAddr coil start address
278*10465441SEvalZero * @param usNCoils coil total number
279*10465441SEvalZero * @param usCoilData data to be written
280*10465441SEvalZero * @param lTimeOut timeout (-1 will waiting forever)
281*10465441SEvalZero *
282*10465441SEvalZero * @return error code
283*10465441SEvalZero *
284*10465441SEvalZero * @see eMBMasterReqWriteCoil
285*10465441SEvalZero */
286*10465441SEvalZero eMBMasterReqErrCode
eMBMasterReqWriteMultipleCoils(UCHAR ucSndAddr,USHORT usCoilAddr,USHORT usNCoils,UCHAR * pucDataBuffer,LONG lTimeOut)287*10465441SEvalZero eMBMasterReqWriteMultipleCoils( UCHAR ucSndAddr,
288*10465441SEvalZero USHORT usCoilAddr, USHORT usNCoils, UCHAR * pucDataBuffer, LONG lTimeOut)
289*10465441SEvalZero {
290*10465441SEvalZero UCHAR *ucMBFrame;
291*10465441SEvalZero USHORT usRegIndex = 0;
292*10465441SEvalZero UCHAR ucByteCount;
293*10465441SEvalZero eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR;
294*10465441SEvalZero
295*10465441SEvalZero if ( ucSndAddr > MB_MASTER_TOTAL_SLAVE_NUM ) eErrStatus = MB_MRE_ILL_ARG;
296*10465441SEvalZero else if ( usNCoils > MB_PDU_REQ_WRITE_MUL_COILCNT_MAX ) eErrStatus = MB_MRE_ILL_ARG;
297*10465441SEvalZero else if ( xMBMasterRunResTake( lTimeOut ) == FALSE ) eErrStatus = MB_MRE_MASTER_BUSY;
298*10465441SEvalZero else
299*10465441SEvalZero {
300*10465441SEvalZero vMBMasterGetPDUSndBuf(&ucMBFrame);
301*10465441SEvalZero vMBMasterSetDestAddress(ucSndAddr);
302*10465441SEvalZero ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_WRITE_MULTIPLE_COILS;
303*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_MUL_ADDR_OFF] = usCoilAddr >> 8;
304*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_MUL_ADDR_OFF + 1] = usCoilAddr;
305*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_MUL_COILCNT_OFF] = usNCoils >> 8;
306*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_MUL_COILCNT_OFF + 1] = usNCoils ;
307*10465441SEvalZero if( ( usNCoils & 0x0007 ) != 0 )
308*10465441SEvalZero {
309*10465441SEvalZero ucByteCount = ( UCHAR )( usNCoils / 8 + 1 );
310*10465441SEvalZero }
311*10465441SEvalZero else
312*10465441SEvalZero {
313*10465441SEvalZero ucByteCount = ( UCHAR )( usNCoils / 8 );
314*10465441SEvalZero }
315*10465441SEvalZero ucMBFrame[MB_PDU_REQ_WRITE_MUL_BYTECNT_OFF] = ucByteCount;
316*10465441SEvalZero ucMBFrame += MB_PDU_REQ_WRITE_MUL_VALUES_OFF;
317*10465441SEvalZero while( ucByteCount > usRegIndex)
318*10465441SEvalZero {
319*10465441SEvalZero *ucMBFrame++ = pucDataBuffer[usRegIndex++];
320*10465441SEvalZero }
321*10465441SEvalZero vMBMasterSetPDUSndLength( MB_PDU_SIZE_MIN + MB_PDU_REQ_WRITE_MUL_SIZE_MIN + ucByteCount );
322*10465441SEvalZero ( void ) xMBMasterPortEventPost( EV_MASTER_FRAME_SENT );
323*10465441SEvalZero eErrStatus = eMBMasterWaitRequestFinish( );
324*10465441SEvalZero }
325*10465441SEvalZero return eErrStatus;
326*10465441SEvalZero }
327*10465441SEvalZero
328*10465441SEvalZero eMBException
eMBMasterFuncWriteMultipleCoils(UCHAR * pucFrame,USHORT * usLen)329*10465441SEvalZero eMBMasterFuncWriteMultipleCoils( UCHAR * pucFrame, USHORT * usLen )
330*10465441SEvalZero {
331*10465441SEvalZero USHORT usRegAddress;
332*10465441SEvalZero USHORT usCoilCnt;
333*10465441SEvalZero UCHAR ucByteCount;
334*10465441SEvalZero UCHAR ucByteCountVerify;
335*10465441SEvalZero UCHAR *ucMBFrame;
336*10465441SEvalZero
337*10465441SEvalZero eMBException eStatus = MB_EX_NONE;
338*10465441SEvalZero eMBErrorCode eRegStatus;
339*10465441SEvalZero
340*10465441SEvalZero /* If this request is broadcast, the *usLen is not need check. */
341*10465441SEvalZero if( ( *usLen == MB_PDU_FUNC_WRITE_MUL_SIZE ) || xMBMasterRequestIsBroadcast() )
342*10465441SEvalZero {
343*10465441SEvalZero vMBMasterGetPDUSndBuf(&ucMBFrame);
344*10465441SEvalZero usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_ADDR_OFF] << 8 );
345*10465441SEvalZero usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_ADDR_OFF + 1] );
346*10465441SEvalZero usRegAddress++;
347*10465441SEvalZero
348*10465441SEvalZero usCoilCnt = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_COILCNT_OFF] << 8 );
349*10465441SEvalZero usCoilCnt |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_COILCNT_OFF + 1] );
350*10465441SEvalZero
351*10465441SEvalZero ucByteCount = ucMBFrame[MB_PDU_REQ_WRITE_MUL_BYTECNT_OFF];
352*10465441SEvalZero
353*10465441SEvalZero /* Compute the number of expected bytes in the request. */
354*10465441SEvalZero if( ( usCoilCnt & 0x0007 ) != 0 )
355*10465441SEvalZero {
356*10465441SEvalZero ucByteCountVerify = ( UCHAR )( usCoilCnt / 8 + 1 );
357*10465441SEvalZero }
358*10465441SEvalZero else
359*10465441SEvalZero {
360*10465441SEvalZero ucByteCountVerify = ( UCHAR )( usCoilCnt / 8 );
361*10465441SEvalZero }
362*10465441SEvalZero
363*10465441SEvalZero if( ( usCoilCnt >= 1 ) && ( ucByteCountVerify == ucByteCount ) )
364*10465441SEvalZero {
365*10465441SEvalZero eRegStatus =
366*10465441SEvalZero eMBMasterRegCoilsCB( &ucMBFrame[MB_PDU_REQ_WRITE_MUL_VALUES_OFF],
367*10465441SEvalZero usRegAddress, usCoilCnt, MB_REG_WRITE );
368*10465441SEvalZero
369*10465441SEvalZero /* If an error occured convert it into a Modbus exception. */
370*10465441SEvalZero if( eRegStatus != MB_ENOERR )
371*10465441SEvalZero {
372*10465441SEvalZero eStatus = prveMBError2Exception( eRegStatus );
373*10465441SEvalZero }
374*10465441SEvalZero }
375*10465441SEvalZero else
376*10465441SEvalZero {
377*10465441SEvalZero eStatus = MB_EX_ILLEGAL_DATA_VALUE;
378*10465441SEvalZero }
379*10465441SEvalZero }
380*10465441SEvalZero else
381*10465441SEvalZero {
382*10465441SEvalZero /* Can't be a valid write coil register request because the length
383*10465441SEvalZero * is incorrect. */
384*10465441SEvalZero eStatus = MB_EX_ILLEGAL_DATA_VALUE;
385*10465441SEvalZero }
386*10465441SEvalZero return eStatus;
387*10465441SEvalZero }
388*10465441SEvalZero
389*10465441SEvalZero #endif
390*10465441SEvalZero #endif
391