1*10465441SEvalZero /*
2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero *
4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero *
6*10465441SEvalZero * Change Logs:
7*10465441SEvalZero * Date Author Notes
8*10465441SEvalZero * 2015-10-11 fullhan copy from winbond flash
9*10465441SEvalZero */
10*10465441SEvalZero
11*10465441SEvalZero #include <stdint.h>
12*10465441SEvalZero #include <rtthread.h>
13*10465441SEvalZero #include <rtdevice.h>
14*10465441SEvalZero
15*10465441SEvalZero #include "spi_flash.h"
16*10465441SEvalZero #include "spi_flash_gd.h"
17*10465441SEvalZero
18*10465441SEvalZero #define FLASH_DEBUG
19*10465441SEvalZero
20*10465441SEvalZero #ifdef FLASH_DEBUG
21*10465441SEvalZero #define FLASH_TRACE rt_kprintf
22*10465441SEvalZero #else
23*10465441SEvalZero #define FLASH_TRACE(...)
24*10465441SEvalZero #endif /* #ifdef FLASH_DEBUG */
25*10465441SEvalZero
26*10465441SEvalZero #define PAGE_SIZE 4096
27*10465441SEvalZero
28*10465441SEvalZero /* JEDEC Manufacturer's ID */
29*10465441SEvalZero #define MF_ID (0xC8)
30*10465441SEvalZero /* JEDEC Device ID: Memory type and Capacity */
31*10465441SEvalZero #define MTC_GD25Q128 (0x4018)
32*10465441SEvalZero
33*10465441SEvalZero /* command list */
34*10465441SEvalZero #define CMD_WRSR (0x01) /* Write Status Register */
35*10465441SEvalZero #define CMD_PP (0x02) /* Page Program */
36*10465441SEvalZero #define CMD_READ (0x03) /* Read Data */
37*10465441SEvalZero #define CMD_WRDI (0x04) /* Write Disable */
38*10465441SEvalZero #define CMD_RDSR1 (0x05) /* Read Status Register-1 */
39*10465441SEvalZero #define CMD_WREN (0x06) /* Write Enable */
40*10465441SEvalZero #define CMD_FAST_READ (0x0B) /* Fast Read */
41*10465441SEvalZero #define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
42*10465441SEvalZero #define CMD_RDSR2 (0x35) /* Read Status Register-2 */
43*10465441SEvalZero #define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
44*10465441SEvalZero #define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
45*10465441SEvalZero #define CMD_ERASE_full (0xC7) /* Chip Erase */
46*10465441SEvalZero #define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
47*10465441SEvalZero
48*10465441SEvalZero #define DUMMY (0xFF)
49*10465441SEvalZero
50*10465441SEvalZero static struct spi_flash_device spi_flash_device;
51*10465441SEvalZero
flash_lock(struct spi_flash_device * flash_device)52*10465441SEvalZero static void flash_lock(struct spi_flash_device * flash_device)
53*10465441SEvalZero {
54*10465441SEvalZero rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
55*10465441SEvalZero }
56*10465441SEvalZero
flash_unlock(struct spi_flash_device * flash_device)57*10465441SEvalZero static void flash_unlock(struct spi_flash_device * flash_device)
58*10465441SEvalZero {
59*10465441SEvalZero rt_mutex_release(&flash_device->lock);
60*10465441SEvalZero }
61*10465441SEvalZero
w25qxx_read_status(void)62*10465441SEvalZero static uint8_t w25qxx_read_status(void)
63*10465441SEvalZero {
64*10465441SEvalZero return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
65*10465441SEvalZero }
66*10465441SEvalZero
w25qxx_wait_busy(void)67*10465441SEvalZero static void w25qxx_wait_busy(void)
68*10465441SEvalZero {
69*10465441SEvalZero while( w25qxx_read_status() & (0x01));
70*10465441SEvalZero }
71*10465441SEvalZero
72*10465441SEvalZero /** \brief read [size] byte from [offset] to [buffer]
73*10465441SEvalZero *
74*10465441SEvalZero * \param offset uint32_t unit : byte
75*10465441SEvalZero * \param buffer uint8_t*
76*10465441SEvalZero * \param size uint32_t unit : byte
77*10465441SEvalZero * \return uint32_t byte for read
78*10465441SEvalZero *
79*10465441SEvalZero */
w25qxx_read(uint32_t offset,uint8_t * buffer,uint32_t size)80*10465441SEvalZero static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
81*10465441SEvalZero {
82*10465441SEvalZero uint8_t send_buffer[4];
83*10465441SEvalZero
84*10465441SEvalZero send_buffer[0] = CMD_WRDI;
85*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
86*10465441SEvalZero
87*10465441SEvalZero send_buffer[0] = CMD_READ;
88*10465441SEvalZero send_buffer[1] = (uint8_t)(offset>>16);
89*10465441SEvalZero send_buffer[2] = (uint8_t)(offset>>8);
90*10465441SEvalZero send_buffer[3] = (uint8_t)(offset);
91*10465441SEvalZero
92*10465441SEvalZero rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
93*10465441SEvalZero send_buffer, 4,
94*10465441SEvalZero buffer, size);
95*10465441SEvalZero
96*10465441SEvalZero return size;
97*10465441SEvalZero }
98*10465441SEvalZero
99*10465441SEvalZero /** \brief write N page on [page]
100*10465441SEvalZero *
101*10465441SEvalZero * \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
102*10465441SEvalZero * \param buffer const uint8_t*
103*10465441SEvalZero * \return uint32_t
104*10465441SEvalZero *
105*10465441SEvalZero */
w25qxx_page_write(uint32_t page_addr,const uint8_t * buffer)106*10465441SEvalZero static uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
107*10465441SEvalZero {
108*10465441SEvalZero uint32_t index;
109*10465441SEvalZero uint8_t send_buffer[4];
110*10465441SEvalZero
111*10465441SEvalZero RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
112*10465441SEvalZero
113*10465441SEvalZero send_buffer[0] = CMD_WREN;
114*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
115*10465441SEvalZero
116*10465441SEvalZero send_buffer[0] = CMD_ERASE_4K;
117*10465441SEvalZero send_buffer[1] = (page_addr >> 16);
118*10465441SEvalZero send_buffer[2] = (page_addr >> 8);
119*10465441SEvalZero send_buffer[3] = (page_addr);
120*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
121*10465441SEvalZero
122*10465441SEvalZero w25qxx_wait_busy(); // wait erase done.
123*10465441SEvalZero
124*10465441SEvalZero for(index=0; index < (PAGE_SIZE / 256); index++)
125*10465441SEvalZero {
126*10465441SEvalZero send_buffer[0] = CMD_WREN;
127*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
128*10465441SEvalZero
129*10465441SEvalZero send_buffer[0] = CMD_PP;
130*10465441SEvalZero send_buffer[1] = (uint8_t)(page_addr >> 16);
131*10465441SEvalZero send_buffer[2] = (uint8_t)(page_addr >> 8);
132*10465441SEvalZero send_buffer[3] = (uint8_t)(page_addr);
133*10465441SEvalZero
134*10465441SEvalZero rt_spi_send_then_send(spi_flash_device.rt_spi_device,
135*10465441SEvalZero send_buffer,
136*10465441SEvalZero 4,
137*10465441SEvalZero buffer,
138*10465441SEvalZero 256);
139*10465441SEvalZero
140*10465441SEvalZero buffer += 256;
141*10465441SEvalZero page_addr += 256;
142*10465441SEvalZero w25qxx_wait_busy();
143*10465441SEvalZero }
144*10465441SEvalZero
145*10465441SEvalZero send_buffer[0] = CMD_WRDI;
146*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
147*10465441SEvalZero
148*10465441SEvalZero return PAGE_SIZE;
149*10465441SEvalZero }
150*10465441SEvalZero
151*10465441SEvalZero /* RT-Thread device interface */
w25qxx_flash_init(rt_device_t dev)152*10465441SEvalZero static rt_err_t w25qxx_flash_init(rt_device_t dev)
153*10465441SEvalZero {
154*10465441SEvalZero return RT_EOK;
155*10465441SEvalZero }
156*10465441SEvalZero
w25qxx_flash_open(rt_device_t dev,rt_uint16_t oflag)157*10465441SEvalZero static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
158*10465441SEvalZero {
159*10465441SEvalZero uint8_t send_buffer[3];
160*10465441SEvalZero
161*10465441SEvalZero flash_lock((struct spi_flash_device *)dev);
162*10465441SEvalZero
163*10465441SEvalZero send_buffer[0] = CMD_WREN;
164*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
165*10465441SEvalZero
166*10465441SEvalZero send_buffer[0] = CMD_WRSR;
167*10465441SEvalZero send_buffer[1] = 0;
168*10465441SEvalZero send_buffer[2] = 0;
169*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
170*10465441SEvalZero
171*10465441SEvalZero w25qxx_wait_busy();
172*10465441SEvalZero
173*10465441SEvalZero flash_unlock((struct spi_flash_device *)dev);
174*10465441SEvalZero
175*10465441SEvalZero return RT_EOK;
176*10465441SEvalZero }
177*10465441SEvalZero
w25qxx_flash_close(rt_device_t dev)178*10465441SEvalZero static rt_err_t w25qxx_flash_close(rt_device_t dev)
179*10465441SEvalZero {
180*10465441SEvalZero return RT_EOK;
181*10465441SEvalZero }
182*10465441SEvalZero
w25qxx_flash_control(rt_device_t dev,int cmd,void * args)183*10465441SEvalZero static rt_err_t w25qxx_flash_control(rt_device_t dev, int cmd, void *args)
184*10465441SEvalZero {
185*10465441SEvalZero RT_ASSERT(dev != RT_NULL);
186*10465441SEvalZero
187*10465441SEvalZero if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
188*10465441SEvalZero {
189*10465441SEvalZero struct rt_device_blk_geometry *geometry;
190*10465441SEvalZero
191*10465441SEvalZero geometry = (struct rt_device_blk_geometry *)args;
192*10465441SEvalZero if (geometry == RT_NULL) return -RT_ERROR;
193*10465441SEvalZero
194*10465441SEvalZero geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
195*10465441SEvalZero geometry->sector_count = spi_flash_device.geometry.sector_count;
196*10465441SEvalZero geometry->block_size = spi_flash_device.geometry.block_size;
197*10465441SEvalZero }
198*10465441SEvalZero
199*10465441SEvalZero return RT_EOK;
200*10465441SEvalZero }
201*10465441SEvalZero
w25qxx_flash_read(rt_device_t dev,rt_off_t pos,void * buffer,rt_size_t size)202*10465441SEvalZero static rt_size_t w25qxx_flash_read(rt_device_t dev,
203*10465441SEvalZero rt_off_t pos,
204*10465441SEvalZero void* buffer,
205*10465441SEvalZero rt_size_t size)
206*10465441SEvalZero {
207*10465441SEvalZero flash_lock((struct spi_flash_device *)dev);
208*10465441SEvalZero
209*10465441SEvalZero w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
210*10465441SEvalZero buffer,
211*10465441SEvalZero size*spi_flash_device.geometry.bytes_per_sector);
212*10465441SEvalZero
213*10465441SEvalZero flash_unlock((struct spi_flash_device *)dev);
214*10465441SEvalZero
215*10465441SEvalZero return size;
216*10465441SEvalZero }
217*10465441SEvalZero
w25qxx_flash_write(rt_device_t dev,rt_off_t pos,const void * buffer,rt_size_t size)218*10465441SEvalZero static rt_size_t w25qxx_flash_write(rt_device_t dev,
219*10465441SEvalZero rt_off_t pos,
220*10465441SEvalZero const void* buffer,
221*10465441SEvalZero rt_size_t size)
222*10465441SEvalZero {
223*10465441SEvalZero rt_size_t i = 0;
224*10465441SEvalZero rt_size_t block = size;
225*10465441SEvalZero const uint8_t * ptr = buffer;
226*10465441SEvalZero
227*10465441SEvalZero flash_lock((struct spi_flash_device *)dev);
228*10465441SEvalZero
229*10465441SEvalZero while(block--)
230*10465441SEvalZero {
231*10465441SEvalZero w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
232*10465441SEvalZero ptr);
233*10465441SEvalZero ptr += PAGE_SIZE;
234*10465441SEvalZero i++;
235*10465441SEvalZero }
236*10465441SEvalZero
237*10465441SEvalZero flash_unlock((struct spi_flash_device *)dev);
238*10465441SEvalZero
239*10465441SEvalZero return size;
240*10465441SEvalZero }
241*10465441SEvalZero
242*10465441SEvalZero #ifdef RT_USING_DEVICE_OPS
243*10465441SEvalZero const static struct rt_device_ops gd_device_ops =
244*10465441SEvalZero {
245*10465441SEvalZero w25qxx_flash_init,
246*10465441SEvalZero w25qxx_flash_open,
247*10465441SEvalZero w25qxx_flash_close,
248*10465441SEvalZero w25qxx_flash_read,
249*10465441SEvalZero w25qxx_flash_write,
250*10465441SEvalZero w25qxx_flash_control
251*10465441SEvalZero };
252*10465441SEvalZero #endif
253*10465441SEvalZero
gd_init(const char * flash_device_name,const char * spi_device_name)254*10465441SEvalZero rt_err_t gd_init(const char * flash_device_name, const char * spi_device_name)
255*10465441SEvalZero {
256*10465441SEvalZero struct rt_spi_device * rt_spi_device;
257*10465441SEvalZero
258*10465441SEvalZero /* initialize mutex */
259*10465441SEvalZero if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
260*10465441SEvalZero {
261*10465441SEvalZero rt_kprintf("init sd lock mutex failed\n");
262*10465441SEvalZero return -RT_ENOSYS;
263*10465441SEvalZero }
264*10465441SEvalZero
265*10465441SEvalZero rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
266*10465441SEvalZero if(rt_spi_device == RT_NULL)
267*10465441SEvalZero {
268*10465441SEvalZero FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
269*10465441SEvalZero return -RT_ENOSYS;
270*10465441SEvalZero }
271*10465441SEvalZero spi_flash_device.rt_spi_device = rt_spi_device;
272*10465441SEvalZero
273*10465441SEvalZero /* config spi */
274*10465441SEvalZero {
275*10465441SEvalZero struct rt_spi_configuration cfg;
276*10465441SEvalZero cfg.data_width = 8;
277*10465441SEvalZero cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
278*10465441SEvalZero cfg.max_hz = 50 * 1000 * 1000; /* 50M */
279*10465441SEvalZero rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
280*10465441SEvalZero }
281*10465441SEvalZero
282*10465441SEvalZero /* init flash */
283*10465441SEvalZero {
284*10465441SEvalZero rt_uint8_t cmd;
285*10465441SEvalZero rt_uint8_t id_recv[3];
286*10465441SEvalZero uint16_t memory_type_capacity;
287*10465441SEvalZero
288*10465441SEvalZero flash_lock(&spi_flash_device);
289*10465441SEvalZero
290*10465441SEvalZero cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
291*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
292*10465441SEvalZero
293*10465441SEvalZero cmd = CMD_WRDI;
294*10465441SEvalZero rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
295*10465441SEvalZero
296*10465441SEvalZero /* read flash id */
297*10465441SEvalZero cmd = CMD_JEDEC_ID;
298*10465441SEvalZero rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
299*10465441SEvalZero
300*10465441SEvalZero flash_unlock(&spi_flash_device);
301*10465441SEvalZero
302*10465441SEvalZero if(id_recv[0] != MF_ID)
303*10465441SEvalZero {
304*10465441SEvalZero FLASH_TRACE("Manufacturers ID error!\r\n");
305*10465441SEvalZero FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
306*10465441SEvalZero return -RT_ENOSYS;
307*10465441SEvalZero }
308*10465441SEvalZero
309*10465441SEvalZero spi_flash_device.geometry.bytes_per_sector = 4096;
310*10465441SEvalZero spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
311*10465441SEvalZero
312*10465441SEvalZero /* get memory type and capacity */
313*10465441SEvalZero memory_type_capacity = id_recv[1];
314*10465441SEvalZero memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
315*10465441SEvalZero
316*10465441SEvalZero if(memory_type_capacity == MTC_GD25Q128)
317*10465441SEvalZero {
318*10465441SEvalZero FLASH_TRACE("GD128 detection\r\n");
319*10465441SEvalZero spi_flash_device.geometry.sector_count = 4096;
320*10465441SEvalZero }
321*10465441SEvalZero else
322*10465441SEvalZero {
323*10465441SEvalZero FLASH_TRACE("Memory Capacity error!\r\n");
324*10465441SEvalZero return -RT_ENOSYS;
325*10465441SEvalZero }
326*10465441SEvalZero }
327*10465441SEvalZero
328*10465441SEvalZero /* register device */
329*10465441SEvalZero spi_flash_device.flash_device.type = RT_Device_Class_Block;
330*10465441SEvalZero #ifdef RT_USING_DEVICE_OPS
331*10465441SEvalZero spi_flash_device.flash_device.ops = &gd_device_ops;
332*10465441SEvalZero #else
333*10465441SEvalZero spi_flash_device.flash_device.init = w25qxx_flash_init;
334*10465441SEvalZero spi_flash_device.flash_device.open = w25qxx_flash_open;
335*10465441SEvalZero spi_flash_device.flash_device.close = w25qxx_flash_close;
336*10465441SEvalZero spi_flash_device.flash_device.read = w25qxx_flash_read;
337*10465441SEvalZero spi_flash_device.flash_device.write = w25qxx_flash_write;
338*10465441SEvalZero spi_flash_device.flash_device.control = w25qxx_flash_control;
339*10465441SEvalZero #endif
340*10465441SEvalZero /* no private */
341*10465441SEvalZero spi_flash_device.flash_device.user_data = RT_NULL;
342*10465441SEvalZero
343*10465441SEvalZero rt_device_register(&spi_flash_device.flash_device, flash_device_name,
344*10465441SEvalZero RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
345*10465441SEvalZero
346*10465441SEvalZero return RT_EOK;
347*10465441SEvalZero }
348