1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2015-1-11 RT_learning the first version 9 */ 10 #ifndef __BMI055_H__ 11 #define __BMI055_H__ 12 13 #include <sensor.h> 14 15 /**************************************************************************************************/ 16 /************************************Register map accelerometer************************************/ 17 18 #define BMI055_ACC_I2C_ADDR1 0x18 //SDO is low(GND) 19 #define BMI055_ACC_I2C_ADDR2 0x19 //SDO is high(VCC) 20 21 #define BMI055_ACC_DEFAULT_ADDRESS BMI055_ACC_I2C_ADDR2 //in the LPC54102 SPM-S 22 23 #define BMI055_ACC_BGW_CHIPID_VALUE 0xFA 24 25 #define BMI055_ACC_BGW_CHIPID 0x00 26 /**<Address of ACC Chip ID Register */ 27 #define BMI055_ACCD_X_LSB 0x02 28 /**< Address of X axis ACC LSB Register */ 29 #define BMI055_ACCD_X_MSB 0x03 30 /**< Address of X axis ACC MSB Register */ 31 #define BMI055_ACCD_Y_LSB 0x04 32 /**< Address of Y axis ACC LSB Register */ 33 #define BMI055_ACCD_Y_MSB 0x05 34 /**< Address of Y axis ACC MSB Register */ 35 #define BMI055_ACCD_Z_LSB 0x06 36 /**< Address of Z axis ACC LSB Register */ 37 #define BMI055_ACCD_Z_MSB 0x07 38 /**< Address of Z axis ACC MSB Register */ 39 #define BMI055_ACCD_TEMP 0x08 40 /**< Address of Temperature Data Register */ 41 42 /* Status Register */ 43 #define BMI055_INT_STATUS_0 0x09 44 /**< Address of Interrupt status Register 0 */ 45 #define BMI055_INT_STATUS_1 0x0A 46 /**< Address of Interrupt status Register 1 */ 47 #define BMI055_INT_STATUS_2 0x0B 48 /**< Address of Interrupt status Register 2 */ 49 #define BMI055_INT_STATUS_3 0x0C 50 /**< Address of Interrupt status Register 3 */ 51 #define BMI055_FIFO_STATUS 0x0E 52 /**< Address of FIFO status Register */ 53 54 /* Control Register */ 55 #define BMI055_PMU_RANGE 0x0F 56 /**< Address of Range address Register */ 57 #define BMI055_PMU_BW 0x10 58 /**< Address of Bandwidth Register */ 59 #define BMI055_PMU_LPW 0x11 60 /**< Address of PMU LPW */ 61 #define BMI055_PMU_LOW_POWER 0x12 62 /**< Address of PMU LOW POWER */ 63 #define BMI055_ACCD_HBW 0x13 64 /**< Address of ACCD HBW */ 65 #define BMI055_BGW_SOFTRESET 0x14 66 /**< Address of BGW SOFTRESET */ 67 #define BMI055_INT_EN_0 0x16 68 /**< Address of interrupt engines in group 0 */ 69 #define BMI055_INT_EN_1 0x17 70 /**< Address of interrupt engines in group 1 */ 71 #define BMI055_INT_EN_2 0x18 72 /**< Address of interrupt engines in group 2 */ 73 #define BMI055_INT_MAP_0 0x19 74 /**< Address of Interrupt MAP 0 */ 75 #define BMI055_INT_MAP_1 0x1A 76 /**< Address of Interrupt MAP 1 */ 77 #define BMI055_INT_MAP_2 0x1B 78 /**< Address of Interrupt MAP 2 */ 79 #define BMI055_INT_SRC 0x1E 80 /**< Address of Interrupt source */ 81 #define BMI055_INT_OUT_CTRL 0x20 82 /**< Address of Interrupt Register */ 83 #define BMI055_INT_RST_LATCH 0x21 84 /**< Address of Interrupt reset and mode Register */ 85 #define BMI055_INT_0 0x22 86 /**< Address of low-g Interrupt delay time Register */ 87 #define BMI055_INT_1 0x23 88 /**< Address of low-g Interrupt threshold Register */ 89 #define BMI055_INT_2 0x24 90 /**< Address of Interrupt 2 Register */ 91 #define BMI055_INT_3 0x25 92 /**< Address of high-g Interrupt delay time Register */ 93 #define BMI055_INT_4 0x26 94 /**< Address of high-g Interrupt threshold Register */ 95 #define BMI055_INT_5 0x27 96 /**< Address of high-g Interrupt 5 Register */ 97 #define BMI055_INT_6 0x28 98 /**< Address of any-motion Interrupt threshold Register */ 99 #define BMI055_INT_7 0x29 100 /**< Address of slow/no-motion interrupt threshold Register */ 101 #define BMI055_INT_8 0x2A 102 /**< Address of high-g Interrupt 8 Register */ 103 #define BMI055_INT_9 0x2B 104 /**< Address of high-g Interrupt 9 Register */ 105 #define BMI055_INT_A 0x2C 106 /**< Address of Interrupt A Register */ 107 #define BMI055_INT_B 0x2D 108 /**< Address of Interrupt B Register */ 109 #define BMI055_INT_C 0x2E 110 /**< Address of Interrupt C Register */ 111 #define BMI055_INT_D 0x2F 112 /**< Address of Interrupt D Register */ 113 #define BMI055_FIFO_CONFIG_0 0x30 114 /**< Address of FIFO CONFIG 0 Register */ 115 #define BMI055_PMU_SELF_TEST 0x32 116 /**< Address of PMU SELF TEST Register */ 117 #define BMI055_TRIM_NVM_CTRL 0x33 118 /**< Address of TRIM NVM CTRL Register */ 119 #define BMI055_BGW_SPI3_WDT 0x34 120 /**< Address of BGW SPI3 WDT Register */ 121 #define BMI055_OFC_CTRL 0x36 122 /**< Address of OFC CTRL Register */ 123 #define BMI055_OFC_SETTING 0x37 124 /**< Address of OFC SETTING Register */ 125 #define BMI055_OFC_OFFSET_X 0x38 126 /**< Address of OFC OFFSET X Register */ 127 #define BMI055_OFC_OFFSET_Y 0x39 128 /**< Address of OFC OFFSET Y Register */ 129 #define BMI055_OFC_OFFSET_Z 0x3A 130 /**< Address of OFC OFFSET Z Register */ 131 132 /* Trim Register */ 133 #define BMI055_TRIM_GP0 0x3B 134 /**< Address of TRIM GP0 Register */ 135 #define BMI055_TRIM_GP1 0x3C 136 /**< Address of TRIM GP1 Register */ 137 138 /* Control Register */ 139 #define BMI055_FIFO_CONFIG_1 0x3E 140 /**< Address of FIFO CONFIG 1 Register */ 141 142 /* Data Register */ 143 #define BMI055_FIFO_DATA 0x3F 144 /**< Address of FIFO DATA Register */ 145 146 147 /**************************************************************************************************/ 148 149 150 151 152 /**************************************************************************************************/ 153 /************************************Register map gyroscope****************************************/ 154 155 156 /**< This refers BMI055 return type as signed */ 157 158 // #define BMI055_I2C_ADDR1 0x68 //SDO is low(GND) 159 // #define BMI055_I2C_ADDR2 0x69 //SDO is high(VCC) 160 #define BMI055_GYRO_I2C_ADDR1 0x68 //SDO is low(GND) 161 #define BMI055_GYRO_I2C_ADDR2 0x69 //SDO is high(VCC) 162 163 #define BMI055_GYRO_DEFAULT_ADDRESS BMI055_GYRO_I2C_ADDR2 164 165 #define BMI055_GRRO_CHIP_ID 0x0F 166 167 /*Define of registers*/ 168 169 /* Hard Wired */ 170 #define BMI055_CHIP_ID_ADDR 0x00 171 /**<Address of Chip ID Register*/ 172 173 /* Data Register */ 174 #define BMI055_RATE_X_LSB_ADDR 0x02 175 /**< Address of X axis Rate LSB Register */ 176 #define BMI055_RATE_X_MSB_ADDR 0x03 177 /**< Address of X axis Rate MSB Register */ 178 #define BMI055_RATE_Y_LSB_ADDR 0x04 179 /**< Address of Y axis Rate LSB Register */ 180 #define BMI055_RATE_Y_MSB_ADDR 0x05 181 /**< Address of Y axis Rate MSB Register */ 182 #define BMI055_RATE_Z_LSB_ADDR 0x06 183 /**< Address of Z axis Rate LSB Register */ 184 #define BMI055_RATE_Z_MSB_ADDR 0x07 185 /**< Address of Z axis Rate MSB Register */ 186 #define BMI055_TEMP_ADDR 0x08 187 /**< Address of Temperature Data LSB Register */ 188 189 /* Status Register */ 190 #define BMI055_INTR_STAT0_ADDR 0x09 191 /**< Address of Interrupt status Register 0 */ 192 #define BMI055_INTR_STAT1_ADDR 0x0A 193 /**< Address of Interrupt status Register 1 */ 194 #define BMI055_INTR_STAT2_ADDR 0x0B 195 /**< Address of Interrupt status Register 2 */ 196 #define BMI055_INTR_STAT3_ADDR 0x0C 197 /**< Address of Interrupt status Register 3 */ 198 #define BMI055_FIFO_STAT_ADDR 0x0E 199 /**< Address of FIFO status Register */ 200 201 /* Control Register */ 202 #define BMI055_RANGE_ADDR 0x0F 203 /**< Address of Range address Register */ 204 #define BMI055_BW_ADDR 0x10 205 /**< Address of Bandwidth Register */ 206 #define BMI055_MODE_LPM1_ADDR 0x11 207 /**< Address of Mode LPM1 Register */ 208 #define BMI055_MODE_LPM2_ADDR 0x12 209 /**< Address of Mode LPM2 Register */ 210 #define BMI055_HIGH_BW_ADDR 0x13 211 /**< Address of Rate HIGH_BW Register */ 212 #define BMI055_BGW_SOFT_RST_ADDR 0x14 213 /**< Address of BGW Softreset Register */ 214 #define BMI055_INTR_ENABLE0_ADDR 0x15 215 /**< Address of Interrupt Enable 0 */ 216 #define BMI055_INTR_ENABLE1_ADDR 0x16 217 /**< Address of Interrupt Enable 1 */ 218 #define BMI055_INTR_MAP_ZERO_ADDR 0x17 219 /**< Address of Interrupt MAP 0 */ 220 #define BMI055_INTR_MAP_ONE_ADDR 0x18 221 /**< Address of Interrupt MAP 1 */ 222 #define BMI055_INTR_MAP_TWO_ADDR 0x19 223 /**< Address of Interrupt MAP 2 */ 224 #define BMI055_INTR_ZERO_ADDR 0x1A 225 /**< Address of Interrupt 0 register */ 226 #define BMI055_INTR_ONE_ADDR 0x1B 227 /**< Address of Interrupt 1 register */ 228 #define BMI055_INTR_TWO_ADDR 0x1C 229 /**< Address of Interrupt 2 register */ 230 #define BMI055_INTR_4_ADDR 0x1E 231 /**< Address of Interrupt 4 register */ 232 #define BMI055_RST_LATCH_ADDR 0x21 233 /**< Address of Reset Latch Register */ 234 #define BMI055_HIGHRATE_THRES_X_ADDR 0x22 235 /**< Address of High Th x Address register */ 236 #define BMI055_HIGHRATE_DURN_X_ADDR 0x23 237 /**< Address of High Dur x Address register */ 238 #define BMI055_HIGHRATE_THRES_Y_ADDR 0x24 239 /**< Address of High Th y Address register */ 240 #define BMI055_HIGHRATE_DURN_Y_ADDR 0x25 241 /**< Address of High Dur y Address register */ 242 #define BMI055_HIGHRATE_THRES_Z_ADDR 0x26 243 /**< Address of High Th z Address register */ 244 #define BMI055_HIGHRATE_DURN_Z_ADDR 0x27 245 /**< Address of High Dur z Address register */ 246 #define BMI055_SOC_ADDR 0x31 247 /**< Address of SOC register */ 248 #define BMI055_A_FOC_ADDR 0x32 249 /**< Address of A_FOC Register */ 250 #define BMI055_TRIM_NVM_CTRL_ADDR 0x33 251 /**< Address of Trim NVM control register */ 252 #define BMI055_BGW_SPI3_WDT_ADDR 0x34 253 /**< Address of BGW SPI3,WDT Register */ 254 255 /* Trim Register */ 256 #define BMI055_OFC1_ADDR 0x36 257 /**< Address of OFC1 Register */ 258 #define BMI055_OFC2_ADDR 0x37 259 /**< Address of OFC2 Register */ 260 #define BMI055_OFC3_ADDR 0x38 261 /**< Address of OFC3 Register */ 262 #define BMI055_OFC4_ADDR 0x39 263 /**< Address of OFC4 Register */ 264 #define BMI055_TRIM_GP0_ADDR 0x3A 265 /**< Address of Trim GP0 Register */ 266 #define BMI055_TRIM_GP1_ADDR 0x3B 267 /**< Address of Trim GP1 Register */ 268 #define BMI055_SELECTF_TEST_ADDR 0x3C 269 /**< Address of BGW Self test Register */ 270 271 /* Control Register */ 272 #define BMI055_FIFO_CGF1_ADDR 0x3D 273 /**< Address of FIFO CGF0 Register */ 274 #define BMI055_FIFO_CGF0_ADDR 0x3E 275 /**< Address of FIFO CGF1 Register */ 276 277 /* Data Register */ 278 #define BMI055_FIFO_DATA_ADDR 0x3F 279 /**< Address of FIFO Data Register */ 280 281 282 /**************************************************************************************************/ 283 284 class BMI055 :public SensorBase 285 { 286 public: 287 BMI055(int sensor_type, const char* iic_bus, int addr); 288 289 int read_reg(rt_uint8_t reg, rt_uint8_t* value); 290 int write_reg(rt_uint8_t reg, rt_uint8_t value); 291 int read_buffer(rt_uint8_t reg, rt_uint8_t* value, rt_size_t size); 292 293 private: 294 struct rt_i2c_bus_device *i2c_bus; 295 int i2c_addr; 296 }; 297 298 class BMI055_Accelerometer:public BMI055 299 { 300 public: 301 BMI055_Accelerometer(const char* iic_name, int addr); 302 303 virtual int configure(SensorConfig *config); 304 virtual int activate(int enable); 305 306 virtual int poll(sensors_event_t *event); 307 virtual void getSensor(sensor_t *sensor); 308 309 private: 310 rt_int16_t x_offset, y_offset, z_offset; 311 312 rt_bool_t enable; 313 float sensitivity; 314 }; 315 316 class BMI055_Gyroscope:public BMI055 317 { 318 public: 319 BMI055_Gyroscope(const char* iic_name, int addr); 320 321 virtual int configure(SensorConfig *config); 322 virtual int activate(int enable); 323 324 virtual int poll(sensors_event_t *event); 325 virtual void getSensor(sensor_t *sensor); 326 327 private: 328 rt_int16_t x_offset, y_offset, z_offset; 329 330 rt_bool_t enable; 331 float sensitivity; 332 }; 333 334 #endif 335