xref: /nrf52832-nimble/rt-thread/components/drivers/sensors/bmi055_sensor.h (revision 104654410c56c573564690304ae786df310c91fc)
1*10465441SEvalZero /*
2*10465441SEvalZero  * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero  *
4*10465441SEvalZero  * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero  *
6*10465441SEvalZero  * Change Logs:
7*10465441SEvalZero  * Date           Author           Notes
8*10465441SEvalZero  * 2015-1-11     RT_learning      the first version
9*10465441SEvalZero  */
10*10465441SEvalZero #ifndef __BMI055_H__
11*10465441SEvalZero #define __BMI055_H__
12*10465441SEvalZero 
13*10465441SEvalZero #include <sensor.h>
14*10465441SEvalZero 
15*10465441SEvalZero /**************************************************************************************************/
16*10465441SEvalZero /************************************Register map accelerometer************************************/
17*10465441SEvalZero 
18*10465441SEvalZero #define	BMI055_ACC_I2C_ADDR1			   	0x18        //SDO is low(GND)
19*10465441SEvalZero #define BMI055_ACC_I2C_ADDR2			   	0x19		//SDO is high(VCC)
20*10465441SEvalZero 
21*10465441SEvalZero #define BMI055_ACC_DEFAULT_ADDRESS     BMI055_ACC_I2C_ADDR2	//in the LPC54102 SPM-S
22*10465441SEvalZero 
23*10465441SEvalZero #define BMI055_ACC_BGW_CHIPID_VALUE			0xFA
24*10465441SEvalZero 
25*10465441SEvalZero #define BMI055_ACC_BGW_CHIPID			   	0x00
26*10465441SEvalZero /**<Address of ACC Chip ID Register					 	   	*/
27*10465441SEvalZero #define	BMI055_ACCD_X_LSB					0x02
28*10465441SEvalZero /**<        Address of X axis ACC LSB Register       	   	*/
29*10465441SEvalZero #define	BMI055_ACCD_X_MSB					0x03
30*10465441SEvalZero /**<        Address of X axis ACC MSB Register       	   	*/
31*10465441SEvalZero #define	BMI055_ACCD_Y_LSB					0x04
32*10465441SEvalZero /**<        Address of Y axis ACC LSB Register       	   	*/
33*10465441SEvalZero #define	BMI055_ACCD_Y_MSB					0x05
34*10465441SEvalZero /**<        Address of Y axis ACC MSB Register       	   	*/
35*10465441SEvalZero #define	BMI055_ACCD_Z_LSB					0x06
36*10465441SEvalZero /**<        Address of Z axis ACC LSB Register       	   	*/
37*10465441SEvalZero #define BMI055_ACCD_Z_MSB					0x07
38*10465441SEvalZero /**<        Address of Z axis ACC MSB Register       	   	*/
39*10465441SEvalZero #define BMI055_ACCD_TEMP					0x08
40*10465441SEvalZero /**<        Address of Temperature Data  Register  	 	   	*/
41*10465441SEvalZero 
42*10465441SEvalZero /* Status Register */
43*10465441SEvalZero #define BMI055_INT_STATUS_0					0x09
44*10465441SEvalZero /**<        Address of Interrupt status Register 0   	    */
45*10465441SEvalZero #define BMI055_INT_STATUS_1					0x0A
46*10465441SEvalZero /**<        Address of Interrupt status Register 1   	    */
47*10465441SEvalZero #define BMI055_INT_STATUS_2					0x0B
48*10465441SEvalZero /**<        Address of Interrupt status Register 2   	    */
49*10465441SEvalZero #define BMI055_INT_STATUS_3					0x0C
50*10465441SEvalZero /**<        Address of Interrupt status Register 3   	    */
51*10465441SEvalZero #define BMI055_FIFO_STATUS					0x0E
52*10465441SEvalZero /**<        Address of FIFO status Register          	    */
53*10465441SEvalZero 
54*10465441SEvalZero /* Control Register */
55*10465441SEvalZero #define BMI055_PMU_RANGE					0x0F
56*10465441SEvalZero /**<        Address of Range address Register     	  		*/
57*10465441SEvalZero #define BMI055_PMU_BW						0x10
58*10465441SEvalZero /**<        Address of Bandwidth Register             		*/
59*10465441SEvalZero #define BMI055_PMU_LPW						0x11
60*10465441SEvalZero /**<        Address of PMU LPW			             		*/
61*10465441SEvalZero #define BMI055_PMU_LOW_POWER				0x12
62*10465441SEvalZero /**<        Address of PMU LOW POWER     	        		*/
63*10465441SEvalZero #define	BMI055_ACCD_HBW						0x13
64*10465441SEvalZero /**<        Address of ACCD HBW			             		*/
65*10465441SEvalZero #define	BMI055_BGW_SOFTRESET				0x14
66*10465441SEvalZero /**<        Address of BGW SOFTRESET	             		*/
67*10465441SEvalZero #define	BMI055_INT_EN_0						0x16
68*10465441SEvalZero /**<        Address of interrupt engines in group 0    		*/
69*10465441SEvalZero #define	BMI055_INT_EN_1						0x17
70*10465441SEvalZero /**<        Address of interrupt engines in group 1   		*/
71*10465441SEvalZero #define	BMI055_INT_EN_2						0x18
72*10465441SEvalZero /**<        Address of interrupt engines in group 2   		*/
73*10465441SEvalZero #define	BMI055_INT_MAP_0					0x19
74*10465441SEvalZero /**<        Address of Interrupt MAP 0				   		*/
75*10465441SEvalZero #define BMI055_INT_MAP_1					0x1A
76*10465441SEvalZero /**<        Address of Interrupt MAP 1			     		*/
77*10465441SEvalZero #define BMI055_INT_MAP_2					0x1B
78*10465441SEvalZero /**<        Address of Interrupt MAP 2	             		*/
79*10465441SEvalZero #define BMI055_INT_SRC						0x1E
80*10465441SEvalZero /**<        Address of Interrupt source             		*/
81*10465441SEvalZero #define BMI055_INT_OUT_CTRL					0x20
82*10465441SEvalZero /**<        Address of Interrupt Register             		*/
83*10465441SEvalZero #define BMI055_INT_RST_LATCH				0x21
84*10465441SEvalZero /**<        Address of Interrupt reset and mode  Register	*/
85*10465441SEvalZero #define BMI055_INT_0						0x22
86*10465441SEvalZero /**<        Address of low-g Interrupt delay time Register	*/
87*10465441SEvalZero #define BMI055_INT_1						0x23
88*10465441SEvalZero /**<        Address of low-g Interrupt threshold Register	*/
89*10465441SEvalZero #define BMI055_INT_2						0x24
90*10465441SEvalZero /**<        Address of Interrupt 2 Register					*/
91*10465441SEvalZero #define BMI055_INT_3						0x25
92*10465441SEvalZero /**<        Address of high-g Interrupt delay time Register */
93*10465441SEvalZero #define BMI055_INT_4						0x26
94*10465441SEvalZero /**<        Address of high-g Interrupt threshold Register  */
95*10465441SEvalZero #define BMI055_INT_5						0x27
96*10465441SEvalZero /**<        Address of high-g Interrupt 5 Register		    */
97*10465441SEvalZero #define BMI055_INT_6						0x28
98*10465441SEvalZero /**<   Address of any-motion Interrupt threshold Register   */
99*10465441SEvalZero #define BMI055_INT_7						0x29
100*10465441SEvalZero /**< Address of slow/no-motion interrupt threshold Register */
101*10465441SEvalZero #define BMI055_INT_8						0x2A
102*10465441SEvalZero /**<        Address of high-g Interrupt 8 Register		    */
103*10465441SEvalZero #define BMI055_INT_9						0x2B
104*10465441SEvalZero /**<        Address of high-g Interrupt 9 Register		    */
105*10465441SEvalZero #define BMI055_INT_A						0x2C
106*10465441SEvalZero /**<        Address of Interrupt A Register		    		*/
107*10465441SEvalZero #define BMI055_INT_B						0x2D
108*10465441SEvalZero /**<        Address of Interrupt B Register		    		*/
109*10465441SEvalZero #define BMI055_INT_C						0x2E
110*10465441SEvalZero /**<        Address of Interrupt C Register		    		*/
111*10465441SEvalZero #define BMI055_INT_D						0x2F
112*10465441SEvalZero /**<        Address of Interrupt D Register		    		*/
113*10465441SEvalZero #define BMI055_FIFO_CONFIG_0				0x30
114*10465441SEvalZero /**<        Address of FIFO CONFIG 0 Register		    	*/
115*10465441SEvalZero #define BMI055_PMU_SELF_TEST				0x32
116*10465441SEvalZero /**<        Address of PMU SELF TEST Register		    	*/
117*10465441SEvalZero #define BMI055_TRIM_NVM_CTRL				0x33
118*10465441SEvalZero /**<        Address of TRIM NVM CTRL Register		    	*/
119*10465441SEvalZero #define BMI055_BGW_SPI3_WDT					0x34
120*10465441SEvalZero /**<        Address of BGW SPI3 WDT Register		    	*/
121*10465441SEvalZero #define BMI055_OFC_CTRL						0x36
122*10465441SEvalZero /**<        Address of OFC CTRL Register			    	*/
123*10465441SEvalZero #define BMI055_OFC_SETTING					0x37
124*10465441SEvalZero /**<        Address of OFC SETTING Register			    	*/
125*10465441SEvalZero #define BMI055_OFC_OFFSET_X					0x38
126*10465441SEvalZero /**<        Address of OFC OFFSET X Register			    */
127*10465441SEvalZero #define BMI055_OFC_OFFSET_Y					0x39
128*10465441SEvalZero /**<        Address of OFC OFFSET Y Register			    */
129*10465441SEvalZero #define BMI055_OFC_OFFSET_Z					0x3A
130*10465441SEvalZero /**<        Address of OFC OFFSET Z Register			    */
131*10465441SEvalZero 
132*10465441SEvalZero /* Trim Register */
133*10465441SEvalZero #define BMI055_TRIM_GP0						0x3B
134*10465441SEvalZero /**<        Address of TRIM GP0 Register				    */
135*10465441SEvalZero #define BMI055_TRIM_GP1						0x3C
136*10465441SEvalZero /**<        Address of TRIM GP1 Register				    */
137*10465441SEvalZero 
138*10465441SEvalZero /* Control Register */
139*10465441SEvalZero #define BMI055_FIFO_CONFIG_1				0x3E
140*10465441SEvalZero /**<        Address of FIFO CONFIG 1 Register			    */
141*10465441SEvalZero 
142*10465441SEvalZero /* Data Register */
143*10465441SEvalZero #define BMI055_FIFO_DATA					0x3F
144*10465441SEvalZero /**<        Address of FIFO DATA Register				    */
145*10465441SEvalZero 
146*10465441SEvalZero 
147*10465441SEvalZero /**************************************************************************************************/
148*10465441SEvalZero 
149*10465441SEvalZero 
150*10465441SEvalZero 
151*10465441SEvalZero 
152*10465441SEvalZero /**************************************************************************************************/
153*10465441SEvalZero /************************************Register map gyroscope****************************************/
154*10465441SEvalZero 
155*10465441SEvalZero 
156*10465441SEvalZero /**< This refers BMI055 return type as signed */
157*10465441SEvalZero 
158*10465441SEvalZero // #define	BMI055_I2C_ADDR1				0x68		//SDO is low(GND)
159*10465441SEvalZero // #define	BMI055_I2C_ADDR2				0x69		//SDO is high(VCC)
160*10465441SEvalZero #define	BMI055_GYRO_I2C_ADDR1				0x68		//SDO is low(GND)
161*10465441SEvalZero #define	BMI055_GYRO_I2C_ADDR2				0x69		//SDO is high(VCC)
162*10465441SEvalZero 
163*10465441SEvalZero #define BMI055_GYRO_DEFAULT_ADDRESS     BMI055_GYRO_I2C_ADDR2
164*10465441SEvalZero 
165*10465441SEvalZero #define BMI055_GRRO_CHIP_ID					0x0F
166*10465441SEvalZero 
167*10465441SEvalZero /*Define of registers*/
168*10465441SEvalZero 
169*10465441SEvalZero /* Hard Wired */
170*10465441SEvalZero #define BMI055_CHIP_ID_ADDR						 0x00
171*10465441SEvalZero /**<Address of Chip ID Register*/
172*10465441SEvalZero 
173*10465441SEvalZero /* Data Register */
174*10465441SEvalZero #define BMI055_RATE_X_LSB_ADDR                    0x02
175*10465441SEvalZero /**<        Address of X axis Rate LSB Register       		*/
176*10465441SEvalZero #define BMI055_RATE_X_MSB_ADDR                    0x03
177*10465441SEvalZero /**<        Address of X axis Rate MSB Register       		*/
178*10465441SEvalZero #define BMI055_RATE_Y_LSB_ADDR                    0x04
179*10465441SEvalZero /**<        Address of Y axis Rate LSB Register       		*/
180*10465441SEvalZero #define BMI055_RATE_Y_MSB_ADDR                     0x05
181*10465441SEvalZero /**<        Address of Y axis Rate MSB Register      		*/
182*10465441SEvalZero #define BMI055_RATE_Z_LSB_ADDR                     0x06
183*10465441SEvalZero /**<        Address of Z axis Rate LSB Register       		*/
184*10465441SEvalZero #define BMI055_RATE_Z_MSB_ADDR                     0x07
185*10465441SEvalZero /**<        Address of Z axis Rate MSB Register       		*/
186*10465441SEvalZero #define BMI055_TEMP_ADDR                           0x08
187*10465441SEvalZero /**<        Address of Temperature Data LSB Register  		*/
188*10465441SEvalZero 
189*10465441SEvalZero /* Status Register */
190*10465441SEvalZero #define BMI055_INTR_STAT0_ADDR                     0x09
191*10465441SEvalZero /**<        Address of Interrupt status Register 0    		*/
192*10465441SEvalZero #define BMI055_INTR_STAT1_ADDR                     0x0A
193*10465441SEvalZero /**<        Address of Interrupt status Register 1    		*/
194*10465441SEvalZero #define BMI055_INTR_STAT2_ADDR                     0x0B
195*10465441SEvalZero /**<        Address of Interrupt status Register 2    		*/
196*10465441SEvalZero #define BMI055_INTR_STAT3_ADDR                     0x0C
197*10465441SEvalZero /**<        Address of Interrupt status Register 3    		*/
198*10465441SEvalZero #define BMI055_FIFO_STAT_ADDR                      0x0E
199*10465441SEvalZero /**<        Address of FIFO status Register           		*/
200*10465441SEvalZero 
201*10465441SEvalZero /* Control Register */
202*10465441SEvalZero #define BMI055_RANGE_ADDR                         0x0F
203*10465441SEvalZero /**<        Address of Range address Register     			*/
204*10465441SEvalZero #define BMI055_BW_ADDR                            0x10
205*10465441SEvalZero /**<        Address of Bandwidth Register         			*/
206*10465441SEvalZero #define BMI055_MODE_LPM1_ADDR                     0x11
207*10465441SEvalZero /**<        Address of Mode LPM1 Register         			*/
208*10465441SEvalZero #define BMI055_MODE_LPM2_ADDR                     0x12
209*10465441SEvalZero /**<        Address of Mode LPM2 Register         			*/
210*10465441SEvalZero #define BMI055_HIGH_BW_ADDR                       0x13
211*10465441SEvalZero /**<        Address of Rate HIGH_BW Register       			*/
212*10465441SEvalZero #define BMI055_BGW_SOFT_RST_ADDR                  0x14
213*10465441SEvalZero /**<        Address of BGW Softreset Register      			*/
214*10465441SEvalZero #define BMI055_INTR_ENABLE0_ADDR                  0x15
215*10465441SEvalZero /**<        Address of Interrupt Enable 0             		*/
216*10465441SEvalZero #define BMI055_INTR_ENABLE1_ADDR                  0x16
217*10465441SEvalZero /**<        Address of Interrupt Enable 1             		*/
218*10465441SEvalZero #define BMI055_INTR_MAP_ZERO_ADDR                 0x17
219*10465441SEvalZero /**<        Address of Interrupt MAP 0                		*/
220*10465441SEvalZero #define BMI055_INTR_MAP_ONE_ADDR                  0x18
221*10465441SEvalZero /**<        Address of Interrupt MAP 1                		*/
222*10465441SEvalZero #define BMI055_INTR_MAP_TWO_ADDR                  0x19
223*10465441SEvalZero /**<        Address of Interrupt MAP 2                		*/
224*10465441SEvalZero #define BMI055_INTR_ZERO_ADDR                     0x1A
225*10465441SEvalZero /**<        Address of Interrupt 0 register   				*/
226*10465441SEvalZero #define BMI055_INTR_ONE_ADDR                      0x1B
227*10465441SEvalZero /**<        Address of Interrupt 1 register   				*/
228*10465441SEvalZero #define BMI055_INTR_TWO_ADDR                      0x1C
229*10465441SEvalZero /**<        Address of Interrupt 2 register   				*/
230*10465441SEvalZero #define BMI055_INTR_4_ADDR                        0x1E
231*10465441SEvalZero /**<        Address of Interrupt 4 register   				*/
232*10465441SEvalZero #define BMI055_RST_LATCH_ADDR                     0x21
233*10465441SEvalZero /**<        Address of Reset Latch Register           		*/
234*10465441SEvalZero #define BMI055_HIGHRATE_THRES_X_ADDR              0x22
235*10465441SEvalZero /**<        Address of High Th x Address register     		*/
236*10465441SEvalZero #define BMI055_HIGHRATE_DURN_X_ADDR               0x23
237*10465441SEvalZero /**<        Address of High Dur x Address register    		*/
238*10465441SEvalZero #define BMI055_HIGHRATE_THRES_Y_ADDR              0x24
239*10465441SEvalZero /**<        Address of High Th y  Address register    		*/
240*10465441SEvalZero #define BMI055_HIGHRATE_DURN_Y_ADDR               0x25
241*10465441SEvalZero /**<        Address of High Dur y Address register    		*/
242*10465441SEvalZero #define BMI055_HIGHRATE_THRES_Z_ADDR              0x26
243*10465441SEvalZero /**<        Address of High Th z Address register  			*/
244*10465441SEvalZero #define BMI055_HIGHRATE_DURN_Z_ADDR               0x27
245*10465441SEvalZero /**<        Address of High Dur z Address register  		*/
246*10465441SEvalZero #define BMI055_SOC_ADDR                           0x31
247*10465441SEvalZero /**<        Address of SOC register        					*/
248*10465441SEvalZero #define BMI055_A_FOC_ADDR                         0x32
249*10465441SEvalZero /**<        Address of A_FOC Register        				*/
250*10465441SEvalZero #define BMI055_TRIM_NVM_CTRL_ADDR                 0x33
251*10465441SEvalZero /**<        Address of Trim NVM control register    		*/
252*10465441SEvalZero #define BMI055_BGW_SPI3_WDT_ADDR                  0x34
253*10465441SEvalZero /**<        Address of BGW SPI3,WDT Register           		*/
254*10465441SEvalZero 
255*10465441SEvalZero /* Trim Register */
256*10465441SEvalZero #define BMI055_OFC1_ADDR                   0x36
257*10465441SEvalZero /**<        Address of OFC1 Register          				*/
258*10465441SEvalZero #define BMI055_OFC2_ADDR                   0x37
259*10465441SEvalZero /**<        Address of OFC2 Register          				*/
260*10465441SEvalZero #define BMI055_OFC3_ADDR                   0x38
261*10465441SEvalZero /**<        Address of OFC3 Register          				*/
262*10465441SEvalZero #define BMI055_OFC4_ADDR                   0x39
263*10465441SEvalZero /**<        Address of OFC4 Register          				*/
264*10465441SEvalZero #define BMI055_TRIM_GP0_ADDR               0x3A
265*10465441SEvalZero /**<        Address of Trim GP0 Register              		*/
266*10465441SEvalZero #define BMI055_TRIM_GP1_ADDR               0x3B
267*10465441SEvalZero /**<        Address of Trim GP1 Register              		*/
268*10465441SEvalZero #define BMI055_SELECTF_TEST_ADDR            0x3C
269*10465441SEvalZero /**<        Address of BGW Self test Register         		*/
270*10465441SEvalZero 
271*10465441SEvalZero /* Control Register */
272*10465441SEvalZero #define BMI055_FIFO_CGF1_ADDR              0x3D
273*10465441SEvalZero /**<        Address of FIFO CGF0 Register             		*/
274*10465441SEvalZero #define BMI055_FIFO_CGF0_ADDR              0x3E
275*10465441SEvalZero /**<        Address of FIFO CGF1 Register             		*/
276*10465441SEvalZero 
277*10465441SEvalZero /* Data Register */
278*10465441SEvalZero #define BMI055_FIFO_DATA_ADDR              0x3F
279*10465441SEvalZero /**<        Address of FIFO Data Register             		*/
280*10465441SEvalZero 
281*10465441SEvalZero 
282*10465441SEvalZero /**************************************************************************************************/
283*10465441SEvalZero 
284*10465441SEvalZero class BMI055 :public SensorBase
285*10465441SEvalZero {
286*10465441SEvalZero public:
287*10465441SEvalZero     BMI055(int sensor_type, const char* iic_bus, int addr);
288*10465441SEvalZero 
289*10465441SEvalZero     int read_reg(rt_uint8_t reg, rt_uint8_t* value);
290*10465441SEvalZero     int write_reg(rt_uint8_t reg, rt_uint8_t value);
291*10465441SEvalZero     int read_buffer(rt_uint8_t reg, rt_uint8_t* value, rt_size_t size);
292*10465441SEvalZero 
293*10465441SEvalZero private:
294*10465441SEvalZero     struct rt_i2c_bus_device *i2c_bus;
295*10465441SEvalZero     int i2c_addr;
296*10465441SEvalZero };
297*10465441SEvalZero 
298*10465441SEvalZero class BMI055_Accelerometer:public BMI055
299*10465441SEvalZero {
300*10465441SEvalZero public:
301*10465441SEvalZero     BMI055_Accelerometer(const char* iic_name, int addr);
302*10465441SEvalZero 
303*10465441SEvalZero     virtual int configure(SensorConfig *config);
304*10465441SEvalZero     virtual int activate(int enable);
305*10465441SEvalZero 
306*10465441SEvalZero     virtual int poll(sensors_event_t *event);
307*10465441SEvalZero     virtual void getSensor(sensor_t *sensor);
308*10465441SEvalZero 
309*10465441SEvalZero private:
310*10465441SEvalZero 	rt_int16_t x_offset, y_offset, z_offset;
311*10465441SEvalZero 
312*10465441SEvalZero 	rt_bool_t enable;
313*10465441SEvalZero 	float sensitivity;
314*10465441SEvalZero };
315*10465441SEvalZero 
316*10465441SEvalZero class BMI055_Gyroscope:public BMI055
317*10465441SEvalZero {
318*10465441SEvalZero public:
319*10465441SEvalZero     BMI055_Gyroscope(const char* iic_name, int addr);
320*10465441SEvalZero 
321*10465441SEvalZero     virtual int configure(SensorConfig *config);
322*10465441SEvalZero     virtual int activate(int enable);
323*10465441SEvalZero 
324*10465441SEvalZero     virtual int poll(sensors_event_t *event);
325*10465441SEvalZero     virtual void getSensor(sensor_t *sensor);
326*10465441SEvalZero 
327*10465441SEvalZero private:
328*10465441SEvalZero 	rt_int16_t x_offset, y_offset, z_offset;
329*10465441SEvalZero 
330*10465441SEvalZero 	rt_bool_t enable;
331*10465441SEvalZero 	float sensitivity;
332*10465441SEvalZero };
333*10465441SEvalZero 
334*10465441SEvalZero #endif
335