1*10465441SEvalZero /*
2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero *
4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero *
6*10465441SEvalZero * Change Logs:
7*10465441SEvalZero * Date Author Notes
8*10465441SEvalZero * 2012-04-25 weety first version
9*10465441SEvalZero */
10*10465441SEvalZero
11*10465441SEvalZero #include <rtdevice.h>
12*10465441SEvalZero
13*10465441SEvalZero #ifdef RT_I2C_BIT_DEBUG
14*10465441SEvalZero #define bit_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
15*10465441SEvalZero #else
16*10465441SEvalZero #define bit_dbg(fmt, ...)
17*10465441SEvalZero #endif
18*10465441SEvalZero
19*10465441SEvalZero #define SET_SDA(ops, val) ops->set_sda(ops->data, val)
20*10465441SEvalZero #define SET_SCL(ops, val) ops->set_scl(ops->data, val)
21*10465441SEvalZero #define GET_SDA(ops) ops->get_sda(ops->data)
22*10465441SEvalZero #define GET_SCL(ops) ops->get_scl(ops->data)
23*10465441SEvalZero
i2c_delay(struct rt_i2c_bit_ops * ops)24*10465441SEvalZero rt_inline void i2c_delay(struct rt_i2c_bit_ops *ops)
25*10465441SEvalZero {
26*10465441SEvalZero ops->udelay((ops->delay_us + 1) >> 1);
27*10465441SEvalZero }
28*10465441SEvalZero
i2c_delay2(struct rt_i2c_bit_ops * ops)29*10465441SEvalZero rt_inline void i2c_delay2(struct rt_i2c_bit_ops *ops)
30*10465441SEvalZero {
31*10465441SEvalZero ops->udelay(ops->delay_us);
32*10465441SEvalZero }
33*10465441SEvalZero
34*10465441SEvalZero #define SDA_L(ops) SET_SDA(ops, 0)
35*10465441SEvalZero #define SDA_H(ops) SET_SDA(ops, 1)
36*10465441SEvalZero #define SCL_L(ops) SET_SCL(ops, 0)
37*10465441SEvalZero
38*10465441SEvalZero /**
39*10465441SEvalZero * release scl line, and wait scl line to high.
40*10465441SEvalZero */
SCL_H(struct rt_i2c_bit_ops * ops)41*10465441SEvalZero static rt_err_t SCL_H(struct rt_i2c_bit_ops *ops)
42*10465441SEvalZero {
43*10465441SEvalZero rt_tick_t start;
44*10465441SEvalZero
45*10465441SEvalZero SET_SCL(ops, 1);
46*10465441SEvalZero
47*10465441SEvalZero if (!ops->get_scl)
48*10465441SEvalZero goto done;
49*10465441SEvalZero
50*10465441SEvalZero start = rt_tick_get();
51*10465441SEvalZero while (!GET_SCL(ops))
52*10465441SEvalZero {
53*10465441SEvalZero if ((rt_tick_get() - start) > ops->timeout)
54*10465441SEvalZero return -RT_ETIMEOUT;
55*10465441SEvalZero rt_thread_delay((ops->timeout + 1) >> 1);
56*10465441SEvalZero }
57*10465441SEvalZero #ifdef RT_I2C_BIT_DEBUG
58*10465441SEvalZero if (rt_tick_get() != start)
59*10465441SEvalZero {
60*10465441SEvalZero bit_dbg("wait %ld tick for SCL line to go high\n",
61*10465441SEvalZero rt_tick_get() - start);
62*10465441SEvalZero }
63*10465441SEvalZero #endif
64*10465441SEvalZero
65*10465441SEvalZero done:
66*10465441SEvalZero i2c_delay(ops);
67*10465441SEvalZero
68*10465441SEvalZero return RT_EOK;
69*10465441SEvalZero }
70*10465441SEvalZero
i2c_start(struct rt_i2c_bit_ops * ops)71*10465441SEvalZero static void i2c_start(struct rt_i2c_bit_ops *ops)
72*10465441SEvalZero {
73*10465441SEvalZero #ifdef RT_I2C_BIT_DEBUG
74*10465441SEvalZero if (ops->get_scl && !GET_SCL(ops))
75*10465441SEvalZero {
76*10465441SEvalZero bit_dbg("I2C bus error, SCL line low\n");
77*10465441SEvalZero }
78*10465441SEvalZero if (ops->get_sda && !GET_SDA(ops))
79*10465441SEvalZero {
80*10465441SEvalZero bit_dbg("I2C bus error, SDA line low\n");
81*10465441SEvalZero }
82*10465441SEvalZero #endif
83*10465441SEvalZero SDA_L(ops);
84*10465441SEvalZero i2c_delay(ops);
85*10465441SEvalZero SCL_L(ops);
86*10465441SEvalZero }
87*10465441SEvalZero
i2c_restart(struct rt_i2c_bit_ops * ops)88*10465441SEvalZero static void i2c_restart(struct rt_i2c_bit_ops *ops)
89*10465441SEvalZero {
90*10465441SEvalZero SDA_H(ops);
91*10465441SEvalZero SCL_H(ops);
92*10465441SEvalZero i2c_delay(ops);
93*10465441SEvalZero SDA_L(ops);
94*10465441SEvalZero i2c_delay(ops);
95*10465441SEvalZero SCL_L(ops);
96*10465441SEvalZero }
97*10465441SEvalZero
i2c_stop(struct rt_i2c_bit_ops * ops)98*10465441SEvalZero static void i2c_stop(struct rt_i2c_bit_ops *ops)
99*10465441SEvalZero {
100*10465441SEvalZero SDA_L(ops);
101*10465441SEvalZero i2c_delay(ops);
102*10465441SEvalZero SCL_H(ops);
103*10465441SEvalZero i2c_delay(ops);
104*10465441SEvalZero SDA_H(ops);
105*10465441SEvalZero i2c_delay2(ops);
106*10465441SEvalZero }
107*10465441SEvalZero
i2c_waitack(struct rt_i2c_bit_ops * ops)108*10465441SEvalZero rt_inline rt_bool_t i2c_waitack(struct rt_i2c_bit_ops *ops)
109*10465441SEvalZero {
110*10465441SEvalZero rt_bool_t ack;
111*10465441SEvalZero
112*10465441SEvalZero SDA_H(ops);
113*10465441SEvalZero i2c_delay(ops);
114*10465441SEvalZero
115*10465441SEvalZero if (SCL_H(ops) < 0)
116*10465441SEvalZero {
117*10465441SEvalZero bit_dbg("wait ack timeout\n");
118*10465441SEvalZero
119*10465441SEvalZero return -RT_ETIMEOUT;
120*10465441SEvalZero }
121*10465441SEvalZero
122*10465441SEvalZero ack = !GET_SDA(ops); /* ACK : SDA pin is pulled low */
123*10465441SEvalZero bit_dbg("%s\n", ack ? "ACK" : "NACK");
124*10465441SEvalZero
125*10465441SEvalZero SCL_L(ops);
126*10465441SEvalZero
127*10465441SEvalZero return ack;
128*10465441SEvalZero }
129*10465441SEvalZero
i2c_writeb(struct rt_i2c_bus_device * bus,rt_uint8_t data)130*10465441SEvalZero static rt_int32_t i2c_writeb(struct rt_i2c_bus_device *bus, rt_uint8_t data)
131*10465441SEvalZero {
132*10465441SEvalZero rt_int32_t i;
133*10465441SEvalZero rt_uint8_t bit;
134*10465441SEvalZero
135*10465441SEvalZero struct rt_i2c_bit_ops *ops = bus->priv;
136*10465441SEvalZero
137*10465441SEvalZero for (i = 7; i >= 0; i--)
138*10465441SEvalZero {
139*10465441SEvalZero SCL_L(ops);
140*10465441SEvalZero bit = (data >> i) & 1;
141*10465441SEvalZero SET_SDA(ops, bit);
142*10465441SEvalZero i2c_delay(ops);
143*10465441SEvalZero if (SCL_H(ops) < 0)
144*10465441SEvalZero {
145*10465441SEvalZero bit_dbg("i2c_writeb: 0x%02x, "
146*10465441SEvalZero "wait scl pin high timeout at bit %d\n",
147*10465441SEvalZero data, i);
148*10465441SEvalZero
149*10465441SEvalZero return -RT_ETIMEOUT;
150*10465441SEvalZero }
151*10465441SEvalZero }
152*10465441SEvalZero SCL_L(ops);
153*10465441SEvalZero i2c_delay(ops);
154*10465441SEvalZero
155*10465441SEvalZero return i2c_waitack(ops);
156*10465441SEvalZero }
157*10465441SEvalZero
i2c_readb(struct rt_i2c_bus_device * bus)158*10465441SEvalZero static rt_int32_t i2c_readb(struct rt_i2c_bus_device *bus)
159*10465441SEvalZero {
160*10465441SEvalZero rt_uint8_t i;
161*10465441SEvalZero rt_uint8_t data = 0;
162*10465441SEvalZero struct rt_i2c_bit_ops *ops = bus->priv;
163*10465441SEvalZero
164*10465441SEvalZero SDA_H(ops);
165*10465441SEvalZero i2c_delay(ops);
166*10465441SEvalZero for (i = 0; i < 8; i++)
167*10465441SEvalZero {
168*10465441SEvalZero data <<= 1;
169*10465441SEvalZero
170*10465441SEvalZero if (SCL_H(ops) < 0)
171*10465441SEvalZero {
172*10465441SEvalZero bit_dbg("i2c_readb: wait scl pin high "
173*10465441SEvalZero "timeout at bit %d\n", 7 - i);
174*10465441SEvalZero
175*10465441SEvalZero return -RT_ETIMEOUT;
176*10465441SEvalZero }
177*10465441SEvalZero
178*10465441SEvalZero if (GET_SDA(ops))
179*10465441SEvalZero data |= 1;
180*10465441SEvalZero SCL_L(ops);
181*10465441SEvalZero i2c_delay2(ops);
182*10465441SEvalZero }
183*10465441SEvalZero
184*10465441SEvalZero return data;
185*10465441SEvalZero }
186*10465441SEvalZero
i2c_send_bytes(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg)187*10465441SEvalZero static rt_size_t i2c_send_bytes(struct rt_i2c_bus_device *bus,
188*10465441SEvalZero struct rt_i2c_msg *msg)
189*10465441SEvalZero {
190*10465441SEvalZero rt_int32_t ret;
191*10465441SEvalZero rt_size_t bytes = 0;
192*10465441SEvalZero const rt_uint8_t *ptr = msg->buf;
193*10465441SEvalZero rt_int32_t count = msg->len;
194*10465441SEvalZero rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
195*10465441SEvalZero
196*10465441SEvalZero while (count > 0)
197*10465441SEvalZero {
198*10465441SEvalZero ret = i2c_writeb(bus, *ptr);
199*10465441SEvalZero
200*10465441SEvalZero if ((ret > 0) || (ignore_nack && (ret == 0)))
201*10465441SEvalZero {
202*10465441SEvalZero count --;
203*10465441SEvalZero ptr ++;
204*10465441SEvalZero bytes ++;
205*10465441SEvalZero }
206*10465441SEvalZero else if (ret == 0)
207*10465441SEvalZero {
208*10465441SEvalZero i2c_dbg("send bytes: NACK.\n");
209*10465441SEvalZero
210*10465441SEvalZero return 0;
211*10465441SEvalZero }
212*10465441SEvalZero else
213*10465441SEvalZero {
214*10465441SEvalZero i2c_dbg("send bytes: error %d\n", ret);
215*10465441SEvalZero
216*10465441SEvalZero return ret;
217*10465441SEvalZero }
218*10465441SEvalZero }
219*10465441SEvalZero
220*10465441SEvalZero return bytes;
221*10465441SEvalZero }
222*10465441SEvalZero
i2c_send_ack_or_nack(struct rt_i2c_bus_device * bus,int ack)223*10465441SEvalZero static rt_err_t i2c_send_ack_or_nack(struct rt_i2c_bus_device *bus, int ack)
224*10465441SEvalZero {
225*10465441SEvalZero struct rt_i2c_bit_ops *ops = bus->priv;
226*10465441SEvalZero
227*10465441SEvalZero if (ack)
228*10465441SEvalZero SET_SDA(ops, 0);
229*10465441SEvalZero i2c_delay(ops);
230*10465441SEvalZero if (SCL_H(ops) < 0)
231*10465441SEvalZero {
232*10465441SEvalZero bit_dbg("ACK or NACK timeout\n");
233*10465441SEvalZero
234*10465441SEvalZero return -RT_ETIMEOUT;
235*10465441SEvalZero }
236*10465441SEvalZero SCL_L(ops);
237*10465441SEvalZero
238*10465441SEvalZero return RT_EOK;
239*10465441SEvalZero }
240*10465441SEvalZero
i2c_recv_bytes(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg)241*10465441SEvalZero static rt_size_t i2c_recv_bytes(struct rt_i2c_bus_device *bus,
242*10465441SEvalZero struct rt_i2c_msg *msg)
243*10465441SEvalZero {
244*10465441SEvalZero rt_int32_t val;
245*10465441SEvalZero rt_int32_t bytes = 0; /* actual bytes */
246*10465441SEvalZero rt_uint8_t *ptr = msg->buf;
247*10465441SEvalZero rt_int32_t count = msg->len;
248*10465441SEvalZero const rt_uint32_t flags = msg->flags;
249*10465441SEvalZero
250*10465441SEvalZero while (count > 0)
251*10465441SEvalZero {
252*10465441SEvalZero val = i2c_readb(bus);
253*10465441SEvalZero if (val >= 0)
254*10465441SEvalZero {
255*10465441SEvalZero *ptr = val;
256*10465441SEvalZero bytes ++;
257*10465441SEvalZero }
258*10465441SEvalZero else
259*10465441SEvalZero {
260*10465441SEvalZero break;
261*10465441SEvalZero }
262*10465441SEvalZero
263*10465441SEvalZero ptr ++;
264*10465441SEvalZero count --;
265*10465441SEvalZero
266*10465441SEvalZero bit_dbg("recieve bytes: 0x%02x, %s\n",
267*10465441SEvalZero val, (flags & RT_I2C_NO_READ_ACK) ?
268*10465441SEvalZero "(No ACK/NACK)" : (count ? "ACK" : "NACK"));
269*10465441SEvalZero
270*10465441SEvalZero if (!(flags & RT_I2C_NO_READ_ACK))
271*10465441SEvalZero {
272*10465441SEvalZero val = i2c_send_ack_or_nack(bus, count);
273*10465441SEvalZero if (val < 0)
274*10465441SEvalZero return val;
275*10465441SEvalZero }
276*10465441SEvalZero }
277*10465441SEvalZero
278*10465441SEvalZero return bytes;
279*10465441SEvalZero }
280*10465441SEvalZero
i2c_send_address(struct rt_i2c_bus_device * bus,rt_uint8_t addr,rt_int32_t retries)281*10465441SEvalZero static rt_int32_t i2c_send_address(struct rt_i2c_bus_device *bus,
282*10465441SEvalZero rt_uint8_t addr,
283*10465441SEvalZero rt_int32_t retries)
284*10465441SEvalZero {
285*10465441SEvalZero struct rt_i2c_bit_ops *ops = bus->priv;
286*10465441SEvalZero rt_int32_t i;
287*10465441SEvalZero rt_err_t ret = 0;
288*10465441SEvalZero
289*10465441SEvalZero for (i = 0; i <= retries; i++)
290*10465441SEvalZero {
291*10465441SEvalZero ret = i2c_writeb(bus, addr);
292*10465441SEvalZero if (ret == 1 || i == retries)
293*10465441SEvalZero break;
294*10465441SEvalZero bit_dbg("send stop condition\n");
295*10465441SEvalZero i2c_stop(ops);
296*10465441SEvalZero i2c_delay2(ops);
297*10465441SEvalZero bit_dbg("send start condition\n");
298*10465441SEvalZero i2c_start(ops);
299*10465441SEvalZero }
300*10465441SEvalZero
301*10465441SEvalZero return ret;
302*10465441SEvalZero }
303*10465441SEvalZero
i2c_bit_send_address(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg)304*10465441SEvalZero static rt_err_t i2c_bit_send_address(struct rt_i2c_bus_device *bus,
305*10465441SEvalZero struct rt_i2c_msg *msg)
306*10465441SEvalZero {
307*10465441SEvalZero rt_uint16_t flags = msg->flags;
308*10465441SEvalZero rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
309*10465441SEvalZero struct rt_i2c_bit_ops *ops = bus->priv;
310*10465441SEvalZero
311*10465441SEvalZero rt_uint8_t addr1, addr2;
312*10465441SEvalZero rt_int32_t retries;
313*10465441SEvalZero rt_err_t ret;
314*10465441SEvalZero
315*10465441SEvalZero retries = ignore_nack ? 0 : bus->retries;
316*10465441SEvalZero
317*10465441SEvalZero if (flags & RT_I2C_ADDR_10BIT)
318*10465441SEvalZero {
319*10465441SEvalZero addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
320*10465441SEvalZero addr2 = msg->addr & 0xff;
321*10465441SEvalZero
322*10465441SEvalZero bit_dbg("addr1: %d, addr2: %d\n", addr1, addr2);
323*10465441SEvalZero
324*10465441SEvalZero ret = i2c_send_address(bus, addr1, retries);
325*10465441SEvalZero if ((ret != 1) && !ignore_nack)
326*10465441SEvalZero {
327*10465441SEvalZero bit_dbg("NACK: sending first addr\n");
328*10465441SEvalZero
329*10465441SEvalZero return -RT_EIO;
330*10465441SEvalZero }
331*10465441SEvalZero
332*10465441SEvalZero ret = i2c_writeb(bus, addr2);
333*10465441SEvalZero if ((ret != 1) && !ignore_nack)
334*10465441SEvalZero {
335*10465441SEvalZero bit_dbg("NACK: sending second addr\n");
336*10465441SEvalZero
337*10465441SEvalZero return -RT_EIO;
338*10465441SEvalZero }
339*10465441SEvalZero if (flags & RT_I2C_RD)
340*10465441SEvalZero {
341*10465441SEvalZero bit_dbg("send repeated start condition\n");
342*10465441SEvalZero i2c_restart(ops);
343*10465441SEvalZero addr1 |= 0x01;
344*10465441SEvalZero ret = i2c_send_address(bus, addr1, retries);
345*10465441SEvalZero if ((ret != 1) && !ignore_nack)
346*10465441SEvalZero {
347*10465441SEvalZero bit_dbg("NACK: sending repeated addr\n");
348*10465441SEvalZero
349*10465441SEvalZero return -RT_EIO;
350*10465441SEvalZero }
351*10465441SEvalZero }
352*10465441SEvalZero }
353*10465441SEvalZero else
354*10465441SEvalZero {
355*10465441SEvalZero /* 7-bit addr */
356*10465441SEvalZero addr1 = msg->addr << 1;
357*10465441SEvalZero if (flags & RT_I2C_RD)
358*10465441SEvalZero addr1 |= 1;
359*10465441SEvalZero ret = i2c_send_address(bus, addr1, retries);
360*10465441SEvalZero if ((ret != 1) && !ignore_nack)
361*10465441SEvalZero return -RT_EIO;
362*10465441SEvalZero }
363*10465441SEvalZero
364*10465441SEvalZero return RT_EOK;
365*10465441SEvalZero }
366*10465441SEvalZero
i2c_bit_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],rt_uint32_t num)367*10465441SEvalZero static rt_size_t i2c_bit_xfer(struct rt_i2c_bus_device *bus,
368*10465441SEvalZero struct rt_i2c_msg msgs[],
369*10465441SEvalZero rt_uint32_t num)
370*10465441SEvalZero {
371*10465441SEvalZero struct rt_i2c_msg *msg;
372*10465441SEvalZero struct rt_i2c_bit_ops *ops = bus->priv;
373*10465441SEvalZero rt_int32_t i, ret;
374*10465441SEvalZero rt_uint16_t ignore_nack;
375*10465441SEvalZero
376*10465441SEvalZero bit_dbg("send start condition\n");
377*10465441SEvalZero i2c_start(ops);
378*10465441SEvalZero for (i = 0; i < num; i++)
379*10465441SEvalZero {
380*10465441SEvalZero msg = &msgs[i];
381*10465441SEvalZero ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
382*10465441SEvalZero if (!(msg->flags & RT_I2C_NO_START))
383*10465441SEvalZero {
384*10465441SEvalZero if (i)
385*10465441SEvalZero {
386*10465441SEvalZero i2c_restart(ops);
387*10465441SEvalZero }
388*10465441SEvalZero ret = i2c_bit_send_address(bus, msg);
389*10465441SEvalZero if ((ret != RT_EOK) && !ignore_nack)
390*10465441SEvalZero {
391*10465441SEvalZero bit_dbg("receive NACK from device addr 0x%02x msg %d\n",
392*10465441SEvalZero msgs[i].addr, i);
393*10465441SEvalZero goto out;
394*10465441SEvalZero }
395*10465441SEvalZero }
396*10465441SEvalZero if (msg->flags & RT_I2C_RD)
397*10465441SEvalZero {
398*10465441SEvalZero ret = i2c_recv_bytes(bus, msg);
399*10465441SEvalZero if (ret >= 1)
400*10465441SEvalZero bit_dbg("read %d byte%s\n", ret, ret == 1 ? "" : "s");
401*10465441SEvalZero if (ret < msg->len)
402*10465441SEvalZero {
403*10465441SEvalZero if (ret >= 0)
404*10465441SEvalZero ret = -RT_EIO;
405*10465441SEvalZero goto out;
406*10465441SEvalZero }
407*10465441SEvalZero }
408*10465441SEvalZero else
409*10465441SEvalZero {
410*10465441SEvalZero ret = i2c_send_bytes(bus, msg);
411*10465441SEvalZero if (ret >= 1)
412*10465441SEvalZero bit_dbg("write %d byte%s\n", ret, ret == 1 ? "" : "s");
413*10465441SEvalZero if (ret < msg->len)
414*10465441SEvalZero {
415*10465441SEvalZero if (ret >= 0)
416*10465441SEvalZero ret = -RT_ERROR;
417*10465441SEvalZero goto out;
418*10465441SEvalZero }
419*10465441SEvalZero }
420*10465441SEvalZero }
421*10465441SEvalZero ret = i;
422*10465441SEvalZero
423*10465441SEvalZero out:
424*10465441SEvalZero bit_dbg("send stop condition\n");
425*10465441SEvalZero i2c_stop(ops);
426*10465441SEvalZero
427*10465441SEvalZero return ret;
428*10465441SEvalZero }
429*10465441SEvalZero
430*10465441SEvalZero static const struct rt_i2c_bus_device_ops i2c_bit_bus_ops =
431*10465441SEvalZero {
432*10465441SEvalZero i2c_bit_xfer,
433*10465441SEvalZero RT_NULL,
434*10465441SEvalZero RT_NULL
435*10465441SEvalZero };
436*10465441SEvalZero
rt_i2c_bit_add_bus(struct rt_i2c_bus_device * bus,const char * bus_name)437*10465441SEvalZero rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
438*10465441SEvalZero const char *bus_name)
439*10465441SEvalZero {
440*10465441SEvalZero bus->ops = &i2c_bit_bus_ops;
441*10465441SEvalZero
442*10465441SEvalZero return rt_i2c_bus_device_register(bus, bus_name);
443*10465441SEvalZero }
444