1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38 #if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #ifndef __CORE_SC000_H_GENERIC
47 #define __CORE_SC000_H_GENERIC
48
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63 /*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66 /** \ingroup SC000
67 @{
68 */
69
70 /* CMSIS SC000 definitions */
71 #define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72 #define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76 #define __CORTEX_SC (0) /*!< Cortex secure core */
77
78
79 #if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84 #elif defined ( __ICCARM__ )
85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
87 #define __STATIC_INLINE static inline
88
89 #elif defined ( __GNUC__ )
90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
92 #define __STATIC_INLINE static inline
93
94 #elif defined ( __TASKING__ )
95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
97 #define __STATIC_INLINE static inline
98
99 #endif
100
101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
102 */
103 #define __FPU_USED 0
104
105 #if defined ( __CC_ARM )
106 #if defined __TARGET_FPU_VFP
107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #endif
109
110 #elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113 #endif
114
115 #elif defined ( __GNUC__ )
116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120 #elif defined ( __TASKING__ )
121 #if defined __FPU_VFP__
122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124 #endif
125
126 #include <stdint.h> /* standard types definitions */
127 #include <core_cmInstr.h> /* Core Instruction Access */
128 #include <core_cmFunc.h> /* Core Function Access */
129
130 #endif /* __CORE_SC000_H_GENERIC */
131
132 #ifndef __CMSIS_GENERIC
133
134 #ifndef __CORE_SC000_H_DEPENDANT
135 #define __CORE_SC000_H_DEPENDANT
136
137 /* check device defines and use defaults */
138 #if defined __CHECK_DEVICE_DEFINES
139 #ifndef __SC000_REV
140 #define __SC000_REV 0x0000
141 #warning "__SC000_REV not defined in device header file; using default!"
142 #endif
143
144 #ifndef __MPU_PRESENT
145 #define __MPU_PRESENT 0
146 #warning "__MPU_PRESENT not defined in device header file; using default!"
147 #endif
148
149 #ifndef __NVIC_PRIO_BITS
150 #define __NVIC_PRIO_BITS 2
151 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
152 #endif
153
154 #ifndef __Vendor_SysTickConfig
155 #define __Vendor_SysTickConfig 0
156 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
157 #endif
158 #endif
159
160 /* IO definitions (access restrictions to peripheral registers) */
161 /**
162 \defgroup CMSIS_glob_defs CMSIS Global Defines
163
164 <strong>IO Type Qualifiers</strong> are used
165 \li to specify the access to peripheral variables.
166 \li for automatic generation of peripheral register debug information.
167 */
168 #ifdef __cplusplus
169 #define __I volatile /*!< Defines 'read only' permissions */
170 #else
171 #define __I volatile const /*!< Defines 'read only' permissions */
172 #endif
173 #define __O volatile /*!< Defines 'write only' permissions */
174 #define __IO volatile /*!< Defines 'read / write' permissions */
175
176 /*@} end of group SC000 */
177
178
179
180 /*******************************************************************************
181 * Register Abstraction
182 Core Register contain:
183 - Core Register
184 - Core NVIC Register
185 - Core SCB Register
186 - Core SysTick Register
187 - Core MPU Register
188 ******************************************************************************/
189 /** \defgroup CMSIS_core_register Defines and Type Definitions
190 \brief Type definitions and defines for Cortex-M processor based devices.
191 */
192
193 /** \ingroup CMSIS_core_register
194 \defgroup CMSIS_CORE Status and Control Registers
195 \brief Core Register type definitions.
196 @{
197 */
198
199 /** \brief Union type to access the Application Program Status Register (APSR).
200 */
201 typedef union
202 {
203 struct
204 {
205 #if (__CORTEX_M != 0x04)
206 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
207 #else
208 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
209 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
210 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
211 #endif
212 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
217 } b; /*!< Structure used for bit access */
218 uint32_t w; /*!< Type used for word access */
219 } APSR_Type;
220
221
222 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
223 */
224 typedef union
225 {
226 struct
227 {
228 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
229 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
230 } b; /*!< Structure used for bit access */
231 uint32_t w; /*!< Type used for word access */
232 } IPSR_Type;
233
234
235 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
236 */
237 typedef union
238 {
239 struct
240 {
241 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
242 #if (__CORTEX_M != 0x04)
243 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
244 #else
245 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
247 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
248 #endif
249 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
250 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
251 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
252 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
253 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
254 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
255 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
256 } b; /*!< Structure used for bit access */
257 uint32_t w; /*!< Type used for word access */
258 } xPSR_Type;
259
260
261 /** \brief Union type to access the Control Registers (CONTROL).
262 */
263 typedef union
264 {
265 struct
266 {
267 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
268 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
269 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
270 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
271 } b; /*!< Structure used for bit access */
272 uint32_t w; /*!< Type used for word access */
273 } CONTROL_Type;
274
275 /*@} end of group CMSIS_CORE */
276
277
278 /** \ingroup CMSIS_core_register
279 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
280 \brief Type definitions for the NVIC Registers
281 @{
282 */
283
284 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
285 */
286 typedef struct
287 {
288 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
289 uint32_t RESERVED0[31];
290 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
291 uint32_t RSERVED1[31];
292 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
293 uint32_t RESERVED2[31];
294 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
295 uint32_t RESERVED3[31];
296 uint32_t RESERVED4[64];
297 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
298 } NVIC_Type;
299
300 /*@} end of group CMSIS_NVIC */
301
302
303 /** \ingroup CMSIS_core_register
304 \defgroup CMSIS_SCB System Control Block (SCB)
305 \brief Type definitions for the System Control Block Registers
306 @{
307 */
308
309 /** \brief Structure type to access the System Control Block (SCB).
310 */
311 typedef struct
312 {
313 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
314 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
315 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
316 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
317 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
318 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
319 uint32_t RESERVED0[1];
320 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
321 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
322 uint32_t RESERVED1[154];
323 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
324 } SCB_Type;
325
326 /* SCB CPUID Register Definitions */
327 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
328 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
329
330 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
331 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
332
333 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
334 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
335
336 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
337 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
338
339 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
340 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
341
342 /* SCB Interrupt Control State Register Definitions */
343 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
344 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
345
346 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
347 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
348
349 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
350 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
351
352 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
353 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
354
355 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
356 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
357
358 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
359 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
360
361 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
362 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
363
364 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
365 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
366
367 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
368 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
369
370 /* SCB Interrupt Control State Register Definitions */
371 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
372 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
373
374 /* SCB Application Interrupt and Reset Control Register Definitions */
375 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
376 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
377
378 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
379 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
380
381 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
382 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
383
384 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
385 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
386
387 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
388 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
389
390 /* SCB System Control Register Definitions */
391 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
392 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
393
394 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
395 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
396
397 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
398 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
399
400 /* SCB Configuration Control Register Definitions */
401 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
402 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
403
404 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
405 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
406
407 /* SCB System Handler Control and State Register Definitions */
408 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
409 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
410
411 /* SCB Security Features Register Definitions */
412 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
413 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
414
415 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
416 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
417
418 /*@} end of group CMSIS_SCB */
419
420
421 /** \ingroup CMSIS_core_register
422 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
423 \brief Type definitions for the System Control and ID Register not in the SCB
424 @{
425 */
426
427 /** \brief Structure type to access the System Control and ID Register not in the SCB.
428 */
429 typedef struct
430 {
431 uint32_t RESERVED0[2];
432 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
433 } SCnSCB_Type;
434
435 /* Auxiliary Control Register Definitions */
436 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
437 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
438
439 /*@} end of group CMSIS_SCnotSCB */
440
441
442 /** \ingroup CMSIS_core_register
443 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
444 \brief Type definitions for the System Timer Registers.
445 @{
446 */
447
448 /** \brief Structure type to access the System Timer (SysTick).
449 */
450 typedef struct
451 {
452 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
453 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
454 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
455 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
456 } SysTick_Type;
457
458 /* SysTick Control / Status Register Definitions */
459 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
460 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
461
462 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
463 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
464
465 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
466 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
467
468 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
469 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
470
471 /* SysTick Reload Register Definitions */
472 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
473 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
474
475 /* SysTick Current Register Definitions */
476 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
477 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
478
479 /* SysTick Calibration Register Definitions */
480 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
481 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
482
483 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
484 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
485
486 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
487 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
488
489 /*@} end of group CMSIS_SysTick */
490
491 #if (__MPU_PRESENT == 1)
492 /** \ingroup CMSIS_core_register
493 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
494 \brief Type definitions for the Memory Protection Unit (MPU)
495 @{
496 */
497
498 /** \brief Structure type to access the Memory Protection Unit (MPU).
499 */
500 typedef struct
501 {
502 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
503 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
504 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
505 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
506 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
507 } MPU_Type;
508
509 /* MPU Type Register */
510 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
511 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
512
513 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
514 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
515
516 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
517 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
518
519 /* MPU Control Register */
520 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
521 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
522
523 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
524 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
525
526 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
527 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
528
529 /* MPU Region Number Register */
530 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
531 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
532
533 /* MPU Region Base Address Register */
534 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
535 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
536
537 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
538 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
539
540 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
541 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
542
543 /* MPU Region Attribute and Size Register */
544 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
545 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
546
547 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
548 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
549
550 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
551 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
552
553 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
554 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
555
556 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
557 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
558
559 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
560 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
561
562 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
564
565 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
566 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
567
568 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
569 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
570
571 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
572 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
573
574 /*@} end of group CMSIS_MPU */
575 #endif
576
577
578 /** \ingroup CMSIS_core_register
579 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
580 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
581 are only accessible over DAP and not via processor. Therefore
582 they are not covered by the Cortex-M0 header file.
583 @{
584 */
585 /*@} end of group CMSIS_CoreDebug */
586
587
588 /** \ingroup CMSIS_core_register
589 \defgroup CMSIS_core_base Core Definitions
590 \brief Definitions for base addresses, unions, and structures.
591 @{
592 */
593
594 /* Memory mapping of SC000 Hardware */
595 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
596 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
597 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
598 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
599
600 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
601 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
602 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
603 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
604
605 #if (__MPU_PRESENT == 1)
606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
608 #endif
609
610 /*@} */
611
612
613
614 /*******************************************************************************
615 * Hardware Abstraction Layer
616 Core Function Interface contains:
617 - Core NVIC Functions
618 - Core SysTick Functions
619 - Core Register Access Functions
620 ******************************************************************************/
621 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
622 */
623
624
625
626 /* ########################## NVIC functions #################################### */
627 /** \ingroup CMSIS_Core_FunctionInterface
628 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
629 \brief Functions that manage interrupts and exceptions via the NVIC.
630 @{
631 */
632
633 /* Interrupt Priorities are WORD accessible only under ARMv6M */
634 /* The following MACROS handle generation of the register offset and byte masks */
635 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
636 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
637 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
638
639
640 /** \brief Enable External Interrupt
641
642 The function enables a device-specific interrupt in the NVIC interrupt controller.
643
644 \param [in] IRQn External interrupt number. Value cannot be negative.
645 */
NVIC_EnableIRQ(IRQn_Type IRQn)646 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
647 {
648 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
649 }
650
651
652 /** \brief Disable External Interrupt
653
654 The function disables a device-specific interrupt in the NVIC interrupt controller.
655
656 \param [in] IRQn External interrupt number. Value cannot be negative.
657 */
NVIC_DisableIRQ(IRQn_Type IRQn)658 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
659 {
660 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
661 }
662
663
664 /** \brief Get Pending Interrupt
665
666 The function reads the pending register in the NVIC and returns the pending bit
667 for the specified interrupt.
668
669 \param [in] IRQn Interrupt number.
670
671 \return 0 Interrupt status is not pending.
672 \return 1 Interrupt status is pending.
673 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)674 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
675 {
676 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
677 }
678
679
680 /** \brief Set Pending Interrupt
681
682 The function sets the pending bit of an external interrupt.
683
684 \param [in] IRQn Interrupt number. Value cannot be negative.
685 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)686 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
687 {
688 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
689 }
690
691
692 /** \brief Clear Pending Interrupt
693
694 The function clears the pending bit of an external interrupt.
695
696 \param [in] IRQn External interrupt number. Value cannot be negative.
697 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)698 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
699 {
700 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
701 }
702
703
704 /** \brief Set Interrupt Priority
705
706 The function sets the priority of an interrupt.
707
708 \note The priority cannot be set for every core interrupt.
709
710 \param [in] IRQn Interrupt number.
711 \param [in] priority Priority to set.
712 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)713 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
714 {
715 if(IRQn < 0) {
716 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
717 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
718 else {
719 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
720 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
721 }
722
723
724 /** \brief Get Interrupt Priority
725
726 The function reads the priority of an interrupt. The interrupt
727 number can be positive to specify an external (device specific)
728 interrupt, or negative to specify an internal (core) interrupt.
729
730
731 \param [in] IRQn Interrupt number.
732 \return Interrupt Priority. Value is aligned automatically to the implemented
733 priority bits of the microcontroller.
734 */
NVIC_GetPriority(IRQn_Type IRQn)735 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
736 {
737
738 if(IRQn < 0) {
739 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
740 else {
741 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
742 }
743
744
745 /** \brief System Reset
746
747 The function initiates a system reset request to reset the MCU.
748 */
NVIC_SystemReset(void)749 __STATIC_INLINE void NVIC_SystemReset(void)
750 {
751 __DSB(); /* Ensure all outstanding memory accesses included
752 buffered write are completed before reset */
753 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
754 SCB_AIRCR_SYSRESETREQ_Msk);
755 __DSB(); /* Ensure completion of memory access */
756 while(1); /* wait until reset */
757 }
758
759 /*@} end of CMSIS_Core_NVICFunctions */
760
761
762
763 /* ################################## SysTick function ############################################ */
764 /** \ingroup CMSIS_Core_FunctionInterface
765 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
766 \brief Functions that configure the System.
767 @{
768 */
769
770 #if (__Vendor_SysTickConfig == 0)
771
772 /** \brief System Tick Configuration
773
774 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
775 Counter is in free running mode to generate periodic interrupts.
776
777 \param [in] ticks Number of ticks between two interrupts.
778
779 \return 0 Function succeeded.
780 \return 1 Function failed.
781
782 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
783 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
784 must contain a vendor-specific implementation of this function.
785
786 */
SysTick_Config(uint32_t ticks)787 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
788 {
789 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
790
791 SysTick->LOAD = ticks - 1; /* set reload register */
792 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
793 SysTick->VAL = 0; /* Load the SysTick Counter Value */
794 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
795 SysTick_CTRL_TICKINT_Msk |
796 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
797 return (0); /* Function successful */
798 }
799
800 #endif
801
802 /*@} end of CMSIS_Core_SysTickFunctions */
803
804
805
806
807 #endif /* __CORE_SC000_H_DEPENDANT */
808
809 #endif /* __CMSIS_GENERIC */
810
811 #ifdef __cplusplus
812 }
813 #endif
814