1 /* 2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef NRFX_IRQS_NRF52840_H__ 33 #define NRFX_IRQS_NRF52840_H__ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 40 // POWER_CLOCK_IRQn 41 #define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler 42 43 // RADIO_IRQn 44 45 // UARTE0_UART0_IRQn 46 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) 47 #define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler 48 #else 49 #define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler 50 #define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler 51 #endif 52 53 // SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 54 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) 55 #define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 56 #else 57 #define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 58 #define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 59 #define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 60 #define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 61 #define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 62 #define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 63 #endif 64 65 // SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 66 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) 67 #define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 68 #else 69 #define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 70 #define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 71 #define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 72 #define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 73 #define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 74 #define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 75 #endif 76 77 // NFCT_IRQn 78 #define nrfx_nfct_irq_handler NFCT_IRQHandler 79 80 // GPIOTE_IRQn 81 #define nrfx_gpiote_irq_handler GPIOTE_IRQHandler 82 83 // SAADC_IRQn 84 #define nrfx_saadc_irq_handler SAADC_IRQHandler 85 86 // TIMER0_IRQn 87 #define nrfx_timer_0_irq_handler TIMER0_IRQHandler 88 89 // TIMER1_IRQn 90 #define nrfx_timer_1_irq_handler TIMER1_IRQHandler 91 92 // TIMER2_IRQn 93 #define nrfx_timer_2_irq_handler TIMER2_IRQHandler 94 95 // RTC0_IRQn 96 #define nrfx_rtc_0_irq_handler RTC0_IRQHandler 97 98 // TEMP_IRQn 99 100 // RNG_IRQn 101 #define nrfx_rng_irq_handler RNG_IRQHandler 102 103 // ECB_IRQn 104 105 // CCM_AAR_IRQn 106 107 // WDT_IRQn 108 #define nrfx_wdt_irq_handler WDT_IRQHandler 109 110 // RTC1_IRQn 111 #define nrfx_rtc_1_irq_handler RTC1_IRQHandler 112 113 // QDEC_IRQn 114 #define nrfx_qdec_irq_handler QDEC_IRQHandler 115 116 // COMP_LPCOMP_IRQn 117 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) 118 #define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler 119 #else 120 #define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler 121 #define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler 122 #endif 123 124 // SWI0_EGU0_IRQn 125 #define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler 126 127 // SWI1_EGU1_IRQn 128 #define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler 129 130 // SWI2_EGU2_IRQn 131 #define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler 132 133 // SWI3_EGU3_IRQn 134 #define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler 135 136 // SWI4_EGU4_IRQn 137 #define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler 138 139 // SWI5_EGU5_IRQn 140 #define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler 141 142 // TIMER3_IRQn 143 #define nrfx_timer_3_irq_handler TIMER3_IRQHandler 144 145 // TIMER4_IRQn 146 #define nrfx_timer_4_irq_handler TIMER4_IRQHandler 147 148 // PWM0_IRQn 149 #define nrfx_pwm_0_irq_handler PWM0_IRQHandler 150 151 // PDM_IRQn 152 #define nrfx_pdm_irq_handler PDM_IRQHandler 153 154 // MWU_IRQn 155 156 // PWM1_IRQn 157 #define nrfx_pwm_1_irq_handler PWM1_IRQHandler 158 159 // PWM2_IRQn 160 #define nrfx_pwm_2_irq_handler PWM2_IRQHandler 161 162 // SPIM2_SPIS2_SPI2_IRQn 163 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) 164 #define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler 165 #else 166 #define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler 167 #define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler 168 #define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler 169 #endif 170 171 // RTC2_IRQn 172 #define nrfx_rtc_2_irq_handler RTC2_IRQHandler 173 174 // I2S_IRQn 175 #define nrfx_i2s_irq_handler I2S_IRQHandler 176 177 // FPU_IRQn 178 179 // USBD_IRQn 180 #define nrfx_usbd_irq_handler USBD_IRQHandler 181 182 // UARTE1_IRQn 183 #define nrfx_uarte_1_irq_handler UARTE1_IRQHandler 184 185 // QSPI_IRQn 186 #define nrfx_qspi_irq_handler QSPI_IRQHandler 187 188 // CRYPTOCELL_IRQn 189 190 // PWM3_IRQn 191 #define nrfx_pwm_3_irq_handler PWM3_IRQHandler 192 193 // SPIM3_IRQn 194 #define nrfx_spim_3_irq_handler SPIM3_IRQHandler 195 196 197 #ifdef __cplusplus 198 } 199 #endif 200 201 #endif // NRFX_IRQS_NRF52840_H__ 202