1 /* 2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef NRFX_IRQS_NRF52832_H__ 33 #define NRFX_IRQS_NRF52832_H__ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 40 // POWER_CLOCK_IRQn 41 #define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler 42 43 // RADIO_IRQn 44 45 // UARTE0_IRQn 46 #define nrfx_uarte_0_irq_handler UARTE0_IRQHandler 47 48 // TWIM0_TWIS0_IRQn 49 #if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) 50 #define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_IRQHandler 51 #else 52 #define nrfx_twim_0_irq_handler TWIM0_TWIS0_IRQHandler 53 #define nrfx_twis_0_irq_handler TWIM0_TWIS0_IRQHandler 54 #endif 55 56 // SPIM0_SPIS0_IRQn 57 #if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) 58 #define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_IRQHandler 59 #else 60 #define nrfx_spim_0_irq_handler SPIM0_SPIS0_IRQHandler 61 #define nrfx_spis_0_irq_handler SPIM0_SPIS0_IRQHandler 62 #endif 63 64 // GPIOTE_IRQn 65 #define nrfx_gpiote_irq_handler GPIOTE_IRQHandler 66 67 // SAADC_IRQn 68 #define nrfx_saadc_irq_handler SAADC_IRQHandler 69 70 // TIMER0_IRQn 71 #define nrfx_timer_0_irq_handler TIMER0_IRQHandler 72 73 // TIMER1_IRQn 74 #define nrfx_timer_1_irq_handler TIMER1_IRQHandler 75 76 // TIMER2_IRQn 77 #define nrfx_timer_2_irq_handler TIMER2_IRQHandler 78 79 // RTC0_IRQn 80 #define nrfx_rtc_0_irq_handler RTC0_IRQHandler 81 82 // TEMP_IRQn 83 84 // RNG_IRQn 85 #define nrfx_rng_irq_handler RNG_IRQHandler 86 87 // ECB_IRQn 88 89 // CCM_AAR_IRQn 90 91 // WDT_IRQn 92 #define nrfx_wdt_irq_handler WDT_IRQHandler 93 94 // RTC1_IRQn 95 #define nrfx_rtc_1_irq_handler RTC1_IRQHandler 96 97 // QDEC_IRQn 98 #define nrfx_qdec_irq_handler QDEC_IRQHandler 99 100 // COMP_IRQn 101 #define nrfx_comp_irq_handler COMP_IRQHandler 102 103 // SWI0_EGU0_IRQn 104 #define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler 105 106 // SWI1_EGU1_IRQn 107 #define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler 108 109 // SWI2_IRQn 110 #define nrfx_swi_2_irq_handler SWI2_IRQHandler 111 112 // SWI3_IRQn 113 #define nrfx_swi_3_irq_handler SWI3_IRQHandler 114 115 // SWI4_IRQn 116 #define nrfx_swi_4_irq_handler SWI4_IRQHandler 117 118 // SWI5_IRQn 119 #define nrfx_swi_5_irq_handler SWI5_IRQHandler 120 121 // PWM0_IRQn 122 #define nrfx_pwm_0_irq_handler PWM0_IRQHandler 123 124 // PDM_IRQn 125 #define nrfx_pdm_irq_handler PDM_IRQHandler 126 127 128 #ifdef __cplusplus 129 } 130 #endif 131 132 #endif // NRFX_IRQS_NRF52832_H__ 133