1 /* 2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef NRFX_IRQS_NRF51_H__ 33 #define NRFX_IRQS_NRF51_H__ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 40 // POWER_CLOCK_IRQn 41 #define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler 42 43 // RADIO_IRQn 44 45 // UART0_IRQn 46 #define nrfx_uart_0_irq_handler UART0_IRQHandler 47 48 // SPI0_TWI0_IRQn 49 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) 50 #define nrfx_prs_box_0_irq_handler SPI0_TWI0_IRQHandler 51 #else 52 #define nrfx_spi_0_irq_handler SPI0_TWI0_IRQHandler 53 #define nrfx_twi_0_irq_handler SPI0_TWI0_IRQHandler 54 #endif 55 56 // SPI1_TWI1_IRQn 57 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) 58 #define nrfx_prs_box_1_irq_handler SPI1_TWI1_IRQHandler 59 #else 60 #define nrfx_spi_1_irq_handler SPI1_TWI1_IRQHandler 61 #define nrfx_spis_1_irq_handler SPI1_TWI1_IRQHandler 62 #define nrfx_twi_1_irq_handler SPI1_TWI1_IRQHandler 63 #endif 64 65 // GPIOTE_IRQn 66 #define nrfx_gpiote_irq_handler GPIOTE_IRQHandler 67 68 // ADC_IRQn 69 #define nrfx_adc_irq_handler ADC_IRQHandler 70 71 // TIMER0_IRQn 72 #define nrfx_timer_0_irq_handler TIMER0_IRQHandler 73 74 // TIMER1_IRQn 75 #define nrfx_timer_1_irq_handler TIMER1_IRQHandler 76 77 // TIMER2_IRQn 78 #define nrfx_timer_2_irq_handler TIMER2_IRQHandler 79 80 // RTC0_IRQn 81 #define nrfx_rtc_0_irq_handler RTC0_IRQHandler 82 83 // TEMP_IRQn 84 85 // RNG_IRQn 86 #define nrfx_rng_irq_handler RNG_IRQHandler 87 88 // ECB_IRQn 89 90 // CCM_AAR_IRQn 91 92 // WDT_IRQn 93 #define nrfx_wdt_irq_handler WDT_IRQHandler 94 95 // RTC1_IRQn 96 #define nrfx_rtc_1_irq_handler RTC1_IRQHandler 97 98 // QDEC_IRQn 99 #define nrfx_qdec_irq_handler QDEC_IRQHandler 100 101 // LPCOMP_IRQn 102 #define nrfx_lpcomp_irq_handler LPCOMP_IRQHandler 103 104 // SWI0_IRQn 105 #define nrfx_swi_0_irq_handler SWI0_IRQHandler 106 107 // SWI1_IRQn 108 #define nrfx_swi_1_irq_handler SWI1_IRQHandler 109 110 // SWI2_IRQn 111 #define nrfx_swi_2_irq_handler SWI2_IRQHandler 112 113 // SWI3_IRQn 114 #define nrfx_swi_3_irq_handler SWI3_IRQHandler 115 116 // SWI4_IRQn 117 #define nrfx_swi_4_irq_handler SWI4_IRQHandler 118 119 // SWI5_IRQn 120 #define nrfx_swi_5_irq_handler SWI5_IRQHandler 121 122 123 #ifdef __cplusplus 124 } 125 #endif 126 127 #endif // NRFX_IRQS_NRF51_H__ 128