1/*********************************************************************************** 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 *********************************************************************************** 5 * * 6 * (c) 2014 - 2018 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: [email protected] * 9 * * 10 *********************************************************************************** 11 * * 12 * All rights reserved. * 13 * * 14 * Redistribution and use in source and binary forms, with or * 15 * without modification, are permitted provided that the following * 16 * conditions are met: * 17 * * 18 * - Redistributions of source code must retain the above copyright * 19 * notice, this list of conditions and the following disclaimer. * 20 * * 21 * - Neither the name of SEGGER Microcontroller GmbH * 22 * nor the names of its contributors may be used to endorse or * 23 * promote products derived from this software without specific * 24 * prior written permission. * 25 * * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 30 * DISCLAIMED. * 31 * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 34 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 35 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 36 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 38 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 39 * DAMAGE. * 40 * * 41 ***********************************************************************************/ 42 43/************************************************************************************ 44 * Preprocessor Definitions * 45 * ------------------------ * 46 * NO_FPU_ENABLE * 47 * * 48 * If defined, FPU will not be enabled. * 49 * * 50 * NO_STACK_INIT * 51 * * 52 * If defined, the stack pointer will not be initialised. * 53 * * 54 * NO_SYSTEM_INIT * 55 * * 56 * If defined, the SystemInit() function will not be called. By default * 57 * SystemInit() is called after reset to enable the clocks and memories to * 58 * be initialised prior to any C startup initialisation. * 59 * * 60 * NO_VTOR_CONFIG * 61 * * 62 * If defined, the vector table offset register will not be configured. * 63 * * 64 * MEMORY_INIT * 65 * * 66 * If defined, the MemoryInit() function will be called. By default * 67 * MemoryInit() is called after SystemInit() to enable an external memory * 68 * controller. * 69 * * 70 * STACK_INIT_VAL * 71 * * 72 * If defined, specifies the initial stack pointer value. If undefined, * 73 * the stack pointer will be initialised to point to the end of the * 74 * RAM segment. * 75 * * 76 * VECTORS_IN_RAM * 77 * * 78 * If defined, the exception vectors will be copied from Flash to RAM. * 79 * * 80 ************************************************************************************/ 81 82 .syntax unified 83 84 .global Reset_Handler 85#ifdef INITIALIZE_USER_SECTIONS 86 .global InitializeUserMemorySections 87#endif 88 .extern _vectors 89 .extern nRFInitialize 90 91 .section .init, "ax" 92 .thumb_func 93 94 .equ VTOR_REG, 0xE000ED08 95 .equ FPU_CPACR_REG, 0xE000ED88 96 97#ifndef STACK_INIT_VAL 98#define STACK_INIT_VAL __RAM_segment_end__ 99#endif 100 101Reset_Handler: 102 103 /* Perform prestart tasks. */ 104 ldr r0, =nRFInitialize 105 blx r0 106 107#ifndef NO_STACK_INIT 108 /* Initialise main stack */ 109 ldr r0, =STACK_INIT_VAL 110 ldr r1, =0x7 111 bics r0, r1 112 mov sp, r0 113#endif 114 115#ifndef NO_SYSTEM_INIT 116 /* Initialise system */ 117 ldr r0, =SystemInit 118 blx r0 119#endif 120 121#ifdef MEMORY_INIT 122 ldr r0, =MemoryInit 123 blx r0 124#endif 125 126#ifdef VECTORS_IN_RAM 127 /* Copy exception vectors into RAM */ 128 ldr r0, =__vectors_start__ 129 ldr r1, =__vectors_end__ 130 ldr r2, =__vectors_ram_start__ 1311: 132 cmp r0, r1 133 beq 2f 134 ldr r3, [r0] 135 str r3, [r2] 136 adds r0, r0, #4 137 adds r2, r2, #4 138 b 1b 1392: 140#endif 141 142#ifndef NO_VTOR_CONFIG 143 /* Configure vector table offset register */ 144 ldr r0, =VTOR_REG 145#ifdef VECTORS_IN_RAM 146 ldr r1, =_vectors_ram 147#else 148 ldr r1, =_vectors 149#endif 150 str r1, [r0] 151#endif 152 153#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) 154 /* Enable FPU */ 155 ldr r0, =FPU_CPACR_REG 156 ldr r1, [r0] 157 orr r1, r1, #(0xF << 20) 158 str r1, [r0] 159 dsb 160 isb 161#endif 162 163 /* Jump to program start */ 164 b _start 165 166#ifdef INITIALIZE_USER_SECTIONS 167 .thumb_func 168InitializeUserMemorySections: 169 ldr r0, =__start_nrf_sections 170 ldr r1, =__start_nrf_sections_run 171 ldr r2, =__end_nrf_sections_run 172 cmp r0, r1 173 beq 2f 174 subs r2, r2, r1 175 beq 2f 1761: 177 ldrb r3, [r0] 178 adds r0, r0, #1 179 strb r3, [r1] 180 adds r1, r1, #1 181 subs r2, r2, #1 182 bne 1b 1832: 184 bx lr 185#endif