1*150812a8SEvalZero/*********************************************************************************** 2*150812a8SEvalZero * SEGGER Microcontroller GmbH * 3*150812a8SEvalZero * The Embedded Experts * 4*150812a8SEvalZero *********************************************************************************** 5*150812a8SEvalZero * * 6*150812a8SEvalZero * (c) 2014 - 2018 SEGGER Microcontroller GmbH * 7*150812a8SEvalZero * * 8*150812a8SEvalZero * www.segger.com Support: [email protected] * 9*150812a8SEvalZero * * 10*150812a8SEvalZero *********************************************************************************** 11*150812a8SEvalZero * * 12*150812a8SEvalZero * All rights reserved. * 13*150812a8SEvalZero * * 14*150812a8SEvalZero * Redistribution and use in source and binary forms, with or * 15*150812a8SEvalZero * without modification, are permitted provided that the following * 16*150812a8SEvalZero * conditions are met: * 17*150812a8SEvalZero * * 18*150812a8SEvalZero * - Redistributions of source code must retain the above copyright * 19*150812a8SEvalZero * notice, this list of conditions and the following disclaimer. * 20*150812a8SEvalZero * * 21*150812a8SEvalZero * - Neither the name of SEGGER Microcontroller GmbH * 22*150812a8SEvalZero * nor the names of its contributors may be used to endorse or * 23*150812a8SEvalZero * promote products derived from this software without specific * 24*150812a8SEvalZero * prior written permission. * 25*150812a8SEvalZero * * 26*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 27*150812a8SEvalZero * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 28*150812a8SEvalZero * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 29*150812a8SEvalZero * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 30*150812a8SEvalZero * DISCLAIMED. * 31*150812a8SEvalZero * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * 32*150812a8SEvalZero * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 33*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 34*150812a8SEvalZero * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 35*150812a8SEvalZero * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 36*150812a8SEvalZero * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 37*150812a8SEvalZero * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 38*150812a8SEvalZero * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 39*150812a8SEvalZero * DAMAGE. * 40*150812a8SEvalZero * * 41*150812a8SEvalZero ***********************************************************************************/ 42*150812a8SEvalZero 43*150812a8SEvalZero/************************************************************************************ 44*150812a8SEvalZero * Preprocessor Definitions * 45*150812a8SEvalZero * ------------------------ * 46*150812a8SEvalZero * NO_FPU_ENABLE * 47*150812a8SEvalZero * * 48*150812a8SEvalZero * If defined, FPU will not be enabled. * 49*150812a8SEvalZero * * 50*150812a8SEvalZero * NO_STACK_INIT * 51*150812a8SEvalZero * * 52*150812a8SEvalZero * If defined, the stack pointer will not be initialised. * 53*150812a8SEvalZero * * 54*150812a8SEvalZero * NO_SYSTEM_INIT * 55*150812a8SEvalZero * * 56*150812a8SEvalZero * If defined, the SystemInit() function will not be called. By default * 57*150812a8SEvalZero * SystemInit() is called after reset to enable the clocks and memories to * 58*150812a8SEvalZero * be initialised prior to any C startup initialisation. * 59*150812a8SEvalZero * * 60*150812a8SEvalZero * NO_VTOR_CONFIG * 61*150812a8SEvalZero * * 62*150812a8SEvalZero * If defined, the vector table offset register will not be configured. * 63*150812a8SEvalZero * * 64*150812a8SEvalZero * MEMORY_INIT * 65*150812a8SEvalZero * * 66*150812a8SEvalZero * If defined, the MemoryInit() function will be called. By default * 67*150812a8SEvalZero * MemoryInit() is called after SystemInit() to enable an external memory * 68*150812a8SEvalZero * controller. * 69*150812a8SEvalZero * * 70*150812a8SEvalZero * STACK_INIT_VAL * 71*150812a8SEvalZero * * 72*150812a8SEvalZero * If defined, specifies the initial stack pointer value. If undefined, * 73*150812a8SEvalZero * the stack pointer will be initialised to point to the end of the * 74*150812a8SEvalZero * RAM segment. * 75*150812a8SEvalZero * * 76*150812a8SEvalZero * VECTORS_IN_RAM * 77*150812a8SEvalZero * * 78*150812a8SEvalZero * If defined, the exception vectors will be copied from Flash to RAM. * 79*150812a8SEvalZero * * 80*150812a8SEvalZero ************************************************************************************/ 81*150812a8SEvalZero 82*150812a8SEvalZero .syntax unified 83*150812a8SEvalZero 84*150812a8SEvalZero .global Reset_Handler 85*150812a8SEvalZero#ifdef INITIALIZE_USER_SECTIONS 86*150812a8SEvalZero .global InitializeUserMemorySections 87*150812a8SEvalZero#endif 88*150812a8SEvalZero .extern _vectors 89*150812a8SEvalZero .extern nRFInitialize 90*150812a8SEvalZero 91*150812a8SEvalZero .section .init, "ax" 92*150812a8SEvalZero .thumb_func 93*150812a8SEvalZero 94*150812a8SEvalZero .equ VTOR_REG, 0xE000ED08 95*150812a8SEvalZero .equ FPU_CPACR_REG, 0xE000ED88 96*150812a8SEvalZero 97*150812a8SEvalZero#ifndef STACK_INIT_VAL 98*150812a8SEvalZero#define STACK_INIT_VAL __RAM_segment_end__ 99*150812a8SEvalZero#endif 100*150812a8SEvalZero 101*150812a8SEvalZeroReset_Handler: 102*150812a8SEvalZero 103*150812a8SEvalZero /* Perform prestart tasks. */ 104*150812a8SEvalZero ldr r0, =nRFInitialize 105*150812a8SEvalZero blx r0 106*150812a8SEvalZero 107*150812a8SEvalZero#ifndef NO_STACK_INIT 108*150812a8SEvalZero /* Initialise main stack */ 109*150812a8SEvalZero ldr r0, =STACK_INIT_VAL 110*150812a8SEvalZero ldr r1, =0x7 111*150812a8SEvalZero bics r0, r1 112*150812a8SEvalZero mov sp, r0 113*150812a8SEvalZero#endif 114*150812a8SEvalZero 115*150812a8SEvalZero#ifndef NO_SYSTEM_INIT 116*150812a8SEvalZero /* Initialise system */ 117*150812a8SEvalZero ldr r0, =SystemInit 118*150812a8SEvalZero blx r0 119*150812a8SEvalZero#endif 120*150812a8SEvalZero 121*150812a8SEvalZero#ifdef MEMORY_INIT 122*150812a8SEvalZero ldr r0, =MemoryInit 123*150812a8SEvalZero blx r0 124*150812a8SEvalZero#endif 125*150812a8SEvalZero 126*150812a8SEvalZero#ifdef VECTORS_IN_RAM 127*150812a8SEvalZero /* Copy exception vectors into RAM */ 128*150812a8SEvalZero ldr r0, =__vectors_start__ 129*150812a8SEvalZero ldr r1, =__vectors_end__ 130*150812a8SEvalZero ldr r2, =__vectors_ram_start__ 131*150812a8SEvalZero1: 132*150812a8SEvalZero cmp r0, r1 133*150812a8SEvalZero beq 2f 134*150812a8SEvalZero ldr r3, [r0] 135*150812a8SEvalZero str r3, [r2] 136*150812a8SEvalZero adds r0, r0, #4 137*150812a8SEvalZero adds r2, r2, #4 138*150812a8SEvalZero b 1b 139*150812a8SEvalZero2: 140*150812a8SEvalZero#endif 141*150812a8SEvalZero 142*150812a8SEvalZero#ifndef NO_VTOR_CONFIG 143*150812a8SEvalZero /* Configure vector table offset register */ 144*150812a8SEvalZero ldr r0, =VTOR_REG 145*150812a8SEvalZero#ifdef VECTORS_IN_RAM 146*150812a8SEvalZero ldr r1, =_vectors_ram 147*150812a8SEvalZero#else 148*150812a8SEvalZero ldr r1, =_vectors 149*150812a8SEvalZero#endif 150*150812a8SEvalZero str r1, [r0] 151*150812a8SEvalZero#endif 152*150812a8SEvalZero 153*150812a8SEvalZero#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) 154*150812a8SEvalZero /* Enable FPU */ 155*150812a8SEvalZero ldr r0, =FPU_CPACR_REG 156*150812a8SEvalZero ldr r1, [r0] 157*150812a8SEvalZero orr r1, r1, #(0xF << 20) 158*150812a8SEvalZero str r1, [r0] 159*150812a8SEvalZero dsb 160*150812a8SEvalZero isb 161*150812a8SEvalZero#endif 162*150812a8SEvalZero 163*150812a8SEvalZero /* Jump to program start */ 164*150812a8SEvalZero b _start 165*150812a8SEvalZero 166*150812a8SEvalZero#ifdef INITIALIZE_USER_SECTIONS 167*150812a8SEvalZero .thumb_func 168*150812a8SEvalZeroInitializeUserMemorySections: 169*150812a8SEvalZero ldr r0, =__start_nrf_sections 170*150812a8SEvalZero ldr r1, =__start_nrf_sections_run 171*150812a8SEvalZero ldr r2, =__end_nrf_sections_run 172*150812a8SEvalZero cmp r0, r1 173*150812a8SEvalZero beq 2f 174*150812a8SEvalZero subs r2, r2, r1 175*150812a8SEvalZero beq 2f 176*150812a8SEvalZero1: 177*150812a8SEvalZero ldrb r3, [r0] 178*150812a8SEvalZero adds r0, r0, #1 179*150812a8SEvalZero strb r3, [r1] 180*150812a8SEvalZero adds r1, r1, #1 181*150812a8SEvalZero subs r2, r2, #1 182*150812a8SEvalZero bne 1b 183*150812a8SEvalZero2: 184*150812a8SEvalZero bx lr 185*150812a8SEvalZero#endif