xref: /nrf52832-nimble/nordic/nrfx/mdk/nrf9160_peripherals.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b)
1*150812a8SEvalZero /*
2*150812a8SEvalZero 
3*150812a8SEvalZero Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
4*150812a8SEvalZero 
5*150812a8SEvalZero Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero 
8*150812a8SEvalZero 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero    list of conditions and the following disclaimer.
10*150812a8SEvalZero 
11*150812a8SEvalZero 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero    notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero    documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero 
15*150812a8SEvalZero 3. Neither the name of Nordic Semiconductor ASA nor the names of its
16*150812a8SEvalZero    contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero    software without specific prior written permission.
18*150812a8SEvalZero 
19*150812a8SEvalZero THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
23*150812a8SEvalZero LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero 
31*150812a8SEvalZero */
32*150812a8SEvalZero 
33*150812a8SEvalZero #ifndef _NRF9160_PERIPHERALS_H
34*150812a8SEvalZero #define _NRF9160_PERIPHERALS_H
35*150812a8SEvalZero 
36*150812a8SEvalZero /* UICR */
37*150812a8SEvalZero #define UICR_KEYSLOT_COUNT 128
38*150812a8SEvalZero 
39*150812a8SEvalZero /* Clock Peripheral */
40*150812a8SEvalZero #define CLOCK_PRESENT
41*150812a8SEvalZero #define CLOCK_COUNT 1
42*150812a8SEvalZero 
43*150812a8SEvalZero /* Power Peripheral */
44*150812a8SEvalZero #define POWER_PRESENT
45*150812a8SEvalZero #define POWER_COUNT 1
46*150812a8SEvalZero 
47*150812a8SEvalZero /* Memory Watch Unit */
48*150812a8SEvalZero #define MWU_PRESENT
49*150812a8SEvalZero #define MWU_COUNT 1
50*150812a8SEvalZero 
51*150812a8SEvalZero /* GPIO */
52*150812a8SEvalZero #define GPIO_PRESENT
53*150812a8SEvalZero #define GPIO_COUNT 1
54*150812a8SEvalZero 
55*150812a8SEvalZero #define P0_PIN_NUM 32
56*150812a8SEvalZero 
57*150812a8SEvalZero /* Distributed  Peripheral to Peripheral Interconnect */
58*150812a8SEvalZero #define DPPI_PRESENT
59*150812a8SEvalZero #define DPPI_COUNT 1
60*150812a8SEvalZero 
61*150812a8SEvalZero #define DPPI_CH_NUM 16
62*150812a8SEvalZero #define DPPI_GROUP_NUM 6
63*150812a8SEvalZero 
64*150812a8SEvalZero /* Event Generator Unit */
65*150812a8SEvalZero #define EGU_PRESENT
66*150812a8SEvalZero #define EGU_COUNT 6
67*150812a8SEvalZero 
68*150812a8SEvalZero #define EGU0_CH_NUM 16
69*150812a8SEvalZero #define EGU1_CH_NUM 16
70*150812a8SEvalZero #define EGU2_CH_NUM 16
71*150812a8SEvalZero #define EGU3_CH_NUM 16
72*150812a8SEvalZero #define EGU4_CH_NUM 16
73*150812a8SEvalZero #define EGU5_CH_NUM 16
74*150812a8SEvalZero 
75*150812a8SEvalZero /* Timer/Counter */
76*150812a8SEvalZero #define TIMER_PRESENT
77*150812a8SEvalZero #define TIMER_COUNT 3
78*150812a8SEvalZero 
79*150812a8SEvalZero #define TIMER0_MAX_SIZE 32
80*150812a8SEvalZero #define TIMER1_MAX_SIZE 32
81*150812a8SEvalZero #define TIMER2_MAX_SIZE 32
82*150812a8SEvalZero 
83*150812a8SEvalZero 
84*150812a8SEvalZero #define TIMER0_CC_NUM 6
85*150812a8SEvalZero #define TIMER1_CC_NUM 6
86*150812a8SEvalZero #define TIMER2_CC_NUM 6
87*150812a8SEvalZero 
88*150812a8SEvalZero /* Real Time Counter */
89*150812a8SEvalZero #define RTC_PRESENT
90*150812a8SEvalZero #define RTC_COUNT 2
91*150812a8SEvalZero 
92*150812a8SEvalZero #define RTC0_CC_NUM 4
93*150812a8SEvalZero #define RTC1_CC_NUM 4
94*150812a8SEvalZero 
95*150812a8SEvalZero /* Watchdog Timer */
96*150812a8SEvalZero #define WDT_PRESENT
97*150812a8SEvalZero #define WDT_COUNT 1
98*150812a8SEvalZero 
99*150812a8SEvalZero /* Serial Peripheral Interface Master with DMA */
100*150812a8SEvalZero #define SPIM_PRESENT
101*150812a8SEvalZero #define SPIM_COUNT 4
102*150812a8SEvalZero 
103*150812a8SEvalZero #define SPIM0_MAX_DATARATE  8
104*150812a8SEvalZero #define SPIM1_MAX_DATARATE  8
105*150812a8SEvalZero #define SPIM2_MAX_DATARATE  8
106*150812a8SEvalZero #define SPIM3_MAX_DATARATE  8
107*150812a8SEvalZero 
108*150812a8SEvalZero #define SPIM0_EASYDMA_MAXCNT_SIZE 16
109*150812a8SEvalZero #define SPIM1_EASYDMA_MAXCNT_SIZE 16
110*150812a8SEvalZero #define SPIM2_EASYDMA_MAXCNT_SIZE 16
111*150812a8SEvalZero #define SPIM3_EASYDMA_MAXCNT_SIZE 16
112*150812a8SEvalZero 
113*150812a8SEvalZero /* Serial Peripheral Interface Slave with DMA*/
114*150812a8SEvalZero #define SPIS_PRESENT
115*150812a8SEvalZero #define SPIS_COUNT 4
116*150812a8SEvalZero 
117*150812a8SEvalZero #define SPIS0_EASYDMA_MAXCNT_SIZE 16
118*150812a8SEvalZero #define SPIS1_EASYDMA_MAXCNT_SIZE 16
119*150812a8SEvalZero #define SPIS2_EASYDMA_MAXCNT_SIZE 16
120*150812a8SEvalZero #define SPIS3_EASYDMA_MAXCNT_SIZE 16
121*150812a8SEvalZero 
122*150812a8SEvalZero /* Two Wire Interface Master with DMA */
123*150812a8SEvalZero #define TWIM_PRESENT
124*150812a8SEvalZero #define TWIM_COUNT 4
125*150812a8SEvalZero 
126*150812a8SEvalZero #define TWIM0_EASYDMA_MAXCNT_SIZE 16
127*150812a8SEvalZero #define TWIM1_EASYDMA_MAXCNT_SIZE 16
128*150812a8SEvalZero #define TWIM2_EASYDMA_MAXCNT_SIZE 16
129*150812a8SEvalZero #define TWIM3_EASYDMA_MAXCNT_SIZE 16
130*150812a8SEvalZero 
131*150812a8SEvalZero /* Two Wire Interface Slave with DMA */
132*150812a8SEvalZero #define TWIS_PRESENT
133*150812a8SEvalZero #define TWIS_COUNT 4
134*150812a8SEvalZero 
135*150812a8SEvalZero #define TWIS0_EASYDMA_MAXCNT_SIZE 16
136*150812a8SEvalZero #define TWIS1_EASYDMA_MAXCNT_SIZE 16
137*150812a8SEvalZero #define TWIS2_EASYDMA_MAXCNT_SIZE 16
138*150812a8SEvalZero #define TWIS3_EASYDMA_MAXCNT_SIZE 16
139*150812a8SEvalZero 
140*150812a8SEvalZero /* Universal Asynchronous Receiver-Transmitter with DMA */
141*150812a8SEvalZero #define UARTE_PRESENT
142*150812a8SEvalZero #define UARTE_COUNT 4
143*150812a8SEvalZero 
144*150812a8SEvalZero #define UARTE0_EASYDMA_MAXCNT_SIZE 16
145*150812a8SEvalZero #define UARTE1_EASYDMA_MAXCNT_SIZE 16
146*150812a8SEvalZero #define UARTE2_EASYDMA_MAXCNT_SIZE 16
147*150812a8SEvalZero #define UARTE3_EASYDMA_MAXCNT_SIZE 16
148*150812a8SEvalZero 
149*150812a8SEvalZero 
150*150812a8SEvalZero /* Successive Approximation Analog to Digital Converter */
151*150812a8SEvalZero #define SAADC_PRESENT
152*150812a8SEvalZero #define SAADC_COUNT 1
153*150812a8SEvalZero 
154*150812a8SEvalZero #define SAADC_EASYDMA_MAXCNT_SIZE 15
155*150812a8SEvalZero 
156*150812a8SEvalZero /* GPIO Tasks and Events */
157*150812a8SEvalZero #define GPIOTE_PRESENT
158*150812a8SEvalZero #define GPIOTE_COUNT 2
159*150812a8SEvalZero 
160*150812a8SEvalZero #define GPIOTE_CH_NUM 8
161*150812a8SEvalZero 
162*150812a8SEvalZero #define GPIOTE_FEATURE_SET_PRESENT
163*150812a8SEvalZero #define GPIOTE_FEATURE_CLR_PRESENT
164*150812a8SEvalZero 
165*150812a8SEvalZero /* Pulse Width Modulator */
166*150812a8SEvalZero #define PWM_PRESENT
167*150812a8SEvalZero #define PWM_COUNT 4
168*150812a8SEvalZero 
169*150812a8SEvalZero #define PWM_CH_NUM 4
170*150812a8SEvalZero 
171*150812a8SEvalZero #define PWM_EASYDMA_MAXCNT_SIZE 15
172*150812a8SEvalZero 
173*150812a8SEvalZero /* Pulse Density Modulator */
174*150812a8SEvalZero #define PDM_PRESENT
175*150812a8SEvalZero #define PDM_COUNT 1
176*150812a8SEvalZero 
177*150812a8SEvalZero #define PDM_EASYDMA_MAXCNT_SIZE 15
178*150812a8SEvalZero 
179*150812a8SEvalZero /* Inter-IC Sound Interface */
180*150812a8SEvalZero #define I2S_PRESENT
181*150812a8SEvalZero #define I2S_COUNT 1
182*150812a8SEvalZero 
183*150812a8SEvalZero #define I2S_EASYDMA_MAXCNT_SIZE 14
184*150812a8SEvalZero 
185*150812a8SEvalZero /* Inter Processor Communication */
186*150812a8SEvalZero #define IPC_PRESENT
187*150812a8SEvalZero #define IPC_COUNT 1
188*150812a8SEvalZero 
189*150812a8SEvalZero #define IPC_CH_NUM 8
190*150812a8SEvalZero #define IPC_GPMEM_NUM 4
191*150812a8SEvalZero 
192*150812a8SEvalZero /* FPU */
193*150812a8SEvalZero #define FPU_PRESENT
194*150812a8SEvalZero #define FPU_COUNT 1
195*150812a8SEvalZero 
196*150812a8SEvalZero /* SPU */
197*150812a8SEvalZero #define SPU_PRESENT
198*150812a8SEvalZero #define SPU_COUNT 1
199*150812a8SEvalZero 
200*150812a8SEvalZero /* CRYPTOCELL */
201*150812a8SEvalZero #define CRYPTOCELL_PRESENT
202*150812a8SEvalZero #define CRYPTOCELL_COUNT 1
203*150812a8SEvalZero 
204*150812a8SEvalZero /* KMU */
205*150812a8SEvalZero #define KMU_PRESENT
206*150812a8SEvalZero #define KMU_COUNT 1
207*150812a8SEvalZero 
208*150812a8SEvalZero #define KMU_KEYSLOT_PRESENT
209*150812a8SEvalZero 
210*150812a8SEvalZero /* MAGPIO */
211*150812a8SEvalZero #define MAGPIO_PRESENT
212*150812a8SEvalZero #define MAGPIO_COUNT 1
213*150812a8SEvalZero #define MAGPIO_PIN_NUM 3
214*150812a8SEvalZero 
215*150812a8SEvalZero /* REGULATORS */
216*150812a8SEvalZero #define REGULATORS_PRESENT
217*150812a8SEvalZero #define REGULATORS_COUNT 1
218*150812a8SEvalZero 
219*150812a8SEvalZero 
220*150812a8SEvalZero #endif  // _NRF9160_PERIPHERALS_H
221