xref: /nrf52832-nimble/nordic/nrfx/mdk/nrf9160_bitfields.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b) 
1 /*
2 
3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
4 
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7 
8 1. Redistributions of source code must retain the above copyright notice, this
9    list of conditions and the following disclaimer.
10 
11 2. Redistributions in binary form must reproduce the above copyright
12    notice, this list of conditions and the following disclaimer in the
13    documentation and/or other materials provided with the distribution.
14 
15 3. Neither the name of Nordic Semiconductor ASA nor the names of its
16    contributors may be used to endorse or promote products derived from this
17    software without specific prior written permission.
18 
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE.
30 
31 */
32 
33 #ifndef __NRF9160_BITS_H
34 #define __NRF9160_BITS_H
35 
36 /*lint ++flb "Enter library region" */
37 
38 /* Peripheral: CLOCK */
39 /* Description: Clock management 0 */
40 
41 /* Register: CLOCK_TASKS_HFCLKSTART */
42 /* Description: Start HFCLK crystal oscillator */
43 
44 /* Bit 0 : Start HFCLK crystal oscillator */
45 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
46 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
47 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
48 
49 /* Register: CLOCK_TASKS_HFCLKSTOP */
50 /* Description: Stop HFCLK crystal oscillator */
51 
52 /* Bit 0 : Stop HFCLK crystal oscillator */
53 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
54 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
55 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
56 
57 /* Register: CLOCK_TASKS_LFCLKSTART */
58 /* Description: Start LFCLK source */
59 
60 /* Bit 0 : Start LFCLK source */
61 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
62 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
63 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
64 
65 /* Register: CLOCK_TASKS_LFCLKSTOP */
66 /* Description: Stop LFCLK source */
67 
68 /* Bit 0 : Stop LFCLK source */
69 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
70 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
71 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
72 
73 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
74 /* Description: Subscribe configuration for task HFCLKSTART */
75 
76 /* Bit 31 :   */
77 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
78 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
79 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
80 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
81 
82 /* Bits 3..0 : Channel that task HFCLKSTART will subscribe to */
83 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
84 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
85 
86 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
87 /* Description: Subscribe configuration for task HFCLKSTOP */
88 
89 /* Bit 31 :   */
90 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
91 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
92 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
93 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
94 
95 /* Bits 3..0 : Channel that task HFCLKSTOP will subscribe to */
96 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
97 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
98 
99 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
100 /* Description: Subscribe configuration for task LFCLKSTART */
101 
102 /* Bit 31 :   */
103 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
104 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
105 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
106 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
107 
108 /* Bits 3..0 : Channel that task LFCLKSTART will subscribe to */
109 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
110 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
111 
112 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
113 /* Description: Subscribe configuration for task LFCLKSTOP */
114 
115 /* Bit 31 :   */
116 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
117 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
118 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
119 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
120 
121 /* Bits 3..0 : Channel that task LFCLKSTOP will subscribe to */
122 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
123 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
124 
125 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
126 /* Description: HFCLK oscillator started */
127 
128 /* Bit 0 : HFCLK oscillator started */
129 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
130 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
131 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
132 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
133 
134 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
135 /* Description: LFCLK started */
136 
137 /* Bit 0 : LFCLK started */
138 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
139 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
140 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
141 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
142 
143 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */
144 /* Description: Publish configuration for event HFCLKSTARTED */
145 
146 /* Bit 31 :   */
147 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
148 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
149 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
150 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
151 
152 /* Bits 3..0 : Channel that event HFCLKSTARTED will publish to. */
153 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
154 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
155 
156 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */
157 /* Description: Publish configuration for event LFCLKSTARTED */
158 
159 /* Bit 31 :   */
160 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
161 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
162 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
163 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
164 
165 /* Bits 3..0 : Channel that event LFCLKSTARTED will publish to. */
166 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
167 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
168 
169 /* Register: CLOCK_INTEN */
170 /* Description: Enable or disable interrupt */
171 
172 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
173 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
174 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
175 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
176 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
177 
178 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
179 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
180 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
181 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
182 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
183 
184 /* Register: CLOCK_INTENSET */
185 /* Description: Enable interrupt */
186 
187 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
188 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
189 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
190 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
191 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
192 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
193 
194 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
195 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
196 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
197 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
198 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
199 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
200 
201 /* Register: CLOCK_INTENCLR */
202 /* Description: Disable interrupt */
203 
204 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
205 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
206 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
207 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
208 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
209 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
210 
211 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
212 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
213 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
214 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
215 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
216 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
217 
218 /* Register: CLOCK_INTPEND */
219 /* Description: Pending interrupts */
220 
221 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
222 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
223 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
224 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
225 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
226 
227 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
228 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
229 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
230 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
231 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
232 
233 /* Register: CLOCK_HFCLKRUN */
234 /* Description: Status indicating that HFCLKSTART task has been triggered */
235 
236 /* Bit 0 : HFCLKSTART task triggered or not */
237 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
238 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
239 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
240 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
241 
242 /* Register: CLOCK_HFCLKSTAT */
243 /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) */
244 
245 /* Bit 16 : HFCLK state */
246 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
247 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
248 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */
249 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */
250 
251 /* Bit 0 : Active clock source */
252 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
253 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
254 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */
255 
256 /* Register: CLOCK_LFCLKRUN */
257 /* Description: Status indicating that LFCLKSTART task has been triggered */
258 
259 /* Bit 0 : LFCLKSTART task triggered or not */
260 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
261 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
262 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
263 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
264 
265 /* Register: CLOCK_LFCLKSTAT */
266 /* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) */
267 
268 /* Bit 16 : LFCLK state */
269 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
270 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
271 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */
272 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */
273 
274 /* Bits 1..0 : Active clock source */
275 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
276 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
277 #define CLOCK_LFCLKSTAT_SRC_RFU (0UL) /*!< Reserved for future use */
278 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
279 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
280 
281 /* Register: CLOCK_LFCLKSRCCOPY */
282 /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */
283 
284 /* Bits 1..0 : Clock source */
285 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
286 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
287 #define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL) /*!< Reserved for future use */
288 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
289 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
290 
291 /* Register: CLOCK_LFCLKSRC */
292 /* Description: Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. */
293 
294 /* Bits 1..0 : Clock source */
295 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
296 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
297 #define CLOCK_LFCLKSRC_SRC_RFU (0UL) /*!< Reserved for future use (equals selecting LFRC) */
298 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
299 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
300 
301 
302 /* Peripheral: CRYPTOCELL */
303 /* Description: ARM TrustZone CryptoCell register interface */
304 
305 /* Register: CRYPTOCELL_ENABLE */
306 /* Description: Enable CRYPTOCELL subsystem */
307 
308 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
309 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
310 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
311 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
312 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */
313 
314 
315 /* Peripheral: CTRLAPPERI */
316 /* Description: Control access port */
317 
318 /* Register: CTRLAPPERI_MAILBOX_RXDATA */
319 /* Description: Data sent from the debugger to the CPU */
320 
321 /* Bits 31..0 : Data received from debugger */
322 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */
323 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */
324 
325 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */
326 /* Description: Status to indicate if data sent from the debugger to the CPU has been read */
327 
328 /* Bit 0 : Status of data in register RXDATA */
329 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */
330 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */
331 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */
332 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */
333 
334 /* Register: CTRLAPPERI_MAILBOX_TXDATA */
335 /* Description: Data sent from the CPU to the debugger */
336 
337 /* Bits 31..0 : Data sent to debugger */
338 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */
339 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */
340 
341 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */
342 /* Description: Status to indicate if data sent from the CPU to the debugger status has been read */
343 
344 /* Bit 0 : Status of data in register TXDATA */
345 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */
346 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */
347 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */
348 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */
349 
350 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */
351 /* Description: Lock ERASEALL mechanism */
352 
353 /* Bit 0 : Enable or disable the ERASEALL mechanism */
354 #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos (0UL) /*!< Position of ERASEPROTECTLOCK field. */
355 #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Pos) /*!< Bit mask of ERASEPROTECTLOCK field. */
356 #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Unlocked (0UL) /*!< ERASEALL can be issued */
357 #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked (1UL) /*!< ERASEALL is locked */
358 
359 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */
360 /* Description: Unlock ERASEPROTECT and perform ERASEALL */
361 
362 /* Bits 31..0 : Initiate secure erase even though ERASEPROTECT is enabled if KEY fields match */
363 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */
364 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */
365 
366 
367 /* Peripheral: DPPIC */
368 /* Description: Distributed Programmable Peripheral Interconnect Controller 0 */
369 
370 /* Register: DPPIC_TASKS_CHG_EN */
371 /* Description: Description cluster: Enable channel group n */
372 
373 /* Bit 0 : Enable channel group n */
374 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
375 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
376 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
377 
378 /* Register: DPPIC_TASKS_CHG_DIS */
379 /* Description: Description cluster: Disable channel group n */
380 
381 /* Bit 0 : Disable channel group n */
382 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
383 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
384 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
385 
386 /* Register: DPPIC_SUBSCRIBE_CHG_EN */
387 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
388 
389 /* Bit 31 :   */
390 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
391 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
392 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
393 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
394 
395 /* Bits 3..0 : Channel that task CHG[n].EN will subscribe to */
396 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
397 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
398 
399 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */
400 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
401 
402 /* Bit 31 :   */
403 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
404 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
405 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
406 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
407 
408 /* Bits 3..0 : Channel that task CHG[n].DIS will subscribe to */
409 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
410 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
411 
412 /* Register: DPPIC_CHEN */
413 /* Description: Channel enable register */
414 
415 /* Bit 15 : Enable or disable channel 15 */
416 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
417 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
418 #define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
419 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
420 
421 /* Bit 14 : Enable or disable channel 14 */
422 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
423 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
424 #define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
425 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
426 
427 /* Bit 13 : Enable or disable channel 13 */
428 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
429 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
430 #define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
431 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
432 
433 /* Bit 12 : Enable or disable channel 12 */
434 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
435 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
436 #define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
437 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
438 
439 /* Bit 11 : Enable or disable channel 11 */
440 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
441 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
442 #define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
443 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
444 
445 /* Bit 10 : Enable or disable channel 10 */
446 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
447 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
448 #define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
449 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
450 
451 /* Bit 9 : Enable or disable channel 9 */
452 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
453 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
454 #define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
455 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
456 
457 /* Bit 8 : Enable or disable channel 8 */
458 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
459 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
460 #define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
461 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
462 
463 /* Bit 7 : Enable or disable channel 7 */
464 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
465 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
466 #define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
467 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
468 
469 /* Bit 6 : Enable or disable channel 6 */
470 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
471 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
472 #define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
473 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
474 
475 /* Bit 5 : Enable or disable channel 5 */
476 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
477 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
478 #define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
479 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
480 
481 /* Bit 4 : Enable or disable channel 4 */
482 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
483 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
484 #define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
485 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
486 
487 /* Bit 3 : Enable or disable channel 3 */
488 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
489 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
490 #define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
491 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
492 
493 /* Bit 2 : Enable or disable channel 2 */
494 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
495 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
496 #define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
497 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
498 
499 /* Bit 1 : Enable or disable channel 1 */
500 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
501 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
502 #define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
503 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
504 
505 /* Bit 0 : Enable or disable channel 0 */
506 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
507 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
508 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
509 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
510 
511 /* Register: DPPIC_CHENSET */
512 /* Description: Channel enable set register */
513 
514 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
515 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
516 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
517 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
518 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
519 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
520 
521 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
522 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
523 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
524 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
525 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
526 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
527 
528 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
529 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
530 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
531 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
532 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
533 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
534 
535 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
536 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
537 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
538 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
539 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
540 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
541 
542 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
543 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
544 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
545 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
546 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
547 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
548 
549 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
550 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
551 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
552 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
553 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
554 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
555 
556 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
557 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
558 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
559 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
560 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
561 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
562 
563 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
564 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
565 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
566 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
567 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
568 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
569 
570 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
571 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
572 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
573 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
574 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
575 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
576 
577 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
578 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
579 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
580 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
581 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
582 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
583 
584 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
585 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
586 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
587 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
588 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
589 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
590 
591 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
592 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
593 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
594 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
595 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
596 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
597 
598 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
599 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
600 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
601 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
602 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
603 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
604 
605 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
606 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
607 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
608 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
609 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
610 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
611 
612 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
613 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
614 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
615 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
616 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
617 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
618 
619 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
620 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
621 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
622 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
623 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
624 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
625 
626 /* Register: DPPIC_CHENCLR */
627 /* Description: Channel enable clear register */
628 
629 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
630 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
631 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
632 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
633 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
634 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
635 
636 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
637 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
638 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
639 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
640 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
641 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
642 
643 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
644 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
645 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
646 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
647 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
648 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
649 
650 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
651 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
652 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
653 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
654 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
655 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
656 
657 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
658 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
659 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
660 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
661 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
662 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
663 
664 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
665 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
666 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
667 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
668 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
669 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
670 
671 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
672 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
673 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
674 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
675 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
676 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
677 
678 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
679 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
680 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
681 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
682 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
683 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
684 
685 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
686 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
687 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
688 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
689 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
690 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
691 
692 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
693 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
694 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
695 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
696 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
697 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
698 
699 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
700 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
701 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
702 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
703 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
704 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
705 
706 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
707 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
708 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
709 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
710 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
711 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
712 
713 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
714 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
715 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
716 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
717 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
718 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
719 
720 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
721 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
722 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
723 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
724 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
725 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
726 
727 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
728 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
729 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
730 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
731 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
732 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
733 
734 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
735 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
736 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
737 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
738 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
739 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
740 
741 /* Register: DPPIC_CHG */
742 /* Description: Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. */
743 
744 /* Bit 15 : Include or exclude channel 15 */
745 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
746 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
747 #define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */
748 #define DPPIC_CHG_CH15_Included (1UL) /*!< Include */
749 
750 /* Bit 14 : Include or exclude channel 14 */
751 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
752 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
753 #define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */
754 #define DPPIC_CHG_CH14_Included (1UL) /*!< Include */
755 
756 /* Bit 13 : Include or exclude channel 13 */
757 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
758 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
759 #define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */
760 #define DPPIC_CHG_CH13_Included (1UL) /*!< Include */
761 
762 /* Bit 12 : Include or exclude channel 12 */
763 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
764 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
765 #define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */
766 #define DPPIC_CHG_CH12_Included (1UL) /*!< Include */
767 
768 /* Bit 11 : Include or exclude channel 11 */
769 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
770 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
771 #define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */
772 #define DPPIC_CHG_CH11_Included (1UL) /*!< Include */
773 
774 /* Bit 10 : Include or exclude channel 10 */
775 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
776 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
777 #define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */
778 #define DPPIC_CHG_CH10_Included (1UL) /*!< Include */
779 
780 /* Bit 9 : Include or exclude channel 9 */
781 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
782 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
783 #define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */
784 #define DPPIC_CHG_CH9_Included (1UL) /*!< Include */
785 
786 /* Bit 8 : Include or exclude channel 8 */
787 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
788 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
789 #define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */
790 #define DPPIC_CHG_CH8_Included (1UL) /*!< Include */
791 
792 /* Bit 7 : Include or exclude channel 7 */
793 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
794 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
795 #define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */
796 #define DPPIC_CHG_CH7_Included (1UL) /*!< Include */
797 
798 /* Bit 6 : Include or exclude channel 6 */
799 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
800 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
801 #define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */
802 #define DPPIC_CHG_CH6_Included (1UL) /*!< Include */
803 
804 /* Bit 5 : Include or exclude channel 5 */
805 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
806 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
807 #define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */
808 #define DPPIC_CHG_CH5_Included (1UL) /*!< Include */
809 
810 /* Bit 4 : Include or exclude channel 4 */
811 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
812 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
813 #define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */
814 #define DPPIC_CHG_CH4_Included (1UL) /*!< Include */
815 
816 /* Bit 3 : Include or exclude channel 3 */
817 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
818 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
819 #define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */
820 #define DPPIC_CHG_CH3_Included (1UL) /*!< Include */
821 
822 /* Bit 2 : Include or exclude channel 2 */
823 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
824 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
825 #define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */
826 #define DPPIC_CHG_CH2_Included (1UL) /*!< Include */
827 
828 /* Bit 1 : Include or exclude channel 1 */
829 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
830 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
831 #define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */
832 #define DPPIC_CHG_CH1_Included (1UL) /*!< Include */
833 
834 /* Bit 0 : Include or exclude channel 0 */
835 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
836 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
837 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */
838 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
839 
840 
841 /* Peripheral: EGU */
842 /* Description: Event Generator Unit 0 */
843 
844 /* Register: EGU_TASKS_TRIGGER */
845 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
846 
847 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
848 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
849 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
850 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
851 
852 /* Register: EGU_SUBSCRIBE_TRIGGER */
853 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
854 
855 /* Bit 31 :   */
856 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
857 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
858 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
859 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
860 
861 /* Bits 3..0 : Channel that task TRIGGER[n] will subscribe to */
862 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
863 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
864 
865 /* Register: EGU_EVENTS_TRIGGERED */
866 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
867 
868 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
869 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
870 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
871 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
872 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
873 
874 /* Register: EGU_PUBLISH_TRIGGERED */
875 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */
876 
877 /* Bit 31 :   */
878 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
879 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
880 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
881 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
882 
883 /* Bits 3..0 : Channel that event TRIGGERED[n] will publish to. */
884 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
885 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
886 
887 /* Register: EGU_INTEN */
888 /* Description: Enable or disable interrupt */
889 
890 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
891 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
892 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
893 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
894 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
895 
896 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
897 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
898 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
899 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
900 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
901 
902 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
903 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
904 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
905 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
906 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
907 
908 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
909 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
910 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
911 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
912 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
913 
914 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
915 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
916 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
917 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
918 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
919 
920 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
921 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
922 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
923 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
924 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
925 
926 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
927 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
928 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
929 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
930 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
931 
932 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
933 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
934 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
935 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
936 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
937 
938 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
939 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
940 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
941 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
942 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
943 
944 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
945 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
946 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
947 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
948 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
949 
950 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
951 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
952 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
953 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
954 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
955 
956 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
957 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
958 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
959 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
960 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
961 
962 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
963 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
964 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
965 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
966 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
967 
968 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
969 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
970 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
971 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
972 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
973 
974 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
975 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
976 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
977 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
978 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
979 
980 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
981 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
982 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
983 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
984 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
985 
986 /* Register: EGU_INTENSET */
987 /* Description: Enable interrupt */
988 
989 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
990 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
991 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
992 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
993 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
994 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
995 
996 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
997 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
998 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
999 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1000 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1001 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1002 
1003 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1004 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1005 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1006 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1007 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1008 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1009 
1010 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1011 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1012 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1013 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1014 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1015 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1016 
1017 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1018 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1019 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1020 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1021 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1022 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1023 
1024 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1025 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1026 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1027 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1028 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1029 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1030 
1031 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1032 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1033 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1034 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1035 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1036 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1037 
1038 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1039 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1040 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1041 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1042 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1043 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1044 
1045 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1046 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1047 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1048 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1049 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1050 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1051 
1052 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1053 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1054 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1055 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1056 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1057 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1058 
1059 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1060 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1061 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1062 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1063 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1064 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1065 
1066 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1067 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1068 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1069 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1070 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1071 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1072 
1073 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1074 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1075 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1076 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1077 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1078 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1079 
1080 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1081 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1082 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1083 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1084 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1085 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1086 
1087 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1088 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1089 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1090 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1091 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1092 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1093 
1094 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1095 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1096 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1097 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1098 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1099 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1100 
1101 /* Register: EGU_INTENCLR */
1102 /* Description: Disable interrupt */
1103 
1104 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1105 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1106 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1107 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1108 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1109 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1110 
1111 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1112 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1113 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1114 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1115 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1116 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1117 
1118 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1119 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1120 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1121 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1122 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1123 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1124 
1125 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1126 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1127 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1128 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1129 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1130 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1131 
1132 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1133 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1134 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1135 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1136 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1137 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1138 
1139 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1140 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1141 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1142 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1143 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1144 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1145 
1146 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1147 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1148 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1149 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1150 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1151 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1152 
1153 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1154 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1155 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1156 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1157 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1158 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1159 
1160 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1161 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1162 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1163 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1164 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1165 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1166 
1167 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1168 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1169 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1170 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1171 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1172 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1173 
1174 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1175 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1176 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1177 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1178 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1179 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1180 
1181 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1182 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1183 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1184 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1185 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1186 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1187 
1188 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1189 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1190 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1191 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1192 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1193 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1194 
1195 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1196 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1197 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1198 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1199 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1200 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1201 
1202 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1203 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1204 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1205 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1206 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1207 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1208 
1209 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1210 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1211 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1212 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1213 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1214 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1215 
1216 
1217 /* Peripheral: FICR */
1218 /* Description: Factory Information Configuration Registers */
1219 
1220 /* Register: FICR_INFO_DEVICEID */
1221 /* Description: Description collection: Device identifier */
1222 
1223 /* Bits 31..0 : 64 bit unique device identifier */
1224 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1225 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1226 
1227 /* Register: FICR_INFO_PART */
1228 /* Description: Part code */
1229 
1230 /* Bits 31..0 : Part code */
1231 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1232 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1233 #define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */
1234 
1235 /* Register: FICR_INFO_VARIANT */
1236 /* Description: Part Variant, Hardware version and Production configuration */
1237 
1238 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
1239 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1240 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1241 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
1242 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1243 
1244 /* Register: FICR_INFO_PACKAGE */
1245 /* Description: Package option */
1246 
1247 /* Bits 31..0 : Package option */
1248 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1249 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1250 #define FICR_INFO_PACKAGE_PACKAGE_CC (0x2000UL) /*!< CCxx - 236 ball wlCSP */
1251 
1252 /* Register: FICR_INFO_RAM */
1253 /* Description: RAM variant */
1254 
1255 /* Bits 31..0 : RAM variant */
1256 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1257 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1258 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256  kByte RAM */
1259 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1260 
1261 /* Register: FICR_INFO_FLASH */
1262 /* Description: Flash variant */
1263 
1264 /* Bits 31..0 : Flash variant */
1265 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1266 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1267 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
1268 
1269 /* Register: FICR_INFO_CODEPAGESIZE */
1270 /* Description: Code memory page size */
1271 
1272 /* Bits 31..0 : Code memory page size */
1273 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1274 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1275 
1276 /* Register: FICR_INFO_CODESIZE */
1277 /* Description: Code memory size */
1278 
1279 /* Bits 31..0 : Code memory size in number of pages */
1280 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1281 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1282 
1283 /* Register: FICR_INFO_DEVICETYPE */
1284 /* Description: Device type */
1285 
1286 /* Bits 31..0 : Device type */
1287 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */
1288 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */
1289 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */
1290 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */
1291 
1292 /* Register: FICR_TRIMCNF_ADDR */
1293 /* Description: Description cluster: Address */
1294 
1295 /* Bits 31..0 : Address */
1296 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */
1297 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */
1298 
1299 /* Register: FICR_TRIMCNF_DATA */
1300 /* Description: Description cluster: Data */
1301 
1302 /* Bits 31..0 : Data */
1303 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */
1304 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */
1305 
1306 /* Register: FICR_TRNG90B_BYTES */
1307 /* Description: Amount of bytes for the required entropy bits */
1308 
1309 /* Bits 31..0 : Amount of bytes for the required entropy bits */
1310 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */
1311 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */
1312 
1313 /* Register: FICR_TRNG90B_RCCUTOFF */
1314 /* Description: Repetition counter cutoff */
1315 
1316 /* Bits 31..0 : Repetition counter cutoff */
1317 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */
1318 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */
1319 
1320 /* Register: FICR_TRNG90B_APCUTOFF */
1321 /* Description: Adaptive proportion cutoff */
1322 
1323 /* Bits 31..0 : Adaptive proportion cutoff */
1324 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */
1325 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */
1326 
1327 /* Register: FICR_TRNG90B_STARTUP */
1328 /* Description: Amount of bytes for the startup tests */
1329 
1330 /* Bits 31..0 : Amount of bytes for the startup tests */
1331 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */
1332 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */
1333 
1334 /* Register: FICR_TRNG90B_ROSC1 */
1335 /* Description: Sample count for ring oscillator 1 */
1336 
1337 /* Bits 31..0 : Sample count for ring oscillator 1 */
1338 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */
1339 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */
1340 
1341 /* Register: FICR_TRNG90B_ROSC2 */
1342 /* Description: Sample count for ring oscillator 2 */
1343 
1344 /* Bits 31..0 : Sample count for ring oscillator 2 */
1345 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */
1346 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */
1347 
1348 /* Register: FICR_TRNG90B_ROSC3 */
1349 /* Description: Sample count for ring oscillator 3 */
1350 
1351 /* Bits 31..0 : Sample count for ring oscillator 3 */
1352 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */
1353 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */
1354 
1355 /* Register: FICR_TRNG90B_ROSC4 */
1356 /* Description: Sample count for ring oscillator 4 */
1357 
1358 /* Bits 31..0 : Sample count for ring oscillator 4 */
1359 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */
1360 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */
1361 
1362 
1363 /* Peripheral: GPIOTE */
1364 /* Description: GPIO Tasks and Events 0 */
1365 
1366 /* Register: GPIOTE_TASKS_OUT */
1367 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1368 
1369 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1370 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
1371 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
1372 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1373 
1374 /* Register: GPIOTE_TASKS_SET */
1375 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1376 
1377 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1378 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
1379 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
1380 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1381 
1382 /* Register: GPIOTE_TASKS_CLR */
1383 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1384 
1385 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1386 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
1387 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
1388 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1389 
1390 /* Register: GPIOTE_SUBSCRIBE_OUT */
1391 /* Description: Description collection: Subscribe configuration for task OUT[n] */
1392 
1393 /* Bit 31 :   */
1394 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */
1395 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */
1396 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */
1397 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
1398 
1399 /* Bits 3..0 : Channel that task OUT[n] will subscribe to */
1400 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1401 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1402 
1403 /* Register: GPIOTE_SUBSCRIBE_SET */
1404 /* Description: Description collection: Subscribe configuration for task SET[n] */
1405 
1406 /* Bit 31 :   */
1407 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */
1408 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */
1409 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */
1410 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
1411 
1412 /* Bits 3..0 : Channel that task SET[n] will subscribe to */
1413 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1414 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1415 
1416 /* Register: GPIOTE_SUBSCRIBE_CLR */
1417 /* Description: Description collection: Subscribe configuration for task CLR[n] */
1418 
1419 /* Bit 31 :   */
1420 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */
1421 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */
1422 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */
1423 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
1424 
1425 /* Bits 3..0 : Channel that task CLR[n] will subscribe to */
1426 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1427 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1428 
1429 /* Register: GPIOTE_EVENTS_IN */
1430 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
1431 
1432 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
1433 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
1434 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
1435 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
1436 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1437 
1438 /* Register: GPIOTE_EVENTS_PORT */
1439 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1440 
1441 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1442 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
1443 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
1444 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
1445 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1446 
1447 /* Register: GPIOTE_PUBLISH_IN */
1448 /* Description: Description collection: Publish configuration for event IN[n] */
1449 
1450 /* Bit 31 :   */
1451 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */
1452 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */
1453 #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */
1454 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
1455 
1456 /* Bits 3..0 : Channel that event IN[n] will publish to. */
1457 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1458 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1459 
1460 /* Register: GPIOTE_PUBLISH_PORT */
1461 /* Description: Publish configuration for event PORT */
1462 
1463 /* Bit 31 :   */
1464 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */
1465 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */
1466 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */
1467 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
1468 
1469 /* Bits 3..0 : Channel that event PORT will publish to. */
1470 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1471 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1472 
1473 /* Register: GPIOTE_INTENSET */
1474 /* Description: Enable interrupt */
1475 
1476 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1477 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
1478 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
1479 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1480 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1481 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1482 
1483 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1484 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
1485 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
1486 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1487 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1488 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1489 
1490 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1491 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
1492 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
1493 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1494 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1495 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1496 
1497 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1498 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
1499 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
1500 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1501 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1502 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1503 
1504 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1505 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
1506 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
1507 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1508 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1509 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1510 
1511 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1512 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
1513 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
1514 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1515 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1516 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1517 
1518 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1519 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1520 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
1521 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1522 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1523 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1524 
1525 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1526 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
1527 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
1528 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1529 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1530 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1531 
1532 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
1533 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
1534 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
1535 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1536 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1537 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
1538 
1539 /* Register: GPIOTE_INTENCLR */
1540 /* Description: Disable interrupt */
1541 
1542 /* Bit 31 : Write '1' to disable interrupt for event PORT */
1543 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
1544 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
1545 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1546 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1547 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1548 
1549 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
1550 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
1551 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
1552 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1553 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1554 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1555 
1556 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
1557 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
1558 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
1559 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1560 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1561 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1562 
1563 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
1564 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
1565 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
1566 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1567 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1568 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1569 
1570 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
1571 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
1572 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
1573 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1574 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1575 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1576 
1577 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
1578 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
1579 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
1580 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1581 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1582 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1583 
1584 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1585 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
1586 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
1587 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1588 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1589 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1590 
1591 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
1592 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
1593 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
1594 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1595 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1596 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1597 
1598 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
1599 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
1600 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
1601 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1602 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1603 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
1604 
1605 /* Register: GPIOTE_CONFIG */
1606 /* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
1607 
1608 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
1609 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
1610 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
1611 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
1612 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
1613 
1614 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
1615 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
1616 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
1617 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
1618 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
1619 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
1620 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
1621 
1622 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
1623 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
1624 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
1625 
1626 /* Bits 1..0 : Mode */
1627 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
1628 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
1629 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
1630 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
1631 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
1632 
1633 
1634 /* Peripheral: I2S */
1635 /* Description: Inter-IC Sound 0 */
1636 
1637 /* Register: I2S_TASKS_START */
1638 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
1639 
1640 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
1641 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
1642 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
1643 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
1644 
1645 /* Register: I2S_TASKS_STOP */
1646 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
1647 
1648 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */
1649 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
1650 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
1651 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
1652 
1653 /* Register: I2S_SUBSCRIBE_START */
1654 /* Description: Subscribe configuration for task START */
1655 
1656 /* Bit 31 :   */
1657 #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
1658 #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
1659 #define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
1660 #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
1661 
1662 /* Bits 3..0 : Channel that task START will subscribe to */
1663 #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1664 #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1665 
1666 /* Register: I2S_SUBSCRIBE_STOP */
1667 /* Description: Subscribe configuration for task STOP */
1668 
1669 /* Bit 31 :   */
1670 #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
1671 #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
1672 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
1673 #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
1674 
1675 /* Bits 3..0 : Channel that task STOP will subscribe to */
1676 #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1677 #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1678 
1679 /* Register: I2S_EVENTS_RXPTRUPD */
1680 /* Description: The RXD.PTR register has been copied to internal double-buffers.
1681       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
1682 
1683 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
1684       When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */
1685 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */
1686 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */
1687 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
1688 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
1689 
1690 /* Register: I2S_EVENTS_STOPPED */
1691 /* Description: I2S transfer stopped. */
1692 
1693 /* Bit 0 : I2S transfer stopped. */
1694 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
1695 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
1696 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
1697 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
1698 
1699 /* Register: I2S_EVENTS_TXPTRUPD */
1700 /* Description: The TDX.PTR register has been copied to internal double-buffers.
1701       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
1702 
1703 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
1704       When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
1705 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */
1706 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */
1707 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */
1708 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
1709 
1710 /* Register: I2S_PUBLISH_RXPTRUPD */
1711 /* Description: Publish configuration for event RXPTRUPD */
1712 
1713 /* Bit 31 :   */
1714 #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
1715 #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
1716 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
1717 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1718 
1719 /* Bits 3..0 : Channel that event RXPTRUPD will publish to. */
1720 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1721 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1722 
1723 /* Register: I2S_PUBLISH_STOPPED */
1724 /* Description: Publish configuration for event STOPPED */
1725 
1726 /* Bit 31 :   */
1727 #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
1728 #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
1729 #define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
1730 #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
1731 
1732 /* Bits 3..0 : Channel that event STOPPED will publish to. */
1733 #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1734 #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1735 
1736 /* Register: I2S_PUBLISH_TXPTRUPD */
1737 /* Description: Publish configuration for event TXPTRUPD */
1738 
1739 /* Bit 31 :   */
1740 #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */
1741 #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */
1742 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */
1743 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1744 
1745 /* Bits 3..0 : Channel that event TXPTRUPD will publish to. */
1746 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1747 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1748 
1749 /* Register: I2S_INTEN */
1750 /* Description: Enable or disable interrupt */
1751 
1752 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */
1753 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
1754 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
1755 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
1756 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
1757 
1758 /* Bit 2 : Enable or disable interrupt for event STOPPED */
1759 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1760 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
1761 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
1762 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
1763 
1764 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
1765 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1766 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
1767 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
1768 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
1769 
1770 /* Register: I2S_INTENSET */
1771 /* Description: Enable interrupt */
1772 
1773 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
1774 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
1775 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
1776 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1777 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1778 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
1779 
1780 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
1781 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1782 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
1783 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1784 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1785 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
1786 
1787 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
1788 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1789 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
1790 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1791 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1792 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
1793 
1794 /* Register: I2S_INTENCLR */
1795 /* Description: Disable interrupt */
1796 
1797 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
1798 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
1799 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
1800 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1801 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1802 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
1803 
1804 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
1805 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
1806 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
1807 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1808 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1809 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
1810 
1811 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
1812 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1813 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
1814 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1815 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1816 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
1817 
1818 /* Register: I2S_ENABLE */
1819 /* Description: Enable I2S module. */
1820 
1821 /* Bit 0 : Enable I2S module. */
1822 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1823 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1824 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1825 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
1826 
1827 /* Register: I2S_CONFIG_MODE */
1828 /* Description: I2S mode. */
1829 
1830 /* Bit 0 : I2S mode. */
1831 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
1832 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
1833 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
1834 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
1835 
1836 /* Register: I2S_CONFIG_RXEN */
1837 /* Description: Reception (RX) enable. */
1838 
1839 /* Bit 0 : Reception (RX) enable. */
1840 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
1841 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
1842 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
1843 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
1844 
1845 /* Register: I2S_CONFIG_TXEN */
1846 /* Description: Transmission (TX) enable. */
1847 
1848 /* Bit 0 : Transmission (TX) enable. */
1849 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
1850 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
1851 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
1852 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
1853 
1854 /* Register: I2S_CONFIG_MCKEN */
1855 /* Description: Master clock generator enable. */
1856 
1857 /* Bit 0 : Master clock generator enable. */
1858 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
1859 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
1860 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
1861 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
1862 
1863 /* Register: I2S_CONFIG_MCKFREQ */
1864 /* Description: Master clock generator frequency. */
1865 
1866 /* Bits 31..0 : Master clock generator frequency. */
1867 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
1868 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
1869 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
1870 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
1871 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
1872 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
1873 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
1874 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
1875 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
1876 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
1877 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
1878 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
1879 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
1880 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
1881 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
1882 
1883 /* Register: I2S_CONFIG_RATIO */
1884 /* Description: MCK / LRCK ratio. */
1885 
1886 /* Bits 3..0 : MCK / LRCK ratio. */
1887 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
1888 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
1889 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
1890 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
1891 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
1892 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
1893 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
1894 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
1895 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
1896 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
1897 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
1898 
1899 /* Register: I2S_CONFIG_SWIDTH */
1900 /* Description: Sample width. */
1901 
1902 /* Bits 1..0 : Sample width. */
1903 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
1904 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
1905 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
1906 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
1907 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
1908 
1909 /* Register: I2S_CONFIG_ALIGN */
1910 /* Description: Alignment of sample within a frame. */
1911 
1912 /* Bit 0 : Alignment of sample within a frame. */
1913 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
1914 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
1915 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
1916 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
1917 
1918 /* Register: I2S_CONFIG_FORMAT */
1919 /* Description: Frame format. */
1920 
1921 /* Bit 0 : Frame format. */
1922 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
1923 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
1924 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
1925 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
1926 
1927 /* Register: I2S_CONFIG_CHANNELS */
1928 /* Description: Enable channels. */
1929 
1930 /* Bits 1..0 : Enable channels. */
1931 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
1932 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
1933 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
1934 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
1935 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
1936 
1937 /* Register: I2S_RXD_PTR */
1938 /* Description: Receive buffer RAM start address. */
1939 
1940 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
1941 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
1942 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
1943 
1944 /* Register: I2S_TXD_PTR */
1945 /* Description: Transmit buffer RAM start address. */
1946 
1947 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
1948 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
1949 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
1950 
1951 /* Register: I2S_RXTXD_MAXCNT */
1952 /* Description: Size of RXD and TXD buffers. */
1953 
1954 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
1955 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
1956 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
1957 
1958 /* Register: I2S_PSEL_MCK */
1959 /* Description: Pin select for MCK signal. */
1960 
1961 /* Bit 31 : Connection */
1962 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
1963 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
1964 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
1965 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
1966 
1967 /* Bits 4..0 : Pin number */
1968 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
1969 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
1970 
1971 /* Register: I2S_PSEL_SCK */
1972 /* Description: Pin select for SCK signal. */
1973 
1974 /* Bit 31 : Connection */
1975 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
1976 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
1977 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
1978 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
1979 
1980 /* Bits 4..0 : Pin number */
1981 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
1982 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
1983 
1984 /* Register: I2S_PSEL_LRCK */
1985 /* Description: Pin select for LRCK signal. */
1986 
1987 /* Bit 31 : Connection */
1988 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
1989 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
1990 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
1991 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
1992 
1993 /* Bits 4..0 : Pin number */
1994 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
1995 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
1996 
1997 /* Register: I2S_PSEL_SDIN */
1998 /* Description: Pin select for SDIN signal. */
1999 
2000 /* Bit 31 : Connection */
2001 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2002 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2003 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2004 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2005 
2006 /* Bits 4..0 : Pin number */
2007 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2008 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2009 
2010 /* Register: I2S_PSEL_SDOUT */
2011 /* Description: Pin select for SDOUT signal. */
2012 
2013 /* Bit 31 : Connection */
2014 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2015 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2016 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2017 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2018 
2019 /* Bits 4..0 : Pin number */
2020 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2021 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2022 
2023 
2024 /* Peripheral: IPC */
2025 /* Description: Inter Processor Communication 0 */
2026 
2027 /* Register: IPC_TASKS_SEND */
2028 /* Description: Description collection: Trigger events on channel enabled in SEND_CNF[n]. */
2029 
2030 /* Bit 0 : Trigger events on channel enabled in SEND_CNF[n]. */
2031 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */
2032 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */
2033 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
2034 
2035 /* Register: IPC_SUBSCRIBE_SEND */
2036 /* Description: Description collection: Subscribe configuration for task SEND[n] */
2037 
2038 /* Bit 31 :   */
2039 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */
2040 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */
2041 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */
2042 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
2043 
2044 /* Bits 3..0 : Channel that task SEND[n] will subscribe to */
2045 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2046 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2047 
2048 /* Register: IPC_EVENTS_RECEIVE */
2049 /* Description: Description collection: Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */
2050 
2051 /* Bit 0 : Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */
2052 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */
2053 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */
2054 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */
2055 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */
2056 
2057 /* Register: IPC_PUBLISH_RECEIVE */
2058 /* Description: Description collection: Publish configuration for event RECEIVE[n] */
2059 
2060 /* Bit 31 :   */
2061 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */
2062 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */
2063 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */
2064 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
2065 
2066 /* Bits 3..0 : Channel that event RECEIVE[n] will publish to. */
2067 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2068 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2069 
2070 /* Register: IPC_INTEN */
2071 /* Description: Enable or disable interrupt */
2072 
2073 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
2074 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2075 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2076 #define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */
2077 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
2078 
2079 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
2080 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2081 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2082 #define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */
2083 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
2084 
2085 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
2086 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2087 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2088 #define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */
2089 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
2090 
2091 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
2092 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2093 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2094 #define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */
2095 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
2096 
2097 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
2098 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2099 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2100 #define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */
2101 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
2102 
2103 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
2104 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2105 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2106 #define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */
2107 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
2108 
2109 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
2110 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2111 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2112 #define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */
2113 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
2114 
2115 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
2116 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2117 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2118 #define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */
2119 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
2120 
2121 /* Register: IPC_INTENSET */
2122 /* Description: Enable interrupt */
2123 
2124 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
2125 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2126 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2127 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2128 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2129 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
2130 
2131 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
2132 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2133 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2134 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2135 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2136 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
2137 
2138 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
2139 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2140 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2141 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2142 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2143 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
2144 
2145 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
2146 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2147 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2148 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2149 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2150 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
2151 
2152 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
2153 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2154 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2155 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2156 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2157 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
2158 
2159 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
2160 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2161 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2162 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2163 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2164 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
2165 
2166 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
2167 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2168 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2169 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2170 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2171 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
2172 
2173 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
2174 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2175 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2176 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2177 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2178 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
2179 
2180 /* Register: IPC_INTENCLR */
2181 /* Description: Disable interrupt */
2182 
2183 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
2184 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2185 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2186 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2187 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2188 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
2189 
2190 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
2191 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2192 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2193 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2194 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2195 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
2196 
2197 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
2198 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2199 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2200 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2201 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2202 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
2203 
2204 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
2205 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2206 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2207 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2208 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2209 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
2210 
2211 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
2212 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2213 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2214 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2215 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2216 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
2217 
2218 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
2219 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2220 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2221 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2222 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2223 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
2224 
2225 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
2226 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2227 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2228 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2229 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2230 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
2231 
2232 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
2233 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2234 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2235 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2236 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2237 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
2238 
2239 /* Register: IPC_INTPEND */
2240 /* Description: Pending interrupts */
2241 
2242 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
2243 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */
2244 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */
2245 #define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */
2246 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
2247 
2248 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
2249 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */
2250 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */
2251 #define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */
2252 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
2253 
2254 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
2255 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */
2256 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */
2257 #define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */
2258 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
2259 
2260 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
2261 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */
2262 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */
2263 #define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */
2264 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
2265 
2266 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
2267 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */
2268 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */
2269 #define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */
2270 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
2271 
2272 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
2273 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */
2274 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */
2275 #define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */
2276 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
2277 
2278 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
2279 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2280 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */
2281 #define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */
2282 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
2283 
2284 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
2285 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */
2286 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */
2287 #define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */
2288 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
2289 
2290 /* Register: IPC_SEND_CNF */
2291 /* Description: Description collection: Send event configuration for TASKS_SEND[n]. */
2292 
2293 /* Bit 7 : Enable broadcasting on channel 7. */
2294 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
2295 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
2296 #define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast. */
2297 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast. */
2298 
2299 /* Bit 6 : Enable broadcasting on channel 6. */
2300 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
2301 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
2302 #define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast. */
2303 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast. */
2304 
2305 /* Bit 5 : Enable broadcasting on channel 5. */
2306 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
2307 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
2308 #define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast. */
2309 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast. */
2310 
2311 /* Bit 4 : Enable broadcasting on channel 4. */
2312 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
2313 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
2314 #define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast. */
2315 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast. */
2316 
2317 /* Bit 3 : Enable broadcasting on channel 3. */
2318 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
2319 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
2320 #define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast. */
2321 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast. */
2322 
2323 /* Bit 2 : Enable broadcasting on channel 2. */
2324 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
2325 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
2326 #define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast. */
2327 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast. */
2328 
2329 /* Bit 1 : Enable broadcasting on channel 1. */
2330 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
2331 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
2332 #define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast. */
2333 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast. */
2334 
2335 /* Bit 0 : Enable broadcasting on channel 0. */
2336 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
2337 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
2338 #define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast. */
2339 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast. */
2340 
2341 /* Register: IPC_RECEIVE_CNF */
2342 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n]. */
2343 
2344 /* Bit 7 : Enable subscription to channel 7. */
2345 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */
2346 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */
2347 #define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events. */
2348 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events. */
2349 
2350 /* Bit 6 : Enable subscription to channel 6. */
2351 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */
2352 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */
2353 #define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events. */
2354 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events. */
2355 
2356 /* Bit 5 : Enable subscription to channel 5. */
2357 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */
2358 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */
2359 #define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events. */
2360 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events. */
2361 
2362 /* Bit 4 : Enable subscription to channel 4. */
2363 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */
2364 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */
2365 #define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events. */
2366 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events. */
2367 
2368 /* Bit 3 : Enable subscription to channel 3. */
2369 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */
2370 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */
2371 #define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events. */
2372 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events. */
2373 
2374 /* Bit 2 : Enable subscription to channel 2. */
2375 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */
2376 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */
2377 #define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events. */
2378 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events. */
2379 
2380 /* Bit 1 : Enable subscription to channel 1. */
2381 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
2382 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */
2383 #define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events. */
2384 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events. */
2385 
2386 /* Bit 0 : Enable subscription to channel 0. */
2387 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */
2388 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */
2389 #define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events. */
2390 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events. */
2391 
2392 /* Register: IPC_GPMEM */
2393 /* Description: Description collection: General purpose memory. */
2394 
2395 /* Bits 31..0 : General purpose memory */
2396 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */
2397 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */
2398 
2399 
2400 /* Peripheral: KMU */
2401 /* Description: Key management unit 0 */
2402 
2403 /* Register: KMU_TASKS_PUSH_KEYSLOT */
2404 /* Description: Push a key slot over secure APB */
2405 
2406 /* Bit 0 : Push a key slot over secure APB */
2407 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */
2408 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */
2409 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */
2410 
2411 /* Register: KMU_EVENTS_KEYSLOT_PUSHED */
2412 /* Description: Key successfully pushed over secure APB */
2413 
2414 /* Bit 0 : Key successfully pushed over secure APB */
2415 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */
2416 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */
2417 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */
2418 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */
2419 
2420 /* Register: KMU_EVENTS_KEYSLOT_REVOKED */
2421 /* Description: Key has been revoked and cannot be tasked for selection */
2422 
2423 /* Bit 0 : Key has been revoked and cannot be tasked for selection */
2424 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */
2425 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */
2426 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */
2427 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */
2428 
2429 /* Register: KMU_EVENTS_KEYSLOT_ERROR */
2430 /* Description: No key slot selected, no destination address defined, or error during push operation */
2431 
2432 /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */
2433 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */
2434 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */
2435 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */
2436 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */
2437 
2438 /* Register: KMU_INTEN */
2439 /* Description: Enable or disable interrupt */
2440 
2441 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */
2442 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2443 #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2444 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */
2445 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */
2446 
2447 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
2448 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2449 #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2450 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */
2451 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */
2452 
2453 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */
2454 #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2455 #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2456 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */
2457 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */
2458 
2459 /* Register: KMU_INTENSET */
2460 /* Description: Enable interrupt */
2461 
2462 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
2463 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2464 #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2465 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2466 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2467 #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */
2468 
2469 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
2470 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2471 #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2472 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2473 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2474 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */
2475 
2476 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
2477 #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2478 #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2479 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2480 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2481 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */
2482 
2483 /* Register: KMU_INTENCLR */
2484 /* Description: Disable interrupt */
2485 
2486 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
2487 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2488 #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2489 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2490 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2491 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */
2492 
2493 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
2494 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2495 #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2496 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2497 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2498 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */
2499 
2500 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
2501 #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2502 #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2503 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2504 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2505 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */
2506 
2507 /* Register: KMU_INTPEND */
2508 /* Description: Pending interrupts */
2509 
2510 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */
2511 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */
2512 #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */
2513 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */
2514 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */
2515 
2516 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
2517 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2518 #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */
2519 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */
2520 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */
2521 
2522 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */
2523 #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */
2524 #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */
2525 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */
2526 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */
2527 
2528 /* Register: KMU_STATUS */
2529 /* Description: Status bits for KMU operation */
2530 
2531 /* Bit 1 : Violation status */
2532 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
2533 #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */
2534 #define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */
2535 #define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */
2536 
2537 /* Bit 0 : Key slot ID successfully selected by the KMU */
2538 #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */
2539 #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
2540 #define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */
2541 #define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */
2542 
2543 /* Register: KMU_SELECTKEYSLOT */
2544 /* Description: Select key slot ID to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */
2545 
2546 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started NOTE: ID=0 is not a valid key ID. The 0 ID should be used when the KMU is idle or not in use NOTE: Note that index N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU keyslot ID=N+1 */
2547 #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */
2548 #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */
2549 
2550 
2551 /* Peripheral: NVMC */
2552 /* Description: Non-volatile memory controller 0 */
2553 
2554 /* Register: NVMC_READY */
2555 /* Description: Ready flag */
2556 
2557 /* Bit 0 : NVMC is ready or busy */
2558 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
2559 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
2560 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
2561 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
2562 
2563 /* Register: NVMC_READYNEXT */
2564 /* Description: Ready flag */
2565 
2566 /* Bit 0 : NVMC can accept a new write operation */
2567 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
2568 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
2569 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
2570 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
2571 
2572 /* Register: NVMC_CONFIG */
2573 /* Description: Configuration register */
2574 
2575 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
2576 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
2577 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
2578 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
2579 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2580 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2581 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
2582 
2583 /* Register: NVMC_ERASEALL */
2584 /* Description: Register for erasing all non-volatile user memory */
2585 
2586 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */
2587 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
2588 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
2589 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
2590 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
2591 
2592 /* Register: NVMC_ERASEPAGEPARTIALCFG */
2593 /* Description: Register for partial erase configuration */
2594 
2595 /* Bits 6..0 : Duration of the partial erase in milliseconds */
2596 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
2597 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
2598 
2599 /* Register: NVMC_ICACHECNF */
2600 /* Description: I-code cache configuration register */
2601 
2602 /* Bit 8 : Cache profiling enable */
2603 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
2604 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
2605 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
2606 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
2607 
2608 /* Bit 0 : Cache enable */
2609 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
2610 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
2611 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
2612 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
2613 
2614 /* Register: NVMC_IHIT */
2615 /* Description: I-code cache hit counter */
2616 
2617 /* Bits 31..0 : Number of cache hits */
2618 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
2619 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
2620 
2621 /* Register: NVMC_IMISS */
2622 /* Description: I-code cache miss counter */
2623 
2624 /* Bits 31..0 : Number of cache misses */
2625 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
2626 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
2627 
2628 /* Register: NVMC_CONFIGNS */
2629 /* Description: Unspecified */
2630 
2631 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
2632 #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */
2633 #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */
2634 #define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */
2635 #define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */
2636 #define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */
2637 
2638 /* Register: NVMC_WRITEUICRNS */
2639 /* Description: Non-secure APPROTECT enable register */
2640 
2641 /* Bits 31..4 : Key to write in order to validate the write operation */
2642 #define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */
2643 #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */
2644 #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */
2645 
2646 /* Bit 0 : Allow non-secure code to set APPROTECT */
2647 #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */
2648 #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */
2649 #define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */
2650 
2651 /* Register: NVMC_FORCEONNVM */
2652 /* Description: Force on all NVM supplies. Also see the internal section in the NVMC chapter. */
2653 
2654 /* Bit 0 : Force on all NVM supplies. Also see the internal section in the NVMC chapter. */
2655 #define NVMC_FORCEONNVM_FORCEONNVM_Pos (0UL) /*!< Position of FORCEONNVM field. */
2656 #define NVMC_FORCEONNVM_FORCEONNVM_Msk (0x1UL << NVMC_FORCEONNVM_FORCEONNVM_Pos) /*!< Bit mask of FORCEONNVM field. */
2657 #define NVMC_FORCEONNVM_FORCEONNVM_DoNotForceOn (0UL) /*!< Do not force on NVM supply */
2658 #define NVMC_FORCEONNVM_FORCEONNVM_ForceOn (1UL) /*!< Force on NVM supply */
2659 
2660 /* Register: NVMC_FORCEOFFNVM */
2661 /* Description: Force off NVM supply. Also see the internal section in the NVMC chapter. */
2662 
2663 /* Bits 31..8 : KEY */
2664 #define NVMC_FORCEOFFNVM_KEY_Pos (8UL) /*!< Position of KEY field. */
2665 #define NVMC_FORCEOFFNVM_KEY_Msk (0xFFFFFFUL << NVMC_FORCEOFFNVM_KEY_Pos) /*!< Bit mask of KEY field. */
2666 #define NVMC_FORCEOFFNVM_KEY_EnableWrite (0xACCE55UL) /*!< Must be written in order to write to bits 0-7. Any other value will ignore writes to this register. Read as zero. */
2667 
2668 /* Bit 1 : Force off NVM supply 1. Also see the internal section in the NVMC chapter. */
2669 #define NVMC_FORCEOFFNVM_FORCEOFFNVM1_Pos (1UL) /*!< Position of FORCEOFFNVM1 field. */
2670 #define NVMC_FORCEOFFNVM_FORCEOFFNVM1_Msk (0x1UL << NVMC_FORCEOFFNVM_FORCEOFFNVM1_Pos) /*!< Bit mask of FORCEOFFNVM1 field. */
2671 #define NVMC_FORCEOFFNVM_FORCEOFFNVM1_DoNotForceOff (0UL) /*!< Do not force off supply */
2672 #define NVMC_FORCEOFFNVM_FORCEOFFNVM1_ForceOff (1UL) /*!< Force off supply */
2673 
2674 /* Bit 0 : Force off NVM supply 0. Also see the internal section in the NVMC chapter. */
2675 #define NVMC_FORCEOFFNVM_FORCEOFFNVM0_Pos (0UL) /*!< Position of FORCEOFFNVM0 field. */
2676 #define NVMC_FORCEOFFNVM_FORCEOFFNVM0_Msk (0x1UL << NVMC_FORCEOFFNVM_FORCEOFFNVM0_Pos) /*!< Bit mask of FORCEOFFNVM0 field. */
2677 #define NVMC_FORCEOFFNVM_FORCEOFFNVM0_DoNotForceOff (0UL) /*!< Do not force off supply */
2678 #define NVMC_FORCEOFFNVM_FORCEOFFNVM0_ForceOff (1UL) /*!< Force off supply */
2679 
2680 
2681 /* Peripheral: GPIO */
2682 /* Description: GPIO Port 0 */
2683 
2684 /* Register: GPIO_OUT */
2685 /* Description: Write GPIO port */
2686 
2687 /* Bit 31 : Pin 31 */
2688 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2689 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2690 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
2691 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
2692 
2693 /* Bit 30 : Pin 30 */
2694 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2695 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2696 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
2697 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
2698 
2699 /* Bit 29 : Pin 29 */
2700 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2701 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2702 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
2703 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
2704 
2705 /* Bit 28 : Pin 28 */
2706 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2707 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2708 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
2709 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
2710 
2711 /* Bit 27 : Pin 27 */
2712 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2713 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2714 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
2715 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
2716 
2717 /* Bit 26 : Pin 26 */
2718 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2719 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2720 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
2721 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
2722 
2723 /* Bit 25 : Pin 25 */
2724 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2725 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2726 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
2727 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
2728 
2729 /* Bit 24 : Pin 24 */
2730 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2731 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2732 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
2733 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
2734 
2735 /* Bit 23 : Pin 23 */
2736 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2737 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2738 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
2739 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
2740 
2741 /* Bit 22 : Pin 22 */
2742 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2743 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2744 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
2745 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
2746 
2747 /* Bit 21 : Pin 21 */
2748 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2749 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2750 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
2751 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
2752 
2753 /* Bit 20 : Pin 20 */
2754 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2755 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2756 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
2757 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
2758 
2759 /* Bit 19 : Pin 19 */
2760 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2761 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2762 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
2763 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
2764 
2765 /* Bit 18 : Pin 18 */
2766 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2767 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2768 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
2769 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
2770 
2771 /* Bit 17 : Pin 17 */
2772 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2773 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2774 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
2775 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
2776 
2777 /* Bit 16 : Pin 16 */
2778 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2779 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2780 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
2781 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
2782 
2783 /* Bit 15 : Pin 15 */
2784 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2785 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2786 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
2787 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
2788 
2789 /* Bit 14 : Pin 14 */
2790 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2791 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2792 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
2793 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
2794 
2795 /* Bit 13 : Pin 13 */
2796 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2797 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2798 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
2799 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
2800 
2801 /* Bit 12 : Pin 12 */
2802 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2803 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2804 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
2805 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
2806 
2807 /* Bit 11 : Pin 11 */
2808 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2809 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2810 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
2811 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
2812 
2813 /* Bit 10 : Pin 10 */
2814 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2815 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2816 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
2817 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
2818 
2819 /* Bit 9 : Pin 9 */
2820 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2821 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2822 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
2823 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
2824 
2825 /* Bit 8 : Pin 8 */
2826 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2827 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2828 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
2829 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
2830 
2831 /* Bit 7 : Pin 7 */
2832 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2833 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2834 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
2835 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
2836 
2837 /* Bit 6 : Pin 6 */
2838 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2839 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2840 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
2841 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
2842 
2843 /* Bit 5 : Pin 5 */
2844 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2845 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2846 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
2847 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
2848 
2849 /* Bit 4 : Pin 4 */
2850 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2851 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2852 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
2853 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
2854 
2855 /* Bit 3 : Pin 3 */
2856 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2857 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2858 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
2859 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
2860 
2861 /* Bit 2 : Pin 2 */
2862 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2863 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2864 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
2865 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
2866 
2867 /* Bit 1 : Pin 1 */
2868 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2869 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2870 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
2871 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
2872 
2873 /* Bit 0 : Pin 0 */
2874 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2875 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2876 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
2877 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
2878 
2879 /* Register: GPIO_OUTSET */
2880 /* Description: Set individual bits in GPIO port */
2881 
2882 /* Bit 31 : Pin 31 */
2883 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2884 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2885 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
2886 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2887 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2888 
2889 /* Bit 30 : Pin 30 */
2890 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2891 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2892 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
2893 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2894 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2895 
2896 /* Bit 29 : Pin 29 */
2897 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2898 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2899 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
2900 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2901 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2902 
2903 /* Bit 28 : Pin 28 */
2904 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2905 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2906 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
2907 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2908 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2909 
2910 /* Bit 27 : Pin 27 */
2911 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2912 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2913 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
2914 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2915 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2916 
2917 /* Bit 26 : Pin 26 */
2918 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2919 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2920 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
2921 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2922 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2923 
2924 /* Bit 25 : Pin 25 */
2925 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2926 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2927 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
2928 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2929 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2930 
2931 /* Bit 24 : Pin 24 */
2932 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2933 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2934 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
2935 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2936 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2937 
2938 /* Bit 23 : Pin 23 */
2939 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2940 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2941 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
2942 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2943 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2944 
2945 /* Bit 22 : Pin 22 */
2946 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2947 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2948 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
2949 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2950 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2951 
2952 /* Bit 21 : Pin 21 */
2953 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2954 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2955 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
2956 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2957 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2958 
2959 /* Bit 20 : Pin 20 */
2960 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2961 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2962 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
2963 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2964 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2965 
2966 /* Bit 19 : Pin 19 */
2967 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2968 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2969 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
2970 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2971 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2972 
2973 /* Bit 18 : Pin 18 */
2974 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2975 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2976 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
2977 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2978 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2979 
2980 /* Bit 17 : Pin 17 */
2981 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2982 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2983 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
2984 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2985 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2986 
2987 /* Bit 16 : Pin 16 */
2988 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2989 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2990 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
2991 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2992 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2993 
2994 /* Bit 15 : Pin 15 */
2995 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2996 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2997 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
2998 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
2999 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3000 
3001 /* Bit 14 : Pin 14 */
3002 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3003 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3004 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
3005 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
3006 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3007 
3008 /* Bit 13 : Pin 13 */
3009 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3010 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3011 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
3012 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
3013 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3014 
3015 /* Bit 12 : Pin 12 */
3016 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3017 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3018 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
3019 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
3020 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3021 
3022 /* Bit 11 : Pin 11 */
3023 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3024 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3025 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
3026 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
3027 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3028 
3029 /* Bit 10 : Pin 10 */
3030 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3031 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3032 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
3033 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
3034 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3035 
3036 /* Bit 9 : Pin 9 */
3037 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3038 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3039 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
3040 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
3041 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3042 
3043 /* Bit 8 : Pin 8 */
3044 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3045 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3046 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
3047 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
3048 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3049 
3050 /* Bit 7 : Pin 7 */
3051 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3052 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3053 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
3054 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
3055 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3056 
3057 /* Bit 6 : Pin 6 */
3058 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3059 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3060 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
3061 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
3062 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3063 
3064 /* Bit 5 : Pin 5 */
3065 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3066 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3067 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
3068 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
3069 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3070 
3071 /* Bit 4 : Pin 4 */
3072 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3073 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3074 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
3075 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
3076 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3077 
3078 /* Bit 3 : Pin 3 */
3079 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3080 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3081 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
3082 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
3083 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3084 
3085 /* Bit 2 : Pin 2 */
3086 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3087 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3088 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
3089 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
3090 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3091 
3092 /* Bit 1 : Pin 1 */
3093 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3094 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3095 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
3096 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
3097 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3098 
3099 /* Bit 0 : Pin 0 */
3100 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3101 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3102 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
3103 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
3104 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
3105 
3106 /* Register: GPIO_OUTCLR */
3107 /* Description: Clear individual bits in GPIO port */
3108 
3109 /* Bit 31 : Pin 31 */
3110 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3111 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3112 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
3113 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
3114 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3115 
3116 /* Bit 30 : Pin 30 */
3117 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3118 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3119 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
3120 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
3121 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3122 
3123 /* Bit 29 : Pin 29 */
3124 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3125 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3126 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
3127 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
3128 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3129 
3130 /* Bit 28 : Pin 28 */
3131 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3132 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3133 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
3134 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
3135 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3136 
3137 /* Bit 27 : Pin 27 */
3138 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3139 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3140 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
3141 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
3142 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3143 
3144 /* Bit 26 : Pin 26 */
3145 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3146 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3147 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
3148 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
3149 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3150 
3151 /* Bit 25 : Pin 25 */
3152 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3153 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3154 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
3155 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
3156 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3157 
3158 /* Bit 24 : Pin 24 */
3159 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3160 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3161 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
3162 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
3163 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3164 
3165 /* Bit 23 : Pin 23 */
3166 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3167 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3168 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
3169 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
3170 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3171 
3172 /* Bit 22 : Pin 22 */
3173 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3174 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3175 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
3176 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
3177 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3178 
3179 /* Bit 21 : Pin 21 */
3180 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3181 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3182 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
3183 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
3184 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3185 
3186 /* Bit 20 : Pin 20 */
3187 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3188 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3189 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
3190 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
3191 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3192 
3193 /* Bit 19 : Pin 19 */
3194 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3195 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3196 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
3197 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
3198 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3199 
3200 /* Bit 18 : Pin 18 */
3201 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3202 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3203 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
3204 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
3205 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3206 
3207 /* Bit 17 : Pin 17 */
3208 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3209 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3210 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
3211 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
3212 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3213 
3214 /* Bit 16 : Pin 16 */
3215 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3216 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3217 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
3218 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
3219 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3220 
3221 /* Bit 15 : Pin 15 */
3222 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3223 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3224 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
3225 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
3226 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3227 
3228 /* Bit 14 : Pin 14 */
3229 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3230 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3231 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
3232 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
3233 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3234 
3235 /* Bit 13 : Pin 13 */
3236 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3237 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3238 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
3239 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
3240 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3241 
3242 /* Bit 12 : Pin 12 */
3243 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3244 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3245 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
3246 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
3247 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3248 
3249 /* Bit 11 : Pin 11 */
3250 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3251 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3252 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
3253 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
3254 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3255 
3256 /* Bit 10 : Pin 10 */
3257 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3258 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3259 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
3260 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
3261 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3262 
3263 /* Bit 9 : Pin 9 */
3264 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3265 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3266 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
3267 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
3268 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3269 
3270 /* Bit 8 : Pin 8 */
3271 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3272 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3273 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
3274 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
3275 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3276 
3277 /* Bit 7 : Pin 7 */
3278 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3279 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3280 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
3281 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
3282 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3283 
3284 /* Bit 6 : Pin 6 */
3285 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3286 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3287 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
3288 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
3289 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3290 
3291 /* Bit 5 : Pin 5 */
3292 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3293 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3294 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
3295 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
3296 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3297 
3298 /* Bit 4 : Pin 4 */
3299 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3300 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3301 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
3302 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
3303 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3304 
3305 /* Bit 3 : Pin 3 */
3306 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3307 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3308 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
3309 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
3310 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3311 
3312 /* Bit 2 : Pin 2 */
3313 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3314 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3315 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
3316 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
3317 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3318 
3319 /* Bit 1 : Pin 1 */
3320 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3321 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3322 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
3323 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
3324 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3325 
3326 /* Bit 0 : Pin 0 */
3327 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3328 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3329 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
3330 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
3331 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
3332 
3333 /* Register: GPIO_IN */
3334 /* Description: Read GPIO port */
3335 
3336 /* Bit 31 : Pin 31 */
3337 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3338 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3339 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
3340 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
3341 
3342 /* Bit 30 : Pin 30 */
3343 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3344 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3345 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
3346 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
3347 
3348 /* Bit 29 : Pin 29 */
3349 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3350 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3351 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
3352 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
3353 
3354 /* Bit 28 : Pin 28 */
3355 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3356 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3357 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
3358 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
3359 
3360 /* Bit 27 : Pin 27 */
3361 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3362 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3363 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
3364 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
3365 
3366 /* Bit 26 : Pin 26 */
3367 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3368 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3369 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
3370 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
3371 
3372 /* Bit 25 : Pin 25 */
3373 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3374 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3375 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
3376 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
3377 
3378 /* Bit 24 : Pin 24 */
3379 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3380 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3381 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
3382 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
3383 
3384 /* Bit 23 : Pin 23 */
3385 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3386 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3387 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
3388 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
3389 
3390 /* Bit 22 : Pin 22 */
3391 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3392 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3393 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
3394 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
3395 
3396 /* Bit 21 : Pin 21 */
3397 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3398 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3399 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
3400 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
3401 
3402 /* Bit 20 : Pin 20 */
3403 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3404 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3405 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
3406 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
3407 
3408 /* Bit 19 : Pin 19 */
3409 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3410 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3411 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
3412 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
3413 
3414 /* Bit 18 : Pin 18 */
3415 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3416 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3417 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
3418 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
3419 
3420 /* Bit 17 : Pin 17 */
3421 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3422 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3423 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
3424 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
3425 
3426 /* Bit 16 : Pin 16 */
3427 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3428 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3429 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
3430 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
3431 
3432 /* Bit 15 : Pin 15 */
3433 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3434 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3435 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
3436 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
3437 
3438 /* Bit 14 : Pin 14 */
3439 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3440 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3441 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
3442 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
3443 
3444 /* Bit 13 : Pin 13 */
3445 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3446 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3447 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
3448 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
3449 
3450 /* Bit 12 : Pin 12 */
3451 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3452 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3453 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
3454 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
3455 
3456 /* Bit 11 : Pin 11 */
3457 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3458 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3459 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
3460 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
3461 
3462 /* Bit 10 : Pin 10 */
3463 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3464 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3465 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
3466 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
3467 
3468 /* Bit 9 : Pin 9 */
3469 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3470 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3471 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
3472 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
3473 
3474 /* Bit 8 : Pin 8 */
3475 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3476 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3477 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
3478 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
3479 
3480 /* Bit 7 : Pin 7 */
3481 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3482 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3483 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
3484 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
3485 
3486 /* Bit 6 : Pin 6 */
3487 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3488 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3489 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
3490 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
3491 
3492 /* Bit 5 : Pin 5 */
3493 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3494 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3495 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
3496 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
3497 
3498 /* Bit 4 : Pin 4 */
3499 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3500 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3501 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
3502 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
3503 
3504 /* Bit 3 : Pin 3 */
3505 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3506 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3507 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
3508 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
3509 
3510 /* Bit 2 : Pin 2 */
3511 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3512 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3513 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
3514 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
3515 
3516 /* Bit 1 : Pin 1 */
3517 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3518 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3519 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
3520 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
3521 
3522 /* Bit 0 : Pin 0 */
3523 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3524 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3525 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
3526 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
3527 
3528 /* Register: GPIO_DIR */
3529 /* Description: Direction of GPIO pins */
3530 
3531 /* Bit 31 : Pin 31 */
3532 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3533 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3534 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
3535 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
3536 
3537 /* Bit 30 : Pin 30 */
3538 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3539 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3540 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
3541 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
3542 
3543 /* Bit 29 : Pin 29 */
3544 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3545 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3546 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
3547 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
3548 
3549 /* Bit 28 : Pin 28 */
3550 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3551 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3552 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
3553 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
3554 
3555 /* Bit 27 : Pin 27 */
3556 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3557 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3558 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
3559 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
3560 
3561 /* Bit 26 : Pin 26 */
3562 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3563 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3564 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
3565 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
3566 
3567 /* Bit 25 : Pin 25 */
3568 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3569 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3570 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
3571 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
3572 
3573 /* Bit 24 : Pin 24 */
3574 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3575 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3576 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
3577 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
3578 
3579 /* Bit 23 : Pin 23 */
3580 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3581 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3582 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
3583 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
3584 
3585 /* Bit 22 : Pin 22 */
3586 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3587 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3588 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
3589 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
3590 
3591 /* Bit 21 : Pin 21 */
3592 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3593 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3594 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
3595 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
3596 
3597 /* Bit 20 : Pin 20 */
3598 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3599 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3600 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
3601 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
3602 
3603 /* Bit 19 : Pin 19 */
3604 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3605 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3606 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
3607 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
3608 
3609 /* Bit 18 : Pin 18 */
3610 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3611 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3612 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
3613 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
3614 
3615 /* Bit 17 : Pin 17 */
3616 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3617 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3618 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
3619 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
3620 
3621 /* Bit 16 : Pin 16 */
3622 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3623 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3624 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
3625 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
3626 
3627 /* Bit 15 : Pin 15 */
3628 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3629 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3630 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
3631 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
3632 
3633 /* Bit 14 : Pin 14 */
3634 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3635 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3636 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
3637 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
3638 
3639 /* Bit 13 : Pin 13 */
3640 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3641 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3642 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
3643 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
3644 
3645 /* Bit 12 : Pin 12 */
3646 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3647 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3648 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
3649 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
3650 
3651 /* Bit 11 : Pin 11 */
3652 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3653 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3654 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
3655 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
3656 
3657 /* Bit 10 : Pin 10 */
3658 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3659 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3660 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
3661 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
3662 
3663 /* Bit 9 : Pin 9 */
3664 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3665 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3666 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
3667 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
3668 
3669 /* Bit 8 : Pin 8 */
3670 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3671 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3672 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
3673 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
3674 
3675 /* Bit 7 : Pin 7 */
3676 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3677 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3678 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
3679 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
3680 
3681 /* Bit 6 : Pin 6 */
3682 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3683 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3684 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
3685 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
3686 
3687 /* Bit 5 : Pin 5 */
3688 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3689 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3690 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
3691 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
3692 
3693 /* Bit 4 : Pin 4 */
3694 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3695 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3696 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
3697 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
3698 
3699 /* Bit 3 : Pin 3 */
3700 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3701 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3702 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
3703 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
3704 
3705 /* Bit 2 : Pin 2 */
3706 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3707 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3708 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
3709 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
3710 
3711 /* Bit 1 : Pin 1 */
3712 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3713 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3714 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
3715 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
3716 
3717 /* Bit 0 : Pin 0 */
3718 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3719 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3720 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
3721 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
3722 
3723 /* Register: GPIO_DIRSET */
3724 /* Description: DIR set register */
3725 
3726 /* Bit 31 : Set as output pin 31 */
3727 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3728 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3729 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
3730 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3731 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3732 
3733 /* Bit 30 : Set as output pin 30 */
3734 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3735 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3736 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
3737 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3738 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3739 
3740 /* Bit 29 : Set as output pin 29 */
3741 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3742 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3743 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
3744 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3745 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3746 
3747 /* Bit 28 : Set as output pin 28 */
3748 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3749 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3750 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
3751 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3752 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3753 
3754 /* Bit 27 : Set as output pin 27 */
3755 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3756 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3757 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
3758 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3759 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3760 
3761 /* Bit 26 : Set as output pin 26 */
3762 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3763 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3764 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
3765 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3766 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3767 
3768 /* Bit 25 : Set as output pin 25 */
3769 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3770 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3771 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
3772 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3773 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3774 
3775 /* Bit 24 : Set as output pin 24 */
3776 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3777 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3778 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
3779 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3780 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3781 
3782 /* Bit 23 : Set as output pin 23 */
3783 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3784 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3785 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
3786 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3787 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3788 
3789 /* Bit 22 : Set as output pin 22 */
3790 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3791 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3792 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
3793 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3794 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3795 
3796 /* Bit 21 : Set as output pin 21 */
3797 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3798 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3799 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
3800 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3801 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3802 
3803 /* Bit 20 : Set as output pin 20 */
3804 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3805 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3806 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
3807 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3808 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3809 
3810 /* Bit 19 : Set as output pin 19 */
3811 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3812 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3813 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
3814 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3815 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3816 
3817 /* Bit 18 : Set as output pin 18 */
3818 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3819 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3820 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
3821 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3822 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3823 
3824 /* Bit 17 : Set as output pin 17 */
3825 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3826 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3827 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
3828 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3829 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3830 
3831 /* Bit 16 : Set as output pin 16 */
3832 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3833 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3834 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
3835 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3836 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3837 
3838 /* Bit 15 : Set as output pin 15 */
3839 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3840 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3841 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
3842 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3843 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3844 
3845 /* Bit 14 : Set as output pin 14 */
3846 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3847 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3848 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
3849 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3850 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3851 
3852 /* Bit 13 : Set as output pin 13 */
3853 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3854 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3855 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
3856 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3857 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3858 
3859 /* Bit 12 : Set as output pin 12 */
3860 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3861 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3862 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
3863 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3864 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3865 
3866 /* Bit 11 : Set as output pin 11 */
3867 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3868 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3869 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
3870 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3871 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3872 
3873 /* Bit 10 : Set as output pin 10 */
3874 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3875 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3876 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
3877 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3878 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3879 
3880 /* Bit 9 : Set as output pin 9 */
3881 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3882 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3883 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
3884 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3885 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3886 
3887 /* Bit 8 : Set as output pin 8 */
3888 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3889 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3890 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
3891 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3892 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3893 
3894 /* Bit 7 : Set as output pin 7 */
3895 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3896 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3897 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
3898 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3899 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3900 
3901 /* Bit 6 : Set as output pin 6 */
3902 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3903 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3904 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
3905 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3906 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3907 
3908 /* Bit 5 : Set as output pin 5 */
3909 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3910 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3911 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
3912 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3913 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3914 
3915 /* Bit 4 : Set as output pin 4 */
3916 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3917 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3918 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
3919 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3920 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3921 
3922 /* Bit 3 : Set as output pin 3 */
3923 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3924 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3925 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
3926 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3927 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3928 
3929 /* Bit 2 : Set as output pin 2 */
3930 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3931 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3932 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
3933 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
3934 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3935 
3936 /* Bit 1 : Set as output pin 1 */
3937 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3938 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3939 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
3940 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
3941 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3942 
3943 /* Bit 0 : Set as output pin 0 */
3944 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3945 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3946 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
3947 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
3948 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3949 
3950 /* Register: GPIO_DIRCLR */
3951 /* Description: DIR clear register */
3952 
3953 /* Bit 31 : Set as input pin 31 */
3954 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3955 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3956 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
3957 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
3958 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3959 
3960 /* Bit 30 : Set as input pin 30 */
3961 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3962 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3963 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
3964 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
3965 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3966 
3967 /* Bit 29 : Set as input pin 29 */
3968 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3969 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3970 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
3971 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
3972 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3973 
3974 /* Bit 28 : Set as input pin 28 */
3975 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3976 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3977 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
3978 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
3979 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3980 
3981 /* Bit 27 : Set as input pin 27 */
3982 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3983 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3984 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
3985 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
3986 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3987 
3988 /* Bit 26 : Set as input pin 26 */
3989 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3990 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3991 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
3992 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
3993 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3994 
3995 /* Bit 25 : Set as input pin 25 */
3996 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3997 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3998 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
3999 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
4000 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4001 
4002 /* Bit 24 : Set as input pin 24 */
4003 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4004 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4005 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
4006 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
4007 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4008 
4009 /* Bit 23 : Set as input pin 23 */
4010 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4011 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4012 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
4013 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
4014 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4015 
4016 /* Bit 22 : Set as input pin 22 */
4017 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4018 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4019 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
4020 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
4021 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4022 
4023 /* Bit 21 : Set as input pin 21 */
4024 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4025 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4026 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
4027 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
4028 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4029 
4030 /* Bit 20 : Set as input pin 20 */
4031 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4032 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4033 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
4034 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
4035 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4036 
4037 /* Bit 19 : Set as input pin 19 */
4038 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4039 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4040 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
4041 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
4042 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4043 
4044 /* Bit 18 : Set as input pin 18 */
4045 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4046 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4047 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
4048 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
4049 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4050 
4051 /* Bit 17 : Set as input pin 17 */
4052 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4053 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4054 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
4055 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
4056 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4057 
4058 /* Bit 16 : Set as input pin 16 */
4059 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4060 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4061 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
4062 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
4063 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4064 
4065 /* Bit 15 : Set as input pin 15 */
4066 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4067 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4068 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
4069 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
4070 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4071 
4072 /* Bit 14 : Set as input pin 14 */
4073 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4074 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4075 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
4076 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
4077 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4078 
4079 /* Bit 13 : Set as input pin 13 */
4080 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4081 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4082 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
4083 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
4084 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4085 
4086 /* Bit 12 : Set as input pin 12 */
4087 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4088 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4089 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
4090 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
4091 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4092 
4093 /* Bit 11 : Set as input pin 11 */
4094 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4095 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4096 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
4097 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
4098 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4099 
4100 /* Bit 10 : Set as input pin 10 */
4101 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4102 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4103 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
4104 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
4105 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4106 
4107 /* Bit 9 : Set as input pin 9 */
4108 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4109 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4110 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
4111 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
4112 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4113 
4114 /* Bit 8 : Set as input pin 8 */
4115 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4116 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4117 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
4118 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
4119 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4120 
4121 /* Bit 7 : Set as input pin 7 */
4122 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4123 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4124 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
4125 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
4126 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4127 
4128 /* Bit 6 : Set as input pin 6 */
4129 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4130 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4131 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
4132 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
4133 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4134 
4135 /* Bit 5 : Set as input pin 5 */
4136 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4137 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4138 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
4139 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
4140 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4141 
4142 /* Bit 4 : Set as input pin 4 */
4143 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4144 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4145 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
4146 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
4147 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4148 
4149 /* Bit 3 : Set as input pin 3 */
4150 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4151 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4152 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
4153 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
4154 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4155 
4156 /* Bit 2 : Set as input pin 2 */
4157 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4158 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4159 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
4160 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
4161 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4162 
4163 /* Bit 1 : Set as input pin 1 */
4164 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4165 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4166 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
4167 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
4168 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4169 
4170 /* Bit 0 : Set as input pin 0 */
4171 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4172 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4173 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
4174 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
4175 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4176 
4177 /* Register: GPIO_LATCH */
4178 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
4179 
4180 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
4181 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4182 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4183 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
4184 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
4185 
4186 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
4187 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4188 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4189 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
4190 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
4191 
4192 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
4193 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4194 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4195 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
4196 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
4197 
4198 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
4199 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4200 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4201 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
4202 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
4203 
4204 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
4205 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4206 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4207 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
4208 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
4209 
4210 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
4211 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4212 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4213 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
4214 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
4215 
4216 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
4217 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4218 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4219 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
4220 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
4221 
4222 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
4223 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4224 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4225 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
4226 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
4227 
4228 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
4229 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4230 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4231 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
4232 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
4233 
4234 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
4235 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4236 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4237 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
4238 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
4239 
4240 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
4241 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4242 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4243 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
4244 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
4245 
4246 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
4247 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4248 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4249 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
4250 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
4251 
4252 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
4253 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4254 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4255 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
4256 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
4257 
4258 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
4259 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4260 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4261 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
4262 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
4263 
4264 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
4265 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4266 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4267 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
4268 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
4269 
4270 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
4271 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4272 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4273 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
4274 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
4275 
4276 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
4277 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4278 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4279 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
4280 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
4281 
4282 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
4283 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4284 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4285 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
4286 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
4287 
4288 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
4289 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4290 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4291 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
4292 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
4293 
4294 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
4295 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4296 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4297 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
4298 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
4299 
4300 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
4301 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4302 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4303 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
4304 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
4305 
4306 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
4307 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4308 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4309 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
4310 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
4311 
4312 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
4313 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4314 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4315 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
4316 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
4317 
4318 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
4319 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4320 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4321 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
4322 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
4323 
4324 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
4325 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4326 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4327 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
4328 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
4329 
4330 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
4331 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4332 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4333 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
4334 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
4335 
4336 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
4337 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4338 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4339 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
4340 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
4341 
4342 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
4343 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
4344 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
4345 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
4346 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
4347 
4348 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
4349 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
4350 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
4351 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
4352 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
4353 
4354 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
4355 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
4356 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
4357 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
4358 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
4359 
4360 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
4361 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4362 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
4363 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
4364 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
4365 
4366 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
4367 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
4368 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
4369 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
4370 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
4371 
4372 /* Register: GPIO_DETECTMODE */
4373 /* Description: Select between default DETECT signal behaviour and LDETECT mode (For non-secure pin only) */
4374 
4375 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
4376 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
4377 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
4378 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
4379 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
4380 
4381 /* Register: GPIO_DETECTMODE_SEC */
4382 /* Description: Select between default DETECT signal behaviour and LDETECT mode (For secure pin only) */
4383 
4384 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
4385 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
4386 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
4387 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
4388 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
4389 
4390 /* Register: GPIO_PIN_CNF */
4391 /* Description: Description collection: Configuration of GPIO pins */
4392 
4393 /* Bits 17..16 : Pin sensing mechanism */
4394 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
4395 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
4396 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
4397 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
4398 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
4399 
4400 /* Bits 10..8 : Drive configuration */
4401 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
4402 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
4403 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
4404 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
4405 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
4406 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
4407 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
4408 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
4409 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
4410 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
4411 
4412 /* Bits 3..2 : Pull configuration */
4413 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
4414 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
4415 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
4416 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
4417 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
4418 
4419 /* Bit 1 : Connect or disconnect input buffer */
4420 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
4421 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
4422 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
4423 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
4424 
4425 /* Bit 0 : Pin direction. Same physical register as DIR register */
4426 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
4427 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
4428 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
4429 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
4430 
4431 
4432 /* Peripheral: PDM */
4433 /* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */
4434 
4435 /* Register: PDM_TASKS_START */
4436 /* Description: Starts continuous PDM transfer */
4437 
4438 /* Bit 0 : Starts continuous PDM transfer */
4439 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
4440 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
4441 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
4442 
4443 /* Register: PDM_TASKS_STOP */
4444 /* Description: Stops PDM transfer */
4445 
4446 /* Bit 0 : Stops PDM transfer */
4447 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
4448 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
4449 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
4450 
4451 /* Register: PDM_SUBSCRIBE_START */
4452 /* Description: Subscribe configuration for task START */
4453 
4454 /* Bit 31 :   */
4455 #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
4456 #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
4457 #define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
4458 #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
4459 
4460 /* Bits 3..0 : Channel that task START will subscribe to */
4461 #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4462 #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4463 
4464 /* Register: PDM_SUBSCRIBE_STOP */
4465 /* Description: Subscribe configuration for task STOP */
4466 
4467 /* Bit 31 :   */
4468 #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
4469 #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
4470 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
4471 #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
4472 
4473 /* Bits 3..0 : Channel that task STOP will subscribe to */
4474 #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4475 #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4476 
4477 /* Register: PDM_EVENTS_STARTED */
4478 /* Description: PDM transfer has started */
4479 
4480 /* Bit 0 : PDM transfer has started */
4481 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
4482 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
4483 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
4484 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
4485 
4486 /* Register: PDM_EVENTS_STOPPED */
4487 /* Description: PDM transfer has finished */
4488 
4489 /* Bit 0 : PDM transfer has finished */
4490 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
4491 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
4492 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
4493 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
4494 
4495 /* Register: PDM_EVENTS_END */
4496 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
4497 
4498 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
4499 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
4500 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
4501 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
4502 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
4503 
4504 /* Register: PDM_PUBLISH_STARTED */
4505 /* Description: Publish configuration for event STARTED */
4506 
4507 /* Bit 31 :   */
4508 #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
4509 #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
4510 #define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
4511 #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
4512 
4513 /* Bits 3..0 : Channel that event STARTED will publish to. */
4514 #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4515 #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4516 
4517 /* Register: PDM_PUBLISH_STOPPED */
4518 /* Description: Publish configuration for event STOPPED */
4519 
4520 /* Bit 31 :   */
4521 #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
4522 #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
4523 #define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
4524 #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
4525 
4526 /* Bits 3..0 : Channel that event STOPPED will publish to. */
4527 #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4528 #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4529 
4530 /* Register: PDM_PUBLISH_END */
4531 /* Description: Publish configuration for event END */
4532 
4533 /* Bit 31 :   */
4534 #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
4535 #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
4536 #define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
4537 #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
4538 
4539 /* Bits 3..0 : Channel that event END will publish to. */
4540 #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4541 #define PDM_PUBLISH_END_CHIDX_Msk (0xFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4542 
4543 /* Register: PDM_INTEN */
4544 /* Description: Enable or disable interrupt */
4545 
4546 /* Bit 2 : Enable or disable interrupt for event END */
4547 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
4548 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
4549 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
4550 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
4551 
4552 /* Bit 1 : Enable or disable interrupt for event STOPPED */
4553 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4554 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4555 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
4556 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
4557 
4558 /* Bit 0 : Enable or disable interrupt for event STARTED */
4559 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4560 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4561 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4562 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4563 
4564 /* Register: PDM_INTENSET */
4565 /* Description: Enable interrupt */
4566 
4567 /* Bit 2 : Write '1' to enable interrupt for event END */
4568 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
4569 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
4570 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
4571 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
4572 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
4573 
4574 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
4575 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4576 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4577 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4578 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4579 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
4580 
4581 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
4582 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4583 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4584 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4585 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4586 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
4587 
4588 /* Register: PDM_INTENCLR */
4589 /* Description: Disable interrupt */
4590 
4591 /* Bit 2 : Write '1' to disable interrupt for event END */
4592 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
4593 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
4594 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
4595 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4596 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
4597 
4598 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
4599 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4600 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4601 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4602 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4603 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
4604 
4605 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
4606 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4607 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4608 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4609 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4610 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4611 
4612 /* Register: PDM_ENABLE */
4613 /* Description: PDM module enable register */
4614 
4615 /* Bit 0 : Enable or disable PDM module */
4616 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4617 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4618 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
4619 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4620 
4621 /* Register: PDM_PDMCLKCTRL */
4622 /* Description: PDM clock generator control */
4623 
4624 /* Bits 31..0 : PDM_CLK frequency */
4625 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
4626 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
4627 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
4628 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
4629 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
4630 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
4631 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
4632 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
4633 
4634 /* Register: PDM_MODE */
4635 /* Description: Defines the routing of the connected PDM microphones' signals */
4636 
4637 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
4638 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
4639 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
4640 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
4641 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
4642 
4643 /* Bit 0 : Mono or stereo operation */
4644 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
4645 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
4646 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
4647 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
4648 
4649 /* Register: PDM_GAINL */
4650 /* Description: Left output gain adjustment */
4651 
4652 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
4653 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
4654 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
4655 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
4656 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */
4657 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
4658 
4659 /* Register: PDM_GAINR */
4660 /* Description: Right output gain adjustment */
4661 
4662 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
4663 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
4664 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
4665 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
4666 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */
4667 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
4668 
4669 /* Register: PDM_RATIO */
4670 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
4671 
4672 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
4673 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
4674 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
4675 #define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
4676 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
4677 
4678 /* Register: PDM_PSEL_CLK */
4679 /* Description: Pin number configuration for PDM CLK signal */
4680 
4681 /* Bit 31 : Connection */
4682 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4683 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4684 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
4685 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4686 
4687 /* Bits 4..0 : Pin number */
4688 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
4689 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
4690 
4691 /* Register: PDM_PSEL_DIN */
4692 /* Description: Pin number configuration for PDM DIN signal */
4693 
4694 /* Bit 31 : Connection */
4695 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4696 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4697 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
4698 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
4699 
4700 /* Bits 4..0 : Pin number */
4701 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
4702 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
4703 
4704 /* Register: PDM_SAMPLE_PTR */
4705 /* Description: RAM address pointer to write samples to with EasyDMA */
4706 
4707 /* Bits 31..0 : Address to write PDM samples to over DMA */
4708 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
4709 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
4710 
4711 /* Register: PDM_SAMPLE_MAXCNT */
4712 /* Description: Number of samples to allocate memory for in EasyDMA mode */
4713 
4714 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
4715 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
4716 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
4717 
4718 
4719 /* Peripheral: POWER */
4720 /* Description: Power control 0 */
4721 
4722 /* Register: POWER_TASKS_CONSTLAT */
4723 /* Description: Enable constant latency mode. */
4724 
4725 /* Bit 0 : Enable constant latency mode. */
4726 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
4727 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
4728 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
4729 
4730 /* Register: POWER_TASKS_LOWPWR */
4731 /* Description: Enable low power mode (variable latency) */
4732 
4733 /* Bit 0 : Enable low power mode (variable latency) */
4734 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
4735 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
4736 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
4737 
4738 /* Register: POWER_SUBSCRIBE_CONSTLAT */
4739 /* Description: Subscribe configuration for task CONSTLAT */
4740 
4741 /* Bit 31 :   */
4742 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */
4743 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */
4744 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */
4745 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
4746 
4747 /* Bits 3..0 : Channel that task CONSTLAT will subscribe to */
4748 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4749 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4750 
4751 /* Register: POWER_SUBSCRIBE_LOWPWR */
4752 /* Description: Subscribe configuration for task LOWPWR */
4753 
4754 /* Bit 31 :   */
4755 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */
4756 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */
4757 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */
4758 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
4759 
4760 /* Bits 3..0 : Channel that task LOWPWR will subscribe to */
4761 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4762 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4763 
4764 /* Register: POWER_EVENTS_POFWARN */
4765 /* Description: Power failure warning */
4766 
4767 /* Bit 0 : Power failure warning */
4768 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
4769 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
4770 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
4771 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
4772 
4773 /* Register: POWER_EVENTS_SLEEPENTER */
4774 /* Description: CPU entered WFI/WFE sleep */
4775 
4776 /* Bit 0 : CPU entered WFI/WFE sleep */
4777 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
4778 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
4779 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
4780 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
4781 
4782 /* Register: POWER_EVENTS_SLEEPEXIT */
4783 /* Description: CPU exited WFI/WFE sleep */
4784 
4785 /* Bit 0 : CPU exited WFI/WFE sleep */
4786 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
4787 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
4788 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
4789 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
4790 
4791 /* Register: POWER_PUBLISH_POFWARN */
4792 /* Description: Publish configuration for event POFWARN */
4793 
4794 /* Bit 31 :   */
4795 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */
4796 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */
4797 #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */
4798 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
4799 
4800 /* Bits 3..0 : Channel that event POFWARN will publish to. */
4801 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4802 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4803 
4804 /* Register: POWER_PUBLISH_SLEEPENTER */
4805 /* Description: Publish configuration for event SLEEPENTER */
4806 
4807 /* Bit 31 :   */
4808 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */
4809 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */
4810 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */
4811 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
4812 
4813 /* Bits 3..0 : Channel that event SLEEPENTER will publish to. */
4814 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4815 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4816 
4817 /* Register: POWER_PUBLISH_SLEEPEXIT */
4818 /* Description: Publish configuration for event SLEEPEXIT */
4819 
4820 /* Bit 31 :   */
4821 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */
4822 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */
4823 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */
4824 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
4825 
4826 /* Bits 3..0 : Channel that event SLEEPEXIT will publish to. */
4827 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4828 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4829 
4830 /* Register: POWER_INTEN */
4831 /* Description: Enable or disable interrupt */
4832 
4833 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */
4834 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4835 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4836 #define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */
4837 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
4838 
4839 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */
4840 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4841 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4842 #define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */
4843 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
4844 
4845 /* Bit 2 : Enable or disable interrupt for event POFWARN */
4846 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4847 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4848 #define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */
4849 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
4850 
4851 /* Register: POWER_INTENSET */
4852 /* Description: Enable interrupt */
4853 
4854 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
4855 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4856 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4857 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4858 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4859 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
4860 
4861 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
4862 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4863 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4864 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4865 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4866 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
4867 
4868 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
4869 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4870 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4871 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4872 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4873 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
4874 
4875 /* Register: POWER_INTENCLR */
4876 /* Description: Disable interrupt */
4877 
4878 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
4879 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4880 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4881 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4882 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4883 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
4884 
4885 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
4886 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4887 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4888 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4889 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4890 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
4891 
4892 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
4893 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4894 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4895 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4896 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4897 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
4898 
4899 /* Register: POWER_RESETREAS */
4900 /* Description: Reset reason */
4901 
4902 /* Bit 18 : Reset triggered through CTRL-AP */
4903 #define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */
4904 #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */
4905 #define POWER_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */
4906 #define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */
4907 
4908 /* Bit 17 : Reset from CPU lock-up detected */
4909 #define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */
4910 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
4911 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
4912 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
4913 
4914 /* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */
4915 #define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */
4916 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
4917 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
4918 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
4919 
4920 /* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */
4921 #define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */
4922 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
4923 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
4924 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
4925 
4926 /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */
4927 #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */
4928 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
4929 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
4930 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
4931 
4932 /* Bit 1 : Reset from global watchdog detected */
4933 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
4934 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
4935 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
4936 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
4937 
4938 /* Bit 0 : Reset from pin reset detected */
4939 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
4940 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
4941 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
4942 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
4943 
4944 /* Register: POWER_POWERSTATUS */
4945 /* Description: Modem domain power status */
4946 
4947 /* Bit 0 : LTE modem domain status */
4948 #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */
4949 #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */
4950 #define POWER_POWERSTATUS_LTEMODEM_OFF (0UL) /*!< LTE modem domain is powered off */
4951 #define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */
4952 
4953 /* Register: POWER_GPREGRET */
4954 /* Description: Description collection: General purpose retention register */
4955 
4956 /* Bits 7..0 : General purpose retention register */
4957 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
4958 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
4959 
4960 
4961 /* Peripheral: PWM */
4962 /* Description: Pulse width modulation unit 0 */
4963 
4964 /* Register: PWM_TASKS_STOP */
4965 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
4966 
4967 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
4968 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
4969 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
4970 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
4971 
4972 /* Register: PWM_TASKS_SEQSTART */
4973 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
4974 
4975 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
4976 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
4977 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
4978 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
4979 
4980 /* Register: PWM_TASKS_NEXTSTEP */
4981 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
4982 
4983 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
4984 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
4985 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
4986 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
4987 
4988 /* Register: PWM_SUBSCRIBE_STOP */
4989 /* Description: Subscribe configuration for task STOP */
4990 
4991 /* Bit 31 :   */
4992 #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
4993 #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
4994 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
4995 #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
4996 
4997 /* Bits 3..0 : Channel that task STOP will subscribe to */
4998 #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4999 #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5000 
5001 /* Register: PWM_SUBSCRIBE_SEQSTART */
5002 /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */
5003 
5004 /* Bit 31 :   */
5005 #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */
5006 #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */
5007 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */
5008 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
5009 
5010 /* Bits 3..0 : Channel that task SEQSTART[n] will subscribe to */
5011 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5012 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5013 
5014 /* Register: PWM_SUBSCRIBE_NEXTSTEP */
5015 /* Description: Subscribe configuration for task NEXTSTEP */
5016 
5017 /* Bit 31 :   */
5018 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */
5019 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */
5020 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */
5021 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
5022 
5023 /* Bits 3..0 : Channel that task NEXTSTEP will subscribe to */
5024 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5025 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5026 
5027 /* Register: PWM_EVENTS_STOPPED */
5028 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
5029 
5030 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
5031 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
5032 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
5033 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
5034 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
5035 
5036 /* Register: PWM_EVENTS_SEQSTARTED */
5037 /* Description: Description collection: First PWM period started on sequence n */
5038 
5039 /* Bit 0 : First PWM period started on sequence n */
5040 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
5041 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
5042 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
5043 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
5044 
5045 /* Register: PWM_EVENTS_SEQEND */
5046 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
5047 
5048 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
5049 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
5050 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
5051 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
5052 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
5053 
5054 /* Register: PWM_EVENTS_PWMPERIODEND */
5055 /* Description: Emitted at the end of each PWM period */
5056 
5057 /* Bit 0 : Emitted at the end of each PWM period */
5058 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
5059 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
5060 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
5061 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
5062 
5063 /* Register: PWM_EVENTS_LOOPSDONE */
5064 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5065 
5066 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5067 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
5068 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
5069 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
5070 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
5071 
5072 /* Register: PWM_PUBLISH_STOPPED */
5073 /* Description: Publish configuration for event STOPPED */
5074 
5075 /* Bit 31 :   */
5076 #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
5077 #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
5078 #define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
5079 #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
5080 
5081 /* Bits 3..0 : Channel that event STOPPED will publish to. */
5082 #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5083 #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5084 
5085 /* Register: PWM_PUBLISH_SEQSTARTED */
5086 /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */
5087 
5088 /* Bit 31 :   */
5089 #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
5090 #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */
5091 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
5092 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
5093 
5094 /* Bits 3..0 : Channel that event SEQSTARTED[n] will publish to. */
5095 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5096 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5097 
5098 /* Register: PWM_PUBLISH_SEQEND */
5099 /* Description: Description collection: Publish configuration for event SEQEND[n] */
5100 
5101 /* Bit 31 :   */
5102 #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */
5103 #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */
5104 #define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */
5105 #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
5106 
5107 /* Bits 3..0 : Channel that event SEQEND[n] will publish to. */
5108 #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5109 #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5110 
5111 /* Register: PWM_PUBLISH_PWMPERIODEND */
5112 /* Description: Publish configuration for event PWMPERIODEND */
5113 
5114 /* Bit 31 :   */
5115 #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */
5116 #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */
5117 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */
5118 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
5119 
5120 /* Bits 3..0 : Channel that event PWMPERIODEND will publish to. */
5121 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5122 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5123 
5124 /* Register: PWM_PUBLISH_LOOPSDONE */
5125 /* Description: Publish configuration for event LOOPSDONE */
5126 
5127 /* Bit 31 :   */
5128 #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */
5129 #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */
5130 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */
5131 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
5132 
5133 /* Bits 3..0 : Channel that event LOOPSDONE will publish to. */
5134 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5135 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5136 
5137 /* Register: PWM_SHORTS */
5138 /* Description: Shortcuts between local events and tasks */
5139 
5140 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
5141 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
5142 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
5143 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
5144 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
5145 
5146 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
5147 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
5148 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
5149 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
5150 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
5151 
5152 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
5153 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
5154 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
5155 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
5156 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
5157 
5158 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
5159 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
5160 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
5161 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
5162 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
5163 
5164 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
5165 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
5166 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
5167 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
5168 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
5169 
5170 /* Register: PWM_INTEN */
5171 /* Description: Enable or disable interrupt */
5172 
5173 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
5174 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5175 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5176 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
5177 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
5178 
5179 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
5180 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5181 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5182 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
5183 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
5184 
5185 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
5186 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5187 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5188 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
5189 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
5190 
5191 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
5192 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5193 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5194 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
5195 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
5196 
5197 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
5198 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5199 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5200 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
5201 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
5202 
5203 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
5204 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5205 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5206 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
5207 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
5208 
5209 /* Bit 1 : Enable or disable interrupt for event STOPPED */
5210 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5211 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5212 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
5213 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
5214 
5215 /* Register: PWM_INTENSET */
5216 /* Description: Enable interrupt */
5217 
5218 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
5219 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5220 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5221 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5222 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5223 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
5224 
5225 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
5226 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5227 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5228 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5229 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5230 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
5231 
5232 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
5233 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5234 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5235 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5236 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5237 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
5238 
5239 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
5240 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5241 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5242 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5243 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5244 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
5245 
5246 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
5247 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5248 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5249 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5250 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5251 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
5252 
5253 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
5254 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5255 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5256 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5257 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5258 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
5259 
5260 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
5261 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5262 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5263 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5264 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5265 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5266 
5267 /* Register: PWM_INTENCLR */
5268 /* Description: Disable interrupt */
5269 
5270 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
5271 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5272 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5273 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5274 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5275 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
5276 
5277 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
5278 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5279 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5280 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5281 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5282 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
5283 
5284 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
5285 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5286 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5287 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5288 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5289 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
5290 
5291 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
5292 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5293 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5294 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5295 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5296 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
5297 
5298 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
5299 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5300 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5301 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5302 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5303 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
5304 
5305 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
5306 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5307 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5308 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5309 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5310 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
5311 
5312 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
5313 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5314 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5315 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5316 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5317 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5318 
5319 /* Register: PWM_ENABLE */
5320 /* Description: PWM module enable register */
5321 
5322 /* Bit 0 : Enable or disable PWM module */
5323 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5324 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5325 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
5326 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5327 
5328 /* Register: PWM_MODE */
5329 /* Description: Selects operating mode of the wave counter */
5330 
5331 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
5332 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
5333 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
5334 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
5335 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
5336 
5337 /* Register: PWM_COUNTERTOP */
5338 /* Description: Value up to which the pulse generator counter counts */
5339 
5340 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
5341 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
5342 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
5343 
5344 /* Register: PWM_PRESCALER */
5345 /* Description: Configuration for PWM_CLK */
5346 
5347 /* Bits 2..0 : Prescaler of PWM_CLK */
5348 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5349 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5350 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
5351 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
5352 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
5353 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
5354 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
5355 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
5356 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
5357 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
5358 
5359 /* Register: PWM_DECODER */
5360 /* Description: Configuration of the decoder */
5361 
5362 /* Bit 8 : Selects source for advancing the active sequence */
5363 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
5364 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
5365 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
5366 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
5367 
5368 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5369 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
5370 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
5371 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
5372 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
5373 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
5374 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
5375 
5376 /* Register: PWM_LOOP */
5377 /* Description: Number of playbacks of a loop */
5378 
5379 /* Bits 15..0 : Number of playbacks of pattern cycles */
5380 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
5381 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
5382 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
5383 
5384 /* Register: PWM_SEQ_PTR */
5385 /* Description: Description cluster: Beginning address in RAM of this sequence */
5386 
5387 /* Bits 31..0 : Beginning address in RAM of this sequence */
5388 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
5389 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
5390 
5391 /* Register: PWM_SEQ_CNT */
5392 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
5393 
5394 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
5395 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
5396 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
5397 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
5398 
5399 /* Register: PWM_SEQ_REFRESH */
5400 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
5401 
5402 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
5403 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
5404 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
5405 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
5406 
5407 /* Register: PWM_SEQ_ENDDELAY */
5408 /* Description: Description cluster: Time added after the sequence */
5409 
5410 /* Bits 23..0 : Time added after the sequence in PWM periods */
5411 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
5412 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
5413 
5414 /* Register: PWM_PSEL_OUT */
5415 /* Description: Description collection: Output pin select for PWM channel n */
5416 
5417 /* Bit 31 : Connection */
5418 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5419 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5420 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
5421 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
5422 
5423 /* Bits 4..0 : Pin number */
5424 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
5425 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
5426 
5427 
5428 /* Peripheral: REGULATORS */
5429 /* Description: Voltage regulators control 0 */
5430 
5431 /* Register: REGULATORS_SYSTEMOFF */
5432 /* Description: System OFF register */
5433 
5434 /* Bit 0 : Enable System OFF mode */
5435 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
5436 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
5437 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
5438 
5439 /* Register: REGULATORS_POFCON */
5440 /* Description: Power-fail comparator configuration */
5441 
5442 /* Bits 4..1 : Power-fail comparator threshold setting */
5443 #define REGULATORS_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
5444 #define REGULATORS_POFCON_THRESHOLD_Msk (0xFUL << REGULATORS_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
5445 #define REGULATORS_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
5446 #define REGULATORS_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
5447 #define REGULATORS_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
5448 #define REGULATORS_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
5449 #define REGULATORS_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
5450 #define REGULATORS_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
5451 #define REGULATORS_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
5452 #define REGULATORS_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
5453 #define REGULATORS_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
5454 #define REGULATORS_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
5455 
5456 /* Bit 0 : Enable or disable power-fail comparator */
5457 #define REGULATORS_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
5458 #define REGULATORS_POFCON_POF_Msk (0x1UL << REGULATORS_POFCON_POF_Pos) /*!< Bit mask of POF field. */
5459 #define REGULATORS_POFCON_POF_Disabled (0UL) /*!< Disable */
5460 #define REGULATORS_POFCON_POF_Enabled (1UL) /*!< Enable */
5461 
5462 /* Register: REGULATORS_DCDCEN */
5463 /* Description: Enable DC/DC mode of the main voltage regulator */
5464 
5465 /* Bit 0 : Enable DC/DC converter */
5466 #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
5467 #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
5468 #define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */
5469 #define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */
5470 
5471 
5472 /* Peripheral: RTC */
5473 /* Description: Real-time counter 0 */
5474 
5475 /* Register: RTC_TASKS_START */
5476 /* Description: Start RTC counter */
5477 
5478 /* Bit 0 : Start RTC counter */
5479 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5480 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5481 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5482 
5483 /* Register: RTC_TASKS_STOP */
5484 /* Description: Stop RTC counter */
5485 
5486 /* Bit 0 : Stop RTC counter */
5487 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5488 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5489 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5490 
5491 /* Register: RTC_TASKS_CLEAR */
5492 /* Description: Clear RTC counter */
5493 
5494 /* Bit 0 : Clear RTC counter */
5495 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
5496 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
5497 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
5498 
5499 /* Register: RTC_TASKS_TRIGOVRFLW */
5500 /* Description: Set counter to 0xFFFFF0 */
5501 
5502 /* Bit 0 : Set counter to 0xFFFFF0 */
5503 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
5504 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
5505 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
5506 
5507 /* Register: RTC_SUBSCRIBE_START */
5508 /* Description: Subscribe configuration for task START */
5509 
5510 /* Bit 31 :   */
5511 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5512 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5513 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5514 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5515 
5516 /* Bits 3..0 : Channel that task START will subscribe to */
5517 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5518 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5519 
5520 /* Register: RTC_SUBSCRIBE_STOP */
5521 /* Description: Subscribe configuration for task STOP */
5522 
5523 /* Bit 31 :   */
5524 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5525 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5526 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5527 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5528 
5529 /* Bits 3..0 : Channel that task STOP will subscribe to */
5530 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5531 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5532 
5533 /* Register: RTC_SUBSCRIBE_CLEAR */
5534 /* Description: Subscribe configuration for task CLEAR */
5535 
5536 /* Bit 31 :   */
5537 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
5538 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
5539 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
5540 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
5541 
5542 /* Bits 3..0 : Channel that task CLEAR will subscribe to */
5543 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5544 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5545 
5546 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
5547 /* Description: Subscribe configuration for task TRIGOVRFLW */
5548 
5549 /* Bit 31 :   */
5550 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
5551 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
5552 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
5553 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
5554 
5555 /* Bits 3..0 : Channel that task TRIGOVRFLW will subscribe to */
5556 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5557 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5558 
5559 /* Register: RTC_EVENTS_TICK */
5560 /* Description: Event on counter increment */
5561 
5562 /* Bit 0 : Event on counter increment */
5563 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
5564 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
5565 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
5566 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
5567 
5568 /* Register: RTC_EVENTS_OVRFLW */
5569 /* Description: Event on counter overflow */
5570 
5571 /* Bit 0 : Event on counter overflow */
5572 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
5573 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
5574 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
5575 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
5576 
5577 /* Register: RTC_EVENTS_COMPARE */
5578 /* Description: Description collection: Compare event on CC[n] match */
5579 
5580 /* Bit 0 : Compare event on CC[n] match */
5581 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
5582 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
5583 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
5584 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
5585 
5586 /* Register: RTC_PUBLISH_TICK */
5587 /* Description: Publish configuration for event TICK */
5588 
5589 /* Bit 31 :   */
5590 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
5591 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
5592 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
5593 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
5594 
5595 /* Bits 3..0 : Channel that event TICK will publish to. */
5596 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5597 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5598 
5599 /* Register: RTC_PUBLISH_OVRFLW */
5600 /* Description: Publish configuration for event OVRFLW */
5601 
5602 /* Bit 31 :   */
5603 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
5604 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
5605 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
5606 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
5607 
5608 /* Bits 3..0 : Channel that event OVRFLW will publish to. */
5609 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5610 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5611 
5612 /* Register: RTC_PUBLISH_COMPARE */
5613 /* Description: Description collection: Publish configuration for event COMPARE[n] */
5614 
5615 /* Bit 31 :   */
5616 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
5617 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
5618 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
5619 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
5620 
5621 /* Bits 3..0 : Channel that event COMPARE[n] will publish to. */
5622 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5623 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5624 
5625 /* Register: RTC_INTENSET */
5626 /* Description: Enable interrupt */
5627 
5628 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
5629 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5630 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5631 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5632 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5633 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
5634 
5635 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
5636 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5637 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5638 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5639 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5640 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
5641 
5642 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
5643 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5644 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5645 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5646 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5647 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
5648 
5649 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
5650 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5651 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5652 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5653 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5654 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
5655 
5656 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
5657 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5658 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5659 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5660 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5661 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
5662 
5663 /* Bit 0 : Write '1' to enable interrupt for event TICK */
5664 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
5665 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
5666 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5667 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5668 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
5669 
5670 /* Register: RTC_INTENCLR */
5671 /* Description: Disable interrupt */
5672 
5673 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
5674 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5675 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5676 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5677 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5678 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5679 
5680 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
5681 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5682 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5683 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5684 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5685 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5686 
5687 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
5688 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5689 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5690 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5691 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5692 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5693 
5694 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
5695 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5696 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5697 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5698 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5699 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5700 
5701 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
5702 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5703 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5704 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5705 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5706 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5707 
5708 /* Bit 0 : Write '1' to disable interrupt for event TICK */
5709 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
5710 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
5711 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5712 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5713 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
5714 
5715 /* Register: RTC_EVTEN */
5716 /* Description: Enable or disable event routing */
5717 
5718 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
5719 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5720 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5721 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
5722 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
5723 
5724 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
5725 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5726 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5727 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
5728 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
5729 
5730 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
5731 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5732 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5733 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
5734 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
5735 
5736 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
5737 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5738 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5739 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
5740 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
5741 
5742 /* Bit 1 : Enable or disable event routing for event OVRFLW */
5743 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5744 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5745 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
5746 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
5747 
5748 /* Bit 0 : Enable or disable event routing for event TICK */
5749 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
5750 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
5751 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
5752 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
5753 
5754 /* Register: RTC_EVTENSET */
5755 /* Description: Enable event routing */
5756 
5757 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
5758 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5759 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5760 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5761 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5762 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
5763 
5764 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
5765 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5766 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5767 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5768 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5769 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
5770 
5771 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
5772 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5773 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5774 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5775 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5776 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
5777 
5778 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
5779 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5780 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5781 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5782 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5783 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
5784 
5785 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
5786 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5787 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5788 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5789 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5790 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
5791 
5792 /* Bit 0 : Write '1' to enable event routing for event TICK */
5793 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
5794 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
5795 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5796 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5797 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
5798 
5799 /* Register: RTC_EVTENCLR */
5800 /* Description: Disable event routing */
5801 
5802 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
5803 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5804 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5805 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5806 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5807 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5808 
5809 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
5810 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
5811 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
5812 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5813 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5814 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5815 
5816 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
5817 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
5818 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
5819 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5820 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5821 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5822 
5823 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
5824 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5825 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5826 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5827 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5828 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5829 
5830 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
5831 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5832 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5833 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5834 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5835 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5836 
5837 /* Bit 0 : Write '1' to disable event routing for event TICK */
5838 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
5839 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
5840 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5841 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5842 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
5843 
5844 /* Register: RTC_COUNTER */
5845 /* Description: Current counter value */
5846 
5847 /* Bits 23..0 : Counter value */
5848 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
5849 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
5850 
5851 /* Register: RTC_PRESCALER */
5852 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */
5853 
5854 /* Bits 11..0 : Prescaler value */
5855 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5856 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5857 
5858 /* Register: RTC_CC */
5859 /* Description: Description collection: Compare register n */
5860 
5861 /* Bits 23..0 : Compare value */
5862 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
5863 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
5864 
5865 
5866 /* Peripheral: SAADC */
5867 /* Description: Analog to Digital Converter 0 */
5868 
5869 /* Register: SAADC_TASKS_START */
5870 /* Description: Start the ADC and prepare the result buffer in RAM */
5871 
5872 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */
5873 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5874 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5875 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5876 
5877 /* Register: SAADC_TASKS_SAMPLE */
5878 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
5879 
5880 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
5881 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
5882 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
5883 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
5884 
5885 /* Register: SAADC_TASKS_STOP */
5886 /* Description: Stop the ADC and terminate any on-going conversion */
5887 
5888 /* Bit 0 : Stop the ADC and terminate any on-going conversion */
5889 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5890 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5891 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5892 
5893 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
5894 /* Description: Starts offset auto-calibration */
5895 
5896 /* Bit 0 : Starts offset auto-calibration */
5897 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
5898 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
5899 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
5900 
5901 /* Register: SAADC_SUBSCRIBE_START */
5902 /* Description: Subscribe configuration for task START */
5903 
5904 /* Bit 31 :   */
5905 #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5906 #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5907 #define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5908 #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5909 
5910 /* Bits 3..0 : Channel that task START will subscribe to */
5911 #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5912 #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5913 
5914 /* Register: SAADC_SUBSCRIBE_SAMPLE */
5915 /* Description: Subscribe configuration for task SAMPLE */
5916 
5917 /* Bit 31 :   */
5918 #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */
5919 #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */
5920 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */
5921 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
5922 
5923 /* Bits 3..0 : Channel that task SAMPLE will subscribe to */
5924 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5925 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5926 
5927 /* Register: SAADC_SUBSCRIBE_STOP */
5928 /* Description: Subscribe configuration for task STOP */
5929 
5930 /* Bit 31 :   */
5931 #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5932 #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5933 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5934 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5935 
5936 /* Bits 3..0 : Channel that task STOP will subscribe to */
5937 #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5938 #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5939 
5940 /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */
5941 /* Description: Subscribe configuration for task CALIBRATEOFFSET */
5942 
5943 /* Bit 31 :   */
5944 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */
5945 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */
5946 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */
5947 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
5948 
5949 /* Bits 3..0 : Channel that task CALIBRATEOFFSET will subscribe to */
5950 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5951 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5952 
5953 /* Register: SAADC_EVENTS_STARTED */
5954 /* Description: The ADC has started */
5955 
5956 /* Bit 0 : The ADC has started */
5957 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
5958 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
5959 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
5960 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
5961 
5962 /* Register: SAADC_EVENTS_END */
5963 /* Description: The ADC has filled up the Result buffer */
5964 
5965 /* Bit 0 : The ADC has filled up the Result buffer */
5966 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
5967 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
5968 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
5969 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
5970 
5971 /* Register: SAADC_EVENTS_DONE */
5972 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
5973 
5974 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
5975 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
5976 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
5977 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
5978 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
5979 
5980 /* Register: SAADC_EVENTS_RESULTDONE */
5981 /* Description: A result is ready to get transferred to RAM. */
5982 
5983 /* Bit 0 : A result is ready to get transferred to RAM. */
5984 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
5985 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
5986 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
5987 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
5988 
5989 /* Register: SAADC_EVENTS_CALIBRATEDONE */
5990 /* Description: Calibration is complete */
5991 
5992 /* Bit 0 : Calibration is complete */
5993 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
5994 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
5995 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
5996 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
5997 
5998 /* Register: SAADC_EVENTS_STOPPED */
5999 /* Description: The ADC has stopped */
6000 
6001 /* Bit 0 : The ADC has stopped */
6002 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6003 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6004 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
6005 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6006 
6007 /* Register: SAADC_EVENTS_CH_LIMITH */
6008 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
6009 
6010 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
6011 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
6012 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
6013 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
6014 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
6015 
6016 /* Register: SAADC_EVENTS_CH_LIMITL */
6017 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
6018 
6019 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
6020 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
6021 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
6022 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
6023 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
6024 
6025 /* Register: SAADC_PUBLISH_STARTED */
6026 /* Description: Publish configuration for event STARTED */
6027 
6028 /* Bit 31 :   */
6029 #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
6030 #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
6031 #define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
6032 #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6033 
6034 /* Bits 3..0 : Channel that event STARTED will publish to. */
6035 #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6036 #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6037 
6038 /* Register: SAADC_PUBLISH_END */
6039 /* Description: Publish configuration for event END */
6040 
6041 /* Bit 31 :   */
6042 #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
6043 #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
6044 #define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6045 #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6046 
6047 /* Bits 3..0 : Channel that event END will publish to. */
6048 #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6049 #define SAADC_PUBLISH_END_CHIDX_Msk (0xFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6050 
6051 /* Register: SAADC_PUBLISH_DONE */
6052 /* Description: Publish configuration for event DONE */
6053 
6054 /* Bit 31 :   */
6055 #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
6056 #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
6057 #define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
6058 #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
6059 
6060 /* Bits 3..0 : Channel that event DONE will publish to. */
6061 #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6062 #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6063 
6064 /* Register: SAADC_PUBLISH_RESULTDONE */
6065 /* Description: Publish configuration for event RESULTDONE */
6066 
6067 /* Bit 31 :   */
6068 #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */
6069 #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */
6070 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */
6071 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
6072 
6073 /* Bits 3..0 : Channel that event RESULTDONE will publish to. */
6074 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6075 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6076 
6077 /* Register: SAADC_PUBLISH_CALIBRATEDONE */
6078 /* Description: Publish configuration for event CALIBRATEDONE */
6079 
6080 /* Bit 31 :   */
6081 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */
6082 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */
6083 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */
6084 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
6085 
6086 /* Bits 3..0 : Channel that event CALIBRATEDONE will publish to. */
6087 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6088 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6089 
6090 /* Register: SAADC_PUBLISH_STOPPED */
6091 /* Description: Publish configuration for event STOPPED */
6092 
6093 /* Bit 31 :   */
6094 #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6095 #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
6096 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6097 #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6098 
6099 /* Bits 3..0 : Channel that event STOPPED will publish to. */
6100 #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6101 #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6102 
6103 /* Register: SAADC_PUBLISH_CH_LIMITH */
6104 /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */
6105 
6106 /* Bit 31 :   */
6107 #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */
6108 #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */
6109 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */
6110 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
6111 
6112 /* Bits 3..0 : Channel that event CH[n].LIMITH will publish to. */
6113 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6114 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6115 
6116 /* Register: SAADC_PUBLISH_CH_LIMITL */
6117 /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */
6118 
6119 /* Bit 31 :   */
6120 #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */
6121 #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */
6122 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */
6123 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
6124 
6125 /* Bits 3..0 : Channel that event CH[n].LIMITL will publish to. */
6126 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6127 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6128 
6129 /* Register: SAADC_INTEN */
6130 /* Description: Enable or disable interrupt */
6131 
6132 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
6133 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
6134 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
6135 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
6136 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
6137 
6138 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
6139 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
6140 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
6141 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
6142 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
6143 
6144 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
6145 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
6146 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
6147 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
6148 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
6149 
6150 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
6151 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
6152 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
6153 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
6154 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
6155 
6156 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
6157 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
6158 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
6159 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
6160 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
6161 
6162 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
6163 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
6164 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
6165 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
6166 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
6167 
6168 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
6169 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
6170 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
6171 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
6172 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
6173 
6174 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
6175 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
6176 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
6177 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
6178 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
6179 
6180 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
6181 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
6182 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
6183 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
6184 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
6185 
6186 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
6187 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
6188 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
6189 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
6190 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
6191 
6192 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
6193 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
6194 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
6195 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
6196 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
6197 
6198 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
6199 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
6200 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
6201 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
6202 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
6203 
6204 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
6205 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
6206 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
6207 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
6208 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
6209 
6210 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
6211 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
6212 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
6213 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
6214 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
6215 
6216 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
6217 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
6218 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
6219 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
6220 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
6221 
6222 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
6223 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
6224 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
6225 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
6226 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
6227 
6228 /* Bit 5 : Enable or disable interrupt for event STOPPED */
6229 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
6230 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6231 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6232 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6233 
6234 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
6235 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
6236 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
6237 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
6238 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
6239 
6240 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
6241 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
6242 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
6243 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
6244 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
6245 
6246 /* Bit 2 : Enable or disable interrupt for event DONE */
6247 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
6248 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
6249 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
6250 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
6251 
6252 /* Bit 1 : Enable or disable interrupt for event END */
6253 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
6254 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
6255 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
6256 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
6257 
6258 /* Bit 0 : Enable or disable interrupt for event STARTED */
6259 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6260 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6261 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6262 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6263 
6264 /* Register: SAADC_INTENSET */
6265 /* Description: Enable interrupt */
6266 
6267 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
6268 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
6269 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
6270 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6271 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6272 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
6273 
6274 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
6275 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
6276 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
6277 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6278 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6279 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
6280 
6281 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
6282 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
6283 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
6284 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6285 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6286 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
6287 
6288 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
6289 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
6290 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
6291 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6292 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6293 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
6294 
6295 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
6296 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
6297 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
6298 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6299 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6300 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
6301 
6302 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
6303 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
6304 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
6305 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6306 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6307 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
6308 
6309 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
6310 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
6311 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
6312 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6313 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6314 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
6315 
6316 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
6317 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
6318 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
6319 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6320 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6321 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
6322 
6323 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
6324 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
6325 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
6326 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6327 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6328 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
6329 
6330 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
6331 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
6332 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
6333 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6334 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6335 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
6336 
6337 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
6338 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
6339 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
6340 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6341 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6342 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
6343 
6344 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
6345 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
6346 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
6347 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6348 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6349 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
6350 
6351 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
6352 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
6353 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
6354 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6355 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6356 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
6357 
6358 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
6359 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
6360 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
6361 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6362 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6363 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
6364 
6365 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
6366 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
6367 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
6368 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6369 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6370 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
6371 
6372 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
6373 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
6374 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
6375 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6376 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6377 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
6378 
6379 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
6380 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
6381 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6382 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6383 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6384 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6385 
6386 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
6387 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
6388 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
6389 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6390 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6391 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
6392 
6393 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
6394 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
6395 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
6396 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6397 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6398 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
6399 
6400 /* Bit 2 : Write '1' to enable interrupt for event DONE */
6401 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
6402 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
6403 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
6404 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
6405 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
6406 
6407 /* Bit 1 : Write '1' to enable interrupt for event END */
6408 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
6409 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
6410 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6411 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6412 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
6413 
6414 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
6415 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6416 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6417 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6418 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6419 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
6420 
6421 /* Register: SAADC_INTENCLR */
6422 /* Description: Disable interrupt */
6423 
6424 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
6425 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
6426 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
6427 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6428 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6429 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
6430 
6431 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
6432 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
6433 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
6434 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6435 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6436 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
6437 
6438 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
6439 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
6440 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
6441 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6442 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6443 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
6444 
6445 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
6446 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
6447 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
6448 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6449 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6450 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
6451 
6452 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
6453 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
6454 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
6455 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6456 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6457 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
6458 
6459 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
6460 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
6461 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
6462 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6463 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6464 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
6465 
6466 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
6467 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
6468 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
6469 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6470 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6471 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
6472 
6473 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
6474 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
6475 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
6476 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6477 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6478 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
6479 
6480 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
6481 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
6482 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
6483 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6484 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6485 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
6486 
6487 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
6488 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
6489 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
6490 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6491 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6492 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
6493 
6494 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
6495 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
6496 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
6497 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6498 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6499 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
6500 
6501 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
6502 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
6503 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
6504 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6505 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6506 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
6507 
6508 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
6509 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
6510 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
6511 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6512 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6513 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
6514 
6515 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
6516 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
6517 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
6518 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6519 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6520 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
6521 
6522 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
6523 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
6524 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
6525 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6526 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6527 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
6528 
6529 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
6530 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
6531 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
6532 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6533 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6534 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
6535 
6536 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
6537 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
6538 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6539 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6540 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6541 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6542 
6543 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
6544 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
6545 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
6546 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6547 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6548 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
6549 
6550 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
6551 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
6552 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
6553 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6554 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6555 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
6556 
6557 /* Bit 2 : Write '1' to disable interrupt for event DONE */
6558 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
6559 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
6560 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
6561 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
6562 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
6563 
6564 /* Bit 1 : Write '1' to disable interrupt for event END */
6565 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
6566 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6567 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6568 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6569 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
6570 
6571 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
6572 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6573 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6574 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6575 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6576 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6577 
6578 /* Register: SAADC_STATUS */
6579 /* Description: Status */
6580 
6581 /* Bit 0 : Status */
6582 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
6583 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
6584 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
6585 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
6586 
6587 /* Register: SAADC_ENABLE */
6588 /* Description: Enable or disable ADC */
6589 
6590 /* Bit 0 : Enable or disable ADC */
6591 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6592 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6593 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
6594 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
6595 
6596 /* Register: SAADC_CH_PSELP */
6597 /* Description: Description cluster: Input positive pin selection for CH[n] */
6598 
6599 /* Bits 4..0 : Analog positive input channel */
6600 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
6601 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
6602 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
6603 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
6604 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
6605 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
6606 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
6607 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
6608 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
6609 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
6610 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
6611 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
6612 
6613 /* Register: SAADC_CH_PSELN */
6614 /* Description: Description cluster: Input negative pin selection for CH[n] */
6615 
6616 /* Bits 4..0 : Analog negative input, enables differential channel */
6617 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
6618 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
6619 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
6620 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
6621 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
6622 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
6623 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
6624 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
6625 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
6626 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
6627 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
6628 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
6629 
6630 /* Register: SAADC_CH_CONFIG */
6631 /* Description: Description cluster: Input configuration for CH[n] */
6632 
6633 /* Bit 24 : Enable burst mode */
6634 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
6635 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
6636 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
6637 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
6638 
6639 /* Bit 20 : Enable differential mode */
6640 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
6641 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
6642 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
6643 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
6644 
6645 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
6646 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
6647 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
6648 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
6649 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
6650 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
6651 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
6652 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
6653 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
6654 
6655 /* Bit 12 : Reference control */
6656 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
6657 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
6658 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
6659 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
6660 
6661 /* Bits 10..8 : Gain control */
6662 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
6663 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
6664 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
6665 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
6666 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
6667 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
6668 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
6669 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
6670 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
6671 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
6672 
6673 /* Bits 5..4 : Negative channel resistor control */
6674 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
6675 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
6676 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
6677 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
6678 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
6679 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
6680 
6681 /* Bits 1..0 : Positive channel resistor control */
6682 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
6683 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
6684 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
6685 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
6686 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
6687 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
6688 
6689 /* Register: SAADC_CH_LIMIT */
6690 /* Description: Description cluster: High/low limits for event monitoring a channel */
6691 
6692 /* Bits 31..16 : High level limit */
6693 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
6694 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
6695 
6696 /* Bits 15..0 : Low level limit */
6697 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
6698 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
6699 
6700 /* Register: SAADC_RESOLUTION */
6701 /* Description: Resolution configuration */
6702 
6703 /* Bits 2..0 : Set the resolution */
6704 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
6705 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
6706 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
6707 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
6708 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
6709 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
6710 
6711 /* Register: SAADC_OVERSAMPLE */
6712 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
6713 
6714 /* Bits 3..0 : Oversample control */
6715 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
6716 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
6717 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
6718 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
6719 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
6720 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
6721 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
6722 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
6723 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
6724 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
6725 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
6726 
6727 /* Register: SAADC_SAMPLERATE */
6728 /* Description: Controls normal or continuous sample rate */
6729 
6730 /* Bit 12 : Select mode for sample rate control */
6731 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
6732 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
6733 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
6734 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
6735 
6736 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
6737 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
6738 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
6739 
6740 /* Register: SAADC_RESULT_PTR */
6741 /* Description: Data pointer */
6742 
6743 /* Bits 31..0 : Data pointer */
6744 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6745 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6746 
6747 /* Register: SAADC_RESULT_MAXCNT */
6748 /* Description: Maximum number of buffer words to transfer */
6749 
6750 /* Bits 14..0 : Maximum number of buffer words to transfer */
6751 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
6752 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
6753 
6754 /* Register: SAADC_RESULT_AMOUNT */
6755 /* Description: Number of buffer words transferred since last START */
6756 
6757 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
6758 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
6759 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
6760 
6761 
6762 /* Peripheral: SPIM */
6763 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
6764 
6765 /* Register: SPIM_TASKS_START */
6766 /* Description: Start SPI transaction */
6767 
6768 /* Bit 0 : Start SPI transaction */
6769 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6770 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6771 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6772 
6773 /* Register: SPIM_TASKS_STOP */
6774 /* Description: Stop SPI transaction */
6775 
6776 /* Bit 0 : Stop SPI transaction */
6777 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6778 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6779 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6780 
6781 /* Register: SPIM_TASKS_SUSPEND */
6782 /* Description: Suspend SPI transaction */
6783 
6784 /* Bit 0 : Suspend SPI transaction */
6785 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
6786 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
6787 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
6788 
6789 /* Register: SPIM_TASKS_RESUME */
6790 /* Description: Resume SPI transaction */
6791 
6792 /* Bit 0 : Resume SPI transaction */
6793 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
6794 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
6795 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
6796 
6797 /* Register: SPIM_SUBSCRIBE_START */
6798 /* Description: Subscribe configuration for task START */
6799 
6800 /* Bit 31 :   */
6801 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
6802 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
6803 #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
6804 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
6805 
6806 /* Bits 3..0 : Channel that task START will subscribe to */
6807 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6808 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6809 
6810 /* Register: SPIM_SUBSCRIBE_STOP */
6811 /* Description: Subscribe configuration for task STOP */
6812 
6813 /* Bit 31 :   */
6814 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
6815 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
6816 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
6817 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
6818 
6819 /* Bits 3..0 : Channel that task STOP will subscribe to */
6820 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6821 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6822 
6823 /* Register: SPIM_SUBSCRIBE_SUSPEND */
6824 /* Description: Subscribe configuration for task SUSPEND */
6825 
6826 /* Bit 31 :   */
6827 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
6828 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
6829 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
6830 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
6831 
6832 /* Bits 3..0 : Channel that task SUSPEND will subscribe to */
6833 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6834 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6835 
6836 /* Register: SPIM_SUBSCRIBE_RESUME */
6837 /* Description: Subscribe configuration for task RESUME */
6838 
6839 /* Bit 31 :   */
6840 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
6841 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
6842 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
6843 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
6844 
6845 /* Bits 3..0 : Channel that task RESUME will subscribe to */
6846 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6847 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6848 
6849 /* Register: SPIM_EVENTS_STOPPED */
6850 /* Description: SPI transaction has stopped */
6851 
6852 /* Bit 0 : SPI transaction has stopped */
6853 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
6854 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
6855 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
6856 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6857 
6858 /* Register: SPIM_EVENTS_ENDRX */
6859 /* Description: End of RXD buffer reached */
6860 
6861 /* Bit 0 : End of RXD buffer reached */
6862 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
6863 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
6864 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
6865 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
6866 
6867 /* Register: SPIM_EVENTS_END */
6868 /* Description: End of RXD buffer and TXD buffer reached */
6869 
6870 /* Bit 0 : End of RXD buffer and TXD buffer reached */
6871 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6872 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6873 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6874 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6875 
6876 /* Register: SPIM_EVENTS_ENDTX */
6877 /* Description: End of TXD buffer reached */
6878 
6879 /* Bit 0 : End of TXD buffer reached */
6880 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
6881 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
6882 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
6883 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
6884 
6885 /* Register: SPIM_EVENTS_STARTED */
6886 /* Description: Transaction started */
6887 
6888 /* Bit 0 : Transaction started */
6889 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
6890 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
6891 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
6892 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
6893 
6894 /* Register: SPIM_PUBLISH_STOPPED */
6895 /* Description: Publish configuration for event STOPPED */
6896 
6897 /* Bit 31 :   */
6898 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
6899 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
6900 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
6901 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6902 
6903 /* Bits 3..0 : Channel that event STOPPED will publish to. */
6904 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6905 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6906 
6907 /* Register: SPIM_PUBLISH_ENDRX */
6908 /* Description: Publish configuration for event ENDRX */
6909 
6910 /* Bit 31 :   */
6911 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
6912 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
6913 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
6914 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
6915 
6916 /* Bits 3..0 : Channel that event ENDRX will publish to. */
6917 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6918 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6919 
6920 /* Register: SPIM_PUBLISH_END */
6921 /* Description: Publish configuration for event END */
6922 
6923 /* Bit 31 :   */
6924 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
6925 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
6926 #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
6927 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6928 
6929 /* Bits 3..0 : Channel that event END will publish to. */
6930 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6931 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6932 
6933 /* Register: SPIM_PUBLISH_ENDTX */
6934 /* Description: Publish configuration for event ENDTX */
6935 
6936 /* Bit 31 :   */
6937 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
6938 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
6939 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
6940 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
6941 
6942 /* Bits 3..0 : Channel that event ENDTX will publish to. */
6943 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6944 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6945 
6946 /* Register: SPIM_PUBLISH_STARTED */
6947 /* Description: Publish configuration for event STARTED */
6948 
6949 /* Bit 31 :   */
6950 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */
6951 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */
6952 #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */
6953 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6954 
6955 /* Bits 3..0 : Channel that event STARTED will publish to. */
6956 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
6957 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
6958 
6959 /* Register: SPIM_SHORTS */
6960 /* Description: Shortcuts between local events and tasks */
6961 
6962 /* Bit 17 : Shortcut between event END and task START */
6963 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
6964 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
6965 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
6966 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
6967 
6968 /* Register: SPIM_INTENSET */
6969 /* Description: Enable interrupt */
6970 
6971 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
6972 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
6973 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6974 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6975 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6976 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6977 
6978 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
6979 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
6980 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6981 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
6982 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6983 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
6984 
6985 /* Bit 6 : Write '1' to enable interrupt for event END */
6986 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
6987 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
6988 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6989 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6990 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
6991 
6992 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
6993 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
6994 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6995 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
6996 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
6997 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
6998 
6999 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
7000 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7001 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7002 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7003 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7004 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7005 
7006 /* Register: SPIM_INTENCLR */
7007 /* Description: Disable interrupt */
7008 
7009 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
7010 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
7011 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
7012 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7013 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7014 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7015 
7016 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
7017 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
7018 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
7019 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7020 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7021 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
7022 
7023 /* Bit 6 : Write '1' to disable interrupt for event END */
7024 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
7025 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7026 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7027 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7028 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
7029 
7030 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7031 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7032 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7033 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7034 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7035 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7036 
7037 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
7038 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7039 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7040 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7041 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7042 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7043 
7044 /* Register: SPIM_ENABLE */
7045 /* Description: Enable SPIM */
7046 
7047 /* Bits 3..0 : Enable or disable SPIM */
7048 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7049 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7050 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
7051 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
7052 
7053 /* Register: SPIM_PSEL_SCK */
7054 /* Description: Pin select for SCK */
7055 
7056 /* Bit 31 : Connection */
7057 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7058 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7059 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7060 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7061 
7062 /* Bits 4..0 : Pin number */
7063 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7064 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7065 
7066 /* Register: SPIM_PSEL_MOSI */
7067 /* Description: Pin select for MOSI signal */
7068 
7069 /* Bit 31 : Connection */
7070 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7071 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7072 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7073 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7074 
7075 /* Bits 4..0 : Pin number */
7076 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7077 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7078 
7079 /* Register: SPIM_PSEL_MISO */
7080 /* Description: Pin select for MISO signal */
7081 
7082 /* Bit 31 : Connection */
7083 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7084 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7085 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7086 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7087 
7088 /* Bits 4..0 : Pin number */
7089 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7090 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7091 
7092 /* Register: SPIM_FREQUENCY */
7093 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
7094 
7095 /* Bits 31..0 : SPI master data rate */
7096 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
7097 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
7098 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
7099 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
7100 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
7101 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7102 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
7103 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
7104 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
7105 
7106 /* Register: SPIM_RXD_PTR */
7107 /* Description: Data pointer */
7108 
7109 /* Bits 31..0 : Data pointer */
7110 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7111 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7112 
7113 /* Register: SPIM_RXD_MAXCNT */
7114 /* Description: Maximum number of bytes in receive buffer */
7115 
7116 /* Bits 12..0 : Maximum number of bytes in receive buffer */
7117 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7118 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7119 
7120 /* Register: SPIM_RXD_AMOUNT */
7121 /* Description: Number of bytes transferred in the last transaction */
7122 
7123 /* Bits 12..0 : Number of bytes transferred in the last transaction */
7124 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7125 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7126 
7127 /* Register: SPIM_RXD_LIST */
7128 /* Description: EasyDMA list type */
7129 
7130 /* Bits 1..0 : List type */
7131 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7132 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7133 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7134 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7135 
7136 /* Register: SPIM_TXD_PTR */
7137 /* Description: Data pointer */
7138 
7139 /* Bits 31..0 : Data pointer */
7140 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7141 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7142 
7143 /* Register: SPIM_TXD_MAXCNT */
7144 /* Description: Maximum number of bytes in transmit buffer */
7145 
7146 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
7147 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7148 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7149 
7150 /* Register: SPIM_TXD_AMOUNT */
7151 /* Description: Number of bytes transferred in the last transaction */
7152 
7153 /* Bits 12..0 : Number of bytes transferred in the last transaction */
7154 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7155 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7156 
7157 /* Register: SPIM_TXD_LIST */
7158 /* Description: EasyDMA list type */
7159 
7160 /* Bits 1..0 : List type */
7161 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
7162 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
7163 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
7164 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7165 
7166 /* Register: SPIM_CONFIG */
7167 /* Description: Configuration register */
7168 
7169 /* Bit 2 : Serial clock (SCK) polarity */
7170 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7171 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7172 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7173 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7174 
7175 /* Bit 1 : Serial clock (SCK) phase */
7176 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7177 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7178 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7179 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7180 
7181 /* Bit 0 : Bit order */
7182 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7183 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7184 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
7185 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7186 
7187 /* Register: SPIM_ORC */
7188 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
7189 
7190 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
7191 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
7192 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
7193 
7194 
7195 /* Peripheral: SPIS */
7196 /* Description: SPI Slave 0 */
7197 
7198 /* Register: SPIS_TASKS_ACQUIRE */
7199 /* Description: Acquire SPI semaphore */
7200 
7201 /* Bit 0 : Acquire SPI semaphore */
7202 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
7203 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
7204 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
7205 
7206 /* Register: SPIS_TASKS_RELEASE */
7207 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
7208 
7209 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
7210 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
7211 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
7212 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
7213 
7214 /* Register: SPIS_SUBSCRIBE_ACQUIRE */
7215 /* Description: Subscribe configuration for task ACQUIRE */
7216 
7217 /* Bit 31 :   */
7218 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */
7219 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */
7220 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */
7221 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
7222 
7223 /* Bits 3..0 : Channel that task ACQUIRE will subscribe to */
7224 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7225 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7226 
7227 /* Register: SPIS_SUBSCRIBE_RELEASE */
7228 /* Description: Subscribe configuration for task RELEASE */
7229 
7230 /* Bit 31 :   */
7231 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */
7232 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */
7233 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */
7234 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
7235 
7236 /* Bits 3..0 : Channel that task RELEASE will subscribe to */
7237 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7238 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7239 
7240 /* Register: SPIS_EVENTS_END */
7241 /* Description: Granted transaction completed */
7242 
7243 /* Bit 0 : Granted transaction completed */
7244 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
7245 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
7246 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
7247 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7248 
7249 /* Register: SPIS_EVENTS_ENDRX */
7250 /* Description: End of RXD buffer reached */
7251 
7252 /* Bit 0 : End of RXD buffer reached */
7253 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
7254 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
7255 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
7256 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
7257 
7258 /* Register: SPIS_EVENTS_ACQUIRED */
7259 /* Description: Semaphore acquired */
7260 
7261 /* Bit 0 : Semaphore acquired */
7262 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
7263 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
7264 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
7265 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
7266 
7267 /* Register: SPIS_PUBLISH_END */
7268 /* Description: Publish configuration for event END */
7269 
7270 /* Bit 31 :   */
7271 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
7272 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
7273 #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
7274 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
7275 
7276 /* Bits 3..0 : Channel that event END will publish to. */
7277 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7278 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7279 
7280 /* Register: SPIS_PUBLISH_ENDRX */
7281 /* Description: Publish configuration for event ENDRX */
7282 
7283 /* Bit 31 :   */
7284 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
7285 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
7286 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
7287 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
7288 
7289 /* Bits 3..0 : Channel that event ENDRX will publish to. */
7290 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7291 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7292 
7293 /* Register: SPIS_PUBLISH_ACQUIRED */
7294 /* Description: Publish configuration for event ACQUIRED */
7295 
7296 /* Bit 31 :   */
7297 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */
7298 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */
7299 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */
7300 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
7301 
7302 /* Bits 3..0 : Channel that event ACQUIRED will publish to. */
7303 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7304 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7305 
7306 /* Register: SPIS_SHORTS */
7307 /* Description: Shortcuts between local events and tasks */
7308 
7309 /* Bit 2 : Shortcut between event END and task ACQUIRE */
7310 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
7311 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
7312 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
7313 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
7314 
7315 /* Register: SPIS_INTENSET */
7316 /* Description: Enable interrupt */
7317 
7318 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
7319 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
7320 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
7321 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7322 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7323 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
7324 
7325 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7326 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7327 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7328 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7329 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7330 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7331 
7332 /* Bit 1 : Write '1' to enable interrupt for event END */
7333 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
7334 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
7335 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7336 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7337 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
7338 
7339 /* Register: SPIS_INTENCLR */
7340 /* Description: Disable interrupt */
7341 
7342 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
7343 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
7344 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
7345 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7346 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7347 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
7348 
7349 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7350 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
7351 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
7352 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7353 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7354 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7355 
7356 /* Bit 1 : Write '1' to disable interrupt for event END */
7357 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
7358 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7359 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7360 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7361 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
7362 
7363 /* Register: SPIS_SEMSTAT */
7364 /* Description: Semaphore status register */
7365 
7366 /* Bits 1..0 : Semaphore status */
7367 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
7368 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
7369 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
7370 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
7371 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
7372 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
7373 
7374 /* Register: SPIS_STATUS */
7375 /* Description: Status from last transaction */
7376 
7377 /* Bit 1 : RX buffer overflow detected, and prevented */
7378 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
7379 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
7380 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
7381 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
7382 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
7383 
7384 /* Bit 0 : TX buffer over-read detected, and prevented */
7385 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
7386 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
7387 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
7388 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
7389 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
7390 
7391 /* Register: SPIS_ENABLE */
7392 /* Description: Enable SPI slave */
7393 
7394 /* Bits 3..0 : Enable or disable SPI slave */
7395 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7396 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7397 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
7398 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
7399 
7400 /* Register: SPIS_PSEL_SCK */
7401 /* Description: Pin select for SCK */
7402 
7403 /* Bit 31 : Connection */
7404 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7405 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7406 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7407 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7408 
7409 /* Bits 4..0 : Pin number */
7410 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7411 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7412 
7413 /* Register: SPIS_PSEL_MISO */
7414 /* Description: Pin select for MISO signal */
7415 
7416 /* Bit 31 : Connection */
7417 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7418 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7419 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
7420 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7421 
7422 /* Bits 4..0 : Pin number */
7423 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
7424 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
7425 
7426 /* Register: SPIS_PSEL_MOSI */
7427 /* Description: Pin select for MOSI signal */
7428 
7429 /* Bit 31 : Connection */
7430 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7431 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7432 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
7433 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7434 
7435 /* Bits 4..0 : Pin number */
7436 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
7437 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
7438 
7439 /* Register: SPIS_PSEL_CSN */
7440 /* Description: Pin select for CSN signal */
7441 
7442 /* Bit 31 : Connection */
7443 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7444 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7445 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
7446 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
7447 
7448 /* Bits 4..0 : Pin number */
7449 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
7450 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
7451 
7452 /* Register: SPIS_RXD_PTR */
7453 /* Description: RXD data pointer */
7454 
7455 /* Bits 31..0 : RXD data pointer */
7456 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7457 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7458 
7459 /* Register: SPIS_RXD_MAXCNT */
7460 /* Description: Maximum number of bytes in receive buffer */
7461 
7462 /* Bits 12..0 : Maximum number of bytes in receive buffer */
7463 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7464 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7465 
7466 /* Register: SPIS_RXD_AMOUNT */
7467 /* Description: Number of bytes received in last granted transaction */
7468 
7469 /* Bits 12..0 : Number of bytes received in the last granted transaction */
7470 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7471 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7472 
7473 /* Register: SPIS_TXD_PTR */
7474 /* Description: TXD data pointer */
7475 
7476 /* Bits 31..0 : TXD data pointer */
7477 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7478 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7479 
7480 /* Register: SPIS_TXD_MAXCNT */
7481 /* Description: Maximum number of bytes in transmit buffer */
7482 
7483 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
7484 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7485 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7486 
7487 /* Register: SPIS_TXD_AMOUNT */
7488 /* Description: Number of bytes transmitted in last granted transaction */
7489 
7490 /* Bits 12..0 : Number of bytes transmitted in last granted transaction */
7491 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7492 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7493 
7494 /* Register: SPIS_CONFIG */
7495 /* Description: Configuration register */
7496 
7497 /* Bit 2 : Serial clock (SCK) polarity */
7498 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
7499 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
7500 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
7501 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7502 
7503 /* Bit 1 : Serial clock (SCK) phase */
7504 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7505 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
7506 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
7507 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
7508 
7509 /* Bit 0 : Bit order */
7510 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
7511 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
7512 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
7513 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7514 
7515 /* Register: SPIS_DEF */
7516 /* Description: Default character. Character clocked out in case of an ignored transaction. */
7517 
7518 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
7519 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
7520 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
7521 
7522 /* Register: SPIS_ORC */
7523 /* Description: Over-read character */
7524 
7525 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
7526 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
7527 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
7528 
7529 
7530 /* Peripheral: SPU */
7531 /* Description: System protection unit */
7532 
7533 /* Register: SPU_EVENTS_RAMACCERR */
7534 /* Description: A security violation has been detected for the RAM memory space */
7535 
7536 /* Bit 0 : A security violation has been detected for the RAM memory space */
7537 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */
7538 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */
7539 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */
7540 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */
7541 
7542 /* Register: SPU_EVENTS_FLASHACCERR */
7543 /* Description: A security violation has been detected for the flash memory space */
7544 
7545 /* Bit 0 : A security violation has been detected for the flash memory space */
7546 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */
7547 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */
7548 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */
7549 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */
7550 
7551 /* Register: SPU_EVENTS_PERIPHACCERR */
7552 /* Description: A security violation has been detected on one or several peripherals */
7553 
7554 /* Bit 0 : A security violation has been detected on one or several peripherals */
7555 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */
7556 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */
7557 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */
7558 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */
7559 
7560 /* Register: SPU_PUBLISH_RAMACCERR */
7561 /* Description: Publish configuration for event RAMACCERR */
7562 
7563 /* Bit 31 :   */
7564 #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */
7565 #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */
7566 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7567 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7568 
7569 /* Bits 3..0 : Channel that event RAMACCERR will publish to. */
7570 #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7571 #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7572 
7573 /* Register: SPU_PUBLISH_FLASHACCERR */
7574 /* Description: Publish configuration for event FLASHACCERR */
7575 
7576 /* Bit 31 :   */
7577 #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
7578 #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */
7579 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7580 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7581 
7582 /* Bits 3..0 : Channel that event FLASHACCERR will publish to. */
7583 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7584 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7585 
7586 /* Register: SPU_PUBLISH_PERIPHACCERR */
7587 /* Description: Publish configuration for event PERIPHACCERR */
7588 
7589 /* Bit 31 :   */
7590 #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */
7591 #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */
7592 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */
7593 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7594 
7595 /* Bits 3..0 : Channel that event PERIPHACCERR will publish to. */
7596 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
7597 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
7598 
7599 /* Register: SPU_INTEN */
7600 /* Description: Enable or disable interrupt */
7601 
7602 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */
7603 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7604 #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
7605 #define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */
7606 #define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */
7607 
7608 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
7609 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7610 #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
7611 #define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */
7612 #define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */
7613 
7614 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */
7615 #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
7616 #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
7617 #define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */
7618 #define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */
7619 
7620 /* Register: SPU_INTENSET */
7621 /* Description: Enable interrupt */
7622 
7623 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
7624 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7625 #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
7626 #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7627 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7628 #define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */
7629 
7630 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
7631 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7632 #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
7633 #define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7634 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7635 #define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */
7636 
7637 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
7638 #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
7639 #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
7640 #define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7641 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7642 #define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */
7643 
7644 /* Register: SPU_INTENCLR */
7645 /* Description: Disable interrupt */
7646 
7647 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
7648 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */
7649 #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */
7650 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7651 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7652 #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */
7653 
7654 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
7655 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7656 #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */
7657 #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7658 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7659 #define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */
7660 
7661 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
7662 #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */
7663 #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */
7664 #define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7665 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7666 #define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */
7667 
7668 /* Register: SPU_CAP */
7669 /* Description: Show implemented features for the current device */
7670 
7671 /* Bit 0 : Show ARM TrustZone status */
7672 #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */
7673 #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */
7674 #define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */
7675 #define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */
7676 
7677 /* Register: SPU_EXTDOMAIN_PERM */
7678 /* Description: Description cluster: Access  for bus access generated from the external domain n List capabilities of the external domain  n */
7679 
7680 /* Bit 8 :   */
7681 #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
7682 #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
7683 #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
7684 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
7685 
7686 /* Bit 4 : Peripheral security mapping */
7687 #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
7688 #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
7689 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */
7690 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */
7691 
7692 /* Bits 1..0 : Define configuration capabilities  for TrustZone Cortex-M secure attribute */
7693 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
7694 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
7695 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */
7696 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */
7697 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */
7698 
7699 /* Register: SPU_DPPI_PERM */
7700 /* Description: Description cluster: Select between secure and non-secure attribute  for the DPPI channels. */
7701 
7702 /* Bit 15 : Select secure attribute. */
7703 #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */
7704 #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */
7705 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */
7706 #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */
7707 
7708 /* Bit 14 : Select secure attribute. */
7709 #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */
7710 #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */
7711 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */
7712 #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */
7713 
7714 /* Bit 13 : Select secure attribute. */
7715 #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */
7716 #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */
7717 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */
7718 #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */
7719 
7720 /* Bit 12 : Select secure attribute. */
7721 #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */
7722 #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */
7723 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */
7724 #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */
7725 
7726 /* Bit 11 : Select secure attribute. */
7727 #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */
7728 #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */
7729 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */
7730 #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */
7731 
7732 /* Bit 10 : Select secure attribute. */
7733 #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */
7734 #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */
7735 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */
7736 #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */
7737 
7738 /* Bit 9 : Select secure attribute. */
7739 #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */
7740 #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */
7741 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */
7742 #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */
7743 
7744 /* Bit 8 : Select secure attribute. */
7745 #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */
7746 #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */
7747 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */
7748 #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */
7749 
7750 /* Bit 7 : Select secure attribute. */
7751 #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */
7752 #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */
7753 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */
7754 #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */
7755 
7756 /* Bit 6 : Select secure attribute. */
7757 #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */
7758 #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */
7759 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */
7760 #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */
7761 
7762 /* Bit 5 : Select secure attribute. */
7763 #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */
7764 #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */
7765 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */
7766 #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */
7767 
7768 /* Bit 4 : Select secure attribute. */
7769 #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */
7770 #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */
7771 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */
7772 #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */
7773 
7774 /* Bit 3 : Select secure attribute. */
7775 #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */
7776 #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */
7777 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */
7778 #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */
7779 
7780 /* Bit 2 : Select secure attribute. */
7781 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */
7782 #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */
7783 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */
7784 #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */
7785 
7786 /* Bit 1 : Select secure attribute. */
7787 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
7788 #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */
7789 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */
7790 #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */
7791 
7792 /* Bit 0 : Select secure attribute. */
7793 #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */
7794 #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */
7795 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */
7796 #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */
7797 
7798 /* Register: SPU_DPPI_LOCK */
7799 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
7800 
7801 /* Bit 0 :   */
7802 #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
7803 #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
7804 #define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */
7805 #define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */
7806 
7807 /* Register: SPU_GPIOPORT_PERM */
7808 /* Description: Description cluster: Select between secure and non-secure attribute  for pins 0 to 31  of port n. */
7809 
7810 /* Bit 31 : Select secure attribute attribute for PIN 31. */
7811 #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
7812 #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */
7813 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */
7814 #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */
7815 
7816 /* Bit 30 : Select secure attribute attribute for PIN 30. */
7817 #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
7818 #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */
7819 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */
7820 #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */
7821 
7822 /* Bit 29 : Select secure attribute attribute for PIN 29. */
7823 #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
7824 #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */
7825 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */
7826 #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */
7827 
7828 /* Bit 28 : Select secure attribute attribute for PIN 28. */
7829 #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
7830 #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */
7831 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */
7832 #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */
7833 
7834 /* Bit 27 : Select secure attribute attribute for PIN 27. */
7835 #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
7836 #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */
7837 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */
7838 #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */
7839 
7840 /* Bit 26 : Select secure attribute attribute for PIN 26. */
7841 #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
7842 #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */
7843 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */
7844 #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */
7845 
7846 /* Bit 25 : Select secure attribute attribute for PIN 25. */
7847 #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
7848 #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */
7849 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */
7850 #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */
7851 
7852 /* Bit 24 : Select secure attribute attribute for PIN 24. */
7853 #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
7854 #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */
7855 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */
7856 #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */
7857 
7858 /* Bit 23 : Select secure attribute attribute for PIN 23. */
7859 #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
7860 #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */
7861 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */
7862 #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */
7863 
7864 /* Bit 22 : Select secure attribute attribute for PIN 22. */
7865 #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
7866 #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */
7867 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */
7868 #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */
7869 
7870 /* Bit 21 : Select secure attribute attribute for PIN 21. */
7871 #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
7872 #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */
7873 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */
7874 #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */
7875 
7876 /* Bit 20 : Select secure attribute attribute for PIN 20. */
7877 #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
7878 #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */
7879 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */
7880 #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */
7881 
7882 /* Bit 19 : Select secure attribute attribute for PIN 19. */
7883 #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
7884 #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */
7885 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */
7886 #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */
7887 
7888 /* Bit 18 : Select secure attribute attribute for PIN 18. */
7889 #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
7890 #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */
7891 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */
7892 #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */
7893 
7894 /* Bit 17 : Select secure attribute attribute for PIN 17. */
7895 #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
7896 #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */
7897 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */
7898 #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */
7899 
7900 /* Bit 16 : Select secure attribute attribute for PIN 16. */
7901 #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
7902 #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */
7903 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */
7904 #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */
7905 
7906 /* Bit 15 : Select secure attribute attribute for PIN 15. */
7907 #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
7908 #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */
7909 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */
7910 #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */
7911 
7912 /* Bit 14 : Select secure attribute attribute for PIN 14. */
7913 #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
7914 #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */
7915 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */
7916 #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */
7917 
7918 /* Bit 13 : Select secure attribute attribute for PIN 13. */
7919 #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
7920 #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */
7921 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */
7922 #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */
7923 
7924 /* Bit 12 : Select secure attribute attribute for PIN 12. */
7925 #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
7926 #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */
7927 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */
7928 #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */
7929 
7930 /* Bit 11 : Select secure attribute attribute for PIN 11. */
7931 #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
7932 #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */
7933 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */
7934 #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */
7935 
7936 /* Bit 10 : Select secure attribute attribute for PIN 10. */
7937 #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
7938 #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */
7939 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */
7940 #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */
7941 
7942 /* Bit 9 : Select secure attribute attribute for PIN 9. */
7943 #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
7944 #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */
7945 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */
7946 #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */
7947 
7948 /* Bit 8 : Select secure attribute attribute for PIN 8. */
7949 #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
7950 #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */
7951 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */
7952 #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */
7953 
7954 /* Bit 7 : Select secure attribute attribute for PIN 7. */
7955 #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
7956 #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */
7957 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */
7958 #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */
7959 
7960 /* Bit 6 : Select secure attribute attribute for PIN 6. */
7961 #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
7962 #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */
7963 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */
7964 #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */
7965 
7966 /* Bit 5 : Select secure attribute attribute for PIN 5. */
7967 #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
7968 #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */
7969 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */
7970 #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */
7971 
7972 /* Bit 4 : Select secure attribute attribute for PIN 4. */
7973 #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
7974 #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */
7975 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */
7976 #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */
7977 
7978 /* Bit 3 : Select secure attribute attribute for PIN 3. */
7979 #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
7980 #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */
7981 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */
7982 #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */
7983 
7984 /* Bit 2 : Select secure attribute attribute for PIN 2. */
7985 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
7986 #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */
7987 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
7988 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
7989 
7990 /* Bit 1 : Select secure attribute attribute for PIN 1. */
7991 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7992 #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */
7993 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
7994 #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */
7995 
7996 /* Bit 0 : Select secure attribute attribute for PIN 0. */
7997 #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
7998 #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */
7999 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */
8000 #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */
8001 
8002 /* Register: SPU_GPIOPORT_LOCK */
8003 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */
8004 
8005 /* Bit 0 :   */
8006 #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */
8007 #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */
8008 #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */
8009 #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */
8010 
8011 /* Register: SPU_FLASHNSC_REGION */
8012 /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */
8013 
8014 /* Bit 8 :   */
8015 #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8016 #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
8017 #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
8018 #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8019 
8020 /* Bits 4..0 : Region number */
8021 #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
8022 #define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
8023 
8024 /* Register: SPU_FLASHNSC_SIZE */
8025 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
8026 
8027 /* Bit 8 :   */
8028 #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8029 #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
8030 #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
8031 #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8032 
8033 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8034 #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
8035 #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
8036 #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
8037 #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
8038 #define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
8039 #define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
8040 #define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
8041 #define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
8042 #define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
8043 #define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
8044 #define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
8045 
8046 /* Register: SPU_RAMNSC_REGION */
8047 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */
8048 
8049 /* Bit 8 :   */
8050 #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8051 #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */
8052 #define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */
8053 #define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8054 
8055 /* Bits 3..0 : Region number */
8056 #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */
8057 #define SPU_RAMNSC_REGION_REGION_Msk (0xFUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */
8058 
8059 /* Register: SPU_RAMNSC_SIZE */
8060 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */
8061 
8062 /* Bit 8 :   */
8063 #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8064 #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */
8065 #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */
8066 #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8067 
8068 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8069 #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
8070 #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
8071 #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */
8072 #define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */
8073 #define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */
8074 #define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */
8075 #define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */
8076 #define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */
8077 #define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */
8078 #define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */
8079 #define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */
8080 
8081 /* Register: SPU_FLASHREGION_PERM */
8082 /* Description: Description cluster: Access permissions for flash region n */
8083 
8084 /* Bit 8 :   */
8085 #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8086 #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
8087 #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
8088 #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8089 
8090 /* Bit 4 : Security attribute for flash region n */
8091 #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
8092 #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
8093 #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */
8094 #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */
8095 
8096 /* Bit 2 : Configure read permissions for flash region n */
8097 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8098 #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
8099 #define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */
8100 #define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */
8101 
8102 /* Bit 1 : Configure write permission for flash region n */
8103 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
8104 #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
8105 #define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */
8106 #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */
8107 
8108 /* Bit 0 : Configure instruction fetch permissions from flash region n */
8109 #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
8110 #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
8111 #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */
8112 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */
8113 
8114 /* Register: SPU_RAMREGION_PERM */
8115 /* Description: Description cluster: Access permissions for RAM region n */
8116 
8117 /* Bit 8 :   */
8118 #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8119 #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
8120 #define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
8121 #define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8122 
8123 /* Bit 4 : Security attribute for RAM region n */
8124 #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
8125 #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
8126 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */
8127 #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */
8128 
8129 /* Bit 2 : Configure read permissions for RAM region n */
8130 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */
8131 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */
8132 #define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */
8133 #define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */
8134 
8135 /* Bit 1 : Configure write permission for RAM region n */
8136 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
8137 #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
8138 #define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */
8139 #define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */
8140 
8141 /* Bit 0 : Configure instruction fetch permissions from RAM region n */
8142 #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */
8143 #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */
8144 #define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */
8145 #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */
8146 
8147 /* Register: SPU_PERIPHID_PERM */
8148 /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */
8149 
8150 /* Bit 31 : Indicate if a peripheral is present with ID n */
8151 #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */
8152 #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */
8153 #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */
8154 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */
8155 
8156 /* Bit 8 :   */
8157 #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */
8158 #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */
8159 #define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */
8160 #define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */
8161 
8162 /* Bit 5 : Security attribution for the DMA transfer */
8163 #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */
8164 #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */
8165 #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */
8166 #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */
8167 
8168 /* Bit 4 : Peripheral security mapping */
8169 #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */
8170 #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */
8171 #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */
8172 #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */
8173 
8174 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */
8175 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */
8176 #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */
8177 #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */
8178 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */
8179 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */
8180 
8181 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
8182 #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */
8183 #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
8184 #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
8185 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */
8186 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */
8187 #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */
8188 
8189 
8190 /* Peripheral: TAD */
8191 /* Description: Trace and debug control */
8192 
8193 /* Register: TAD_ENABLE */
8194 /* Description: Enable debug domain and aquire selected GPIOs */
8195 
8196 /* Bit 0 :   */
8197 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8198 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8199 #define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */
8200 #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
8201 
8202 /* Register: TAD_PSEL_TRACECLK */
8203 /* Description: Pin number configuration for TRACECLK */
8204 
8205 /* Bit 31 : Connection */
8206 #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8207 #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8208 #define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */
8209 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
8210 
8211 /* Bits 4..0 : Pin number */
8212 #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */
8213 #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */
8214 
8215 /* Register: TAD_PSEL_TRACEDATA0 */
8216 /* Description: Pin number configuration for TRACEDATA[0] */
8217 
8218 /* Bit 31 : Connection */
8219 #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8220 #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8221 #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */
8222 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */
8223 
8224 /* Bits 4..0 : Pin number */
8225 #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */
8226 #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */
8227 
8228 /* Register: TAD_PSEL_TRACEDATA1 */
8229 /* Description: Pin number configuration for TRACEDATA[1] */
8230 
8231 /* Bit 31 : Connection */
8232 #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8233 #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8234 #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */
8235 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */
8236 
8237 /* Bits 4..0 : Pin number */
8238 #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */
8239 #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */
8240 
8241 /* Register: TAD_PSEL_TRACEDATA2 */
8242 /* Description: Pin number configuration for TRACEDATA[2] */
8243 
8244 /* Bit 31 : Connection */
8245 #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8246 #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8247 #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */
8248 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */
8249 
8250 /* Bits 4..0 : Pin number */
8251 #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */
8252 #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */
8253 
8254 /* Register: TAD_PSEL_TRACEDATA3 */
8255 /* Description: Pin number configuration for TRACEDATA[3] */
8256 
8257 /* Bit 31 : Connection */
8258 #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8259 #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8260 #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */
8261 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */
8262 
8263 /* Bits 4..0 : Pin number */
8264 #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */
8265 #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */
8266 
8267 /* Register: TAD_TRACEPORTSPEED */
8268 /* Description: Clocking options for the Trace Port debug interface */
8269 
8270 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
8271 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
8272 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
8273 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
8274 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
8275 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
8276 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
8277 
8278 
8279 /* Peripheral: TIMER */
8280 /* Description: Timer/Counter 0 */
8281 
8282 /* Register: TIMER_TASKS_START */
8283 /* Description: Start Timer */
8284 
8285 /* Bit 0 : Start Timer */
8286 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8287 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8288 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8289 
8290 /* Register: TIMER_TASKS_STOP */
8291 /* Description: Stop Timer */
8292 
8293 /* Bit 0 : Stop Timer */
8294 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8295 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8296 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8297 
8298 /* Register: TIMER_TASKS_COUNT */
8299 /* Description: Increment Timer (Counter mode only) */
8300 
8301 /* Bit 0 : Increment Timer (Counter mode only) */
8302 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
8303 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
8304 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
8305 
8306 /* Register: TIMER_TASKS_CLEAR */
8307 /* Description: Clear time */
8308 
8309 /* Bit 0 : Clear time */
8310 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
8311 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
8312 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
8313 
8314 /* Register: TIMER_TASKS_SHUTDOWN */
8315 /* Description: Deprecated register - Shut down timer */
8316 
8317 /* Bit 0 : Deprecated field -  Shut down timer */
8318 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
8319 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
8320 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
8321 
8322 /* Register: TIMER_TASKS_CAPTURE */
8323 /* Description: Description collection: Capture Timer value to CC[n] register */
8324 
8325 /* Bit 0 : Capture Timer value to CC[n] register */
8326 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
8327 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
8328 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
8329 
8330 /* Register: TIMER_SUBSCRIBE_START */
8331 /* Description: Subscribe configuration for task START */
8332 
8333 /* Bit 31 :   */
8334 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
8335 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
8336 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
8337 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8338 
8339 /* Bits 3..0 : Channel that task START will subscribe to */
8340 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8341 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8342 
8343 /* Register: TIMER_SUBSCRIBE_STOP */
8344 /* Description: Subscribe configuration for task STOP */
8345 
8346 /* Bit 31 :   */
8347 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8348 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8349 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8350 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8351 
8352 /* Bits 3..0 : Channel that task STOP will subscribe to */
8353 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8354 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8355 
8356 /* Register: TIMER_SUBSCRIBE_COUNT */
8357 /* Description: Subscribe configuration for task COUNT */
8358 
8359 /* Bit 31 :   */
8360 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
8361 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
8362 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
8363 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
8364 
8365 /* Bits 3..0 : Channel that task COUNT will subscribe to */
8366 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8367 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8368 
8369 /* Register: TIMER_SUBSCRIBE_CLEAR */
8370 /* Description: Subscribe configuration for task CLEAR */
8371 
8372 /* Bit 31 :   */
8373 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
8374 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
8375 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
8376 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
8377 
8378 /* Bits 3..0 : Channel that task CLEAR will subscribe to */
8379 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8380 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8381 
8382 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */
8383 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
8384 
8385 /* Bit 31 :   */
8386 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
8387 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
8388 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
8389 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
8390 
8391 /* Bits 3..0 : Channel that task SHUTDOWN will subscribe to */
8392 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8393 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8394 
8395 /* Register: TIMER_SUBSCRIBE_CAPTURE */
8396 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
8397 
8398 /* Bit 31 :   */
8399 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
8400 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
8401 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
8402 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
8403 
8404 /* Bits 3..0 : Channel that task CAPTURE[n] will subscribe to */
8405 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8406 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8407 
8408 /* Register: TIMER_EVENTS_COMPARE */
8409 /* Description: Description collection: Compare event on CC[n] match */
8410 
8411 /* Bit 0 : Compare event on CC[n] match */
8412 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
8413 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
8414 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
8415 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
8416 
8417 /* Register: TIMER_PUBLISH_COMPARE */
8418 /* Description: Description collection: Publish configuration for event COMPARE[n] */
8419 
8420 /* Bit 31 :   */
8421 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
8422 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
8423 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
8424 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
8425 
8426 /* Bits 3..0 : Channel that event COMPARE[n] will publish to. */
8427 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8428 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8429 
8430 /* Register: TIMER_SHORTS */
8431 /* Description: Shortcuts between local events and tasks */
8432 
8433 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
8434 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
8435 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
8436 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
8437 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8438 
8439 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
8440 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
8441 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
8442 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
8443 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8444 
8445 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
8446 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
8447 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
8448 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
8449 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8450 
8451 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
8452 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
8453 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
8454 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
8455 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8456 
8457 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
8458 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
8459 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
8460 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
8461 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8462 
8463 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
8464 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
8465 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
8466 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
8467 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8468 
8469 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
8470 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
8471 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
8472 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8473 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8474 
8475 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
8476 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
8477 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
8478 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8479 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8480 
8481 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
8482 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
8483 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
8484 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8485 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8486 
8487 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
8488 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8489 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
8490 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8491 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8492 
8493 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
8494 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
8495 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
8496 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8497 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8498 
8499 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
8500 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
8501 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
8502 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8503 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8504 
8505 /* Register: TIMER_INTENSET */
8506 /* Description: Enable interrupt */
8507 
8508 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
8509 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8510 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8511 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8512 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8513 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8514 
8515 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
8516 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8517 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8518 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8519 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8520 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
8521 
8522 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
8523 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8524 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8525 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8526 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8527 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8528 
8529 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8530 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8531 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8532 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8533 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8534 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8535 
8536 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
8537 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8538 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8539 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8540 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8541 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8542 
8543 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
8544 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8545 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8546 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8547 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8548 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8549 
8550 /* Register: TIMER_INTENCLR */
8551 /* Description: Disable interrupt */
8552 
8553 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
8554 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8555 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8556 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8557 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8558 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
8559 
8560 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
8561 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8562 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8563 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8564 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8565 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
8566 
8567 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
8568 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
8569 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
8570 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8571 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8572 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8573 
8574 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8575 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
8576 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
8577 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8578 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8579 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8580 
8581 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
8582 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
8583 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
8584 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8585 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8586 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8587 
8588 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
8589 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
8590 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
8591 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8592 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8593 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8594 
8595 /* Register: TIMER_MODE */
8596 /* Description: Timer mode selection */
8597 
8598 /* Bits 1..0 : Timer mode */
8599 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
8600 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
8601 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
8602 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
8603 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
8604 
8605 /* Register: TIMER_BITMODE */
8606 /* Description: Configure the number of bits used by the TIMER */
8607 
8608 /* Bits 1..0 : Timer bit width */
8609 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
8610 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
8611 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
8612 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
8613 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
8614 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
8615 
8616 /* Register: TIMER_PRESCALER */
8617 /* Description: Timer prescaler register */
8618 
8619 /* Bits 3..0 : Prescaler value */
8620 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8621 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8622 
8623 /* Register: TIMER_CC */
8624 /* Description: Description collection: Capture/Compare register n */
8625 
8626 /* Bits 31..0 : Capture/Compare value */
8627 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
8628 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
8629 
8630 
8631 /* Peripheral: TWIM */
8632 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
8633 
8634 /* Register: TWIM_TASKS_STARTRX */
8635 /* Description: Start TWI receive sequence */
8636 
8637 /* Bit 0 : Start TWI receive sequence */
8638 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
8639 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
8640 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
8641 
8642 /* Register: TWIM_TASKS_STARTTX */
8643 /* Description: Start TWI transmit sequence */
8644 
8645 /* Bit 0 : Start TWI transmit sequence */
8646 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
8647 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
8648 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
8649 
8650 /* Register: TWIM_TASKS_STOP */
8651 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8652 
8653 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
8654 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8655 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8656 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8657 
8658 /* Register: TWIM_TASKS_SUSPEND */
8659 /* Description: Suspend TWI transaction */
8660 
8661 /* Bit 0 : Suspend TWI transaction */
8662 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
8663 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
8664 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8665 
8666 /* Register: TWIM_TASKS_RESUME */
8667 /* Description: Resume TWI transaction */
8668 
8669 /* Bit 0 : Resume TWI transaction */
8670 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
8671 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
8672 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8673 
8674 /* Register: TWIM_SUBSCRIBE_STARTRX */
8675 /* Description: Subscribe configuration for task STARTRX */
8676 
8677 /* Bit 31 :   */
8678 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
8679 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
8680 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
8681 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
8682 
8683 /* Bits 3..0 : Channel that task STARTRX will subscribe to */
8684 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8685 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8686 
8687 /* Register: TWIM_SUBSCRIBE_STARTTX */
8688 /* Description: Subscribe configuration for task STARTTX */
8689 
8690 /* Bit 31 :   */
8691 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
8692 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
8693 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
8694 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
8695 
8696 /* Bits 3..0 : Channel that task STARTTX will subscribe to */
8697 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8698 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8699 
8700 /* Register: TWIM_SUBSCRIBE_STOP */
8701 /* Description: Subscribe configuration for task STOP */
8702 
8703 /* Bit 31 :   */
8704 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
8705 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
8706 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
8707 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8708 
8709 /* Bits 3..0 : Channel that task STOP will subscribe to */
8710 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8711 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8712 
8713 /* Register: TWIM_SUBSCRIBE_SUSPEND */
8714 /* Description: Subscribe configuration for task SUSPEND */
8715 
8716 /* Bit 31 :   */
8717 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
8718 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
8719 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
8720 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
8721 
8722 /* Bits 3..0 : Channel that task SUSPEND will subscribe to */
8723 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8724 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8725 
8726 /* Register: TWIM_SUBSCRIBE_RESUME */
8727 /* Description: Subscribe configuration for task RESUME */
8728 
8729 /* Bit 31 :   */
8730 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
8731 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
8732 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
8733 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
8734 
8735 /* Bits 3..0 : Channel that task RESUME will subscribe to */
8736 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8737 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8738 
8739 /* Register: TWIM_EVENTS_STOPPED */
8740 /* Description: TWI stopped */
8741 
8742 /* Bit 0 : TWI stopped */
8743 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8744 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8745 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8746 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8747 
8748 /* Register: TWIM_EVENTS_ERROR */
8749 /* Description: TWI error */
8750 
8751 /* Bit 0 : TWI error */
8752 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
8753 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
8754 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
8755 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
8756 
8757 /* Register: TWIM_EVENTS_SUSPENDED */
8758 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
8759 
8760 /* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
8761 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
8762 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
8763 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
8764 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
8765 
8766 /* Register: TWIM_EVENTS_RXSTARTED */
8767 /* Description: Receive sequence started */
8768 
8769 /* Bit 0 : Receive sequence started */
8770 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
8771 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
8772 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
8773 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
8774 
8775 /* Register: TWIM_EVENTS_TXSTARTED */
8776 /* Description: Transmit sequence started */
8777 
8778 /* Bit 0 : Transmit sequence started */
8779 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
8780 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
8781 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
8782 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
8783 
8784 /* Register: TWIM_EVENTS_LASTRX */
8785 /* Description: Byte boundary, starting to receive the last byte */
8786 
8787 /* Bit 0 : Byte boundary, starting to receive the last byte */
8788 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
8789 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
8790 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
8791 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
8792 
8793 /* Register: TWIM_EVENTS_LASTTX */
8794 /* Description: Byte boundary, starting to transmit the last byte */
8795 
8796 /* Bit 0 : Byte boundary, starting to transmit the last byte */
8797 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
8798 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
8799 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
8800 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
8801 
8802 /* Register: TWIM_PUBLISH_STOPPED */
8803 /* Description: Publish configuration for event STOPPED */
8804 
8805 /* Bit 31 :   */
8806 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
8807 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
8808 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
8809 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
8810 
8811 /* Bits 3..0 : Channel that event STOPPED will publish to. */
8812 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8813 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8814 
8815 /* Register: TWIM_PUBLISH_ERROR */
8816 /* Description: Publish configuration for event ERROR */
8817 
8818 /* Bit 31 :   */
8819 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
8820 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
8821 #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
8822 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
8823 
8824 /* Bits 3..0 : Channel that event ERROR will publish to. */
8825 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8826 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8827 
8828 /* Register: TWIM_PUBLISH_SUSPENDED */
8829 /* Description: Publish configuration for event SUSPENDED */
8830 
8831 /* Bit 31 :   */
8832 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */
8833 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */
8834 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */
8835 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
8836 
8837 /* Bits 3..0 : Channel that event SUSPENDED will publish to. */
8838 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8839 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8840 
8841 /* Register: TWIM_PUBLISH_RXSTARTED */
8842 /* Description: Publish configuration for event RXSTARTED */
8843 
8844 /* Bit 31 :   */
8845 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
8846 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
8847 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
8848 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8849 
8850 /* Bits 3..0 : Channel that event RXSTARTED will publish to. */
8851 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8852 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8853 
8854 /* Register: TWIM_PUBLISH_TXSTARTED */
8855 /* Description: Publish configuration for event TXSTARTED */
8856 
8857 /* Bit 31 :   */
8858 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
8859 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
8860 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
8861 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8862 
8863 /* Bits 3..0 : Channel that event TXSTARTED will publish to. */
8864 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8865 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8866 
8867 /* Register: TWIM_PUBLISH_LASTRX */
8868 /* Description: Publish configuration for event LASTRX */
8869 
8870 /* Bit 31 :   */
8871 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */
8872 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */
8873 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */
8874 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
8875 
8876 /* Bits 3..0 : Channel that event LASTRX will publish to. */
8877 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8878 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8879 
8880 /* Register: TWIM_PUBLISH_LASTTX */
8881 /* Description: Publish configuration for event LASTTX */
8882 
8883 /* Bit 31 :   */
8884 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */
8885 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */
8886 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */
8887 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
8888 
8889 /* Bits 3..0 : Channel that event LASTTX will publish to. */
8890 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
8891 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
8892 
8893 /* Register: TWIM_SHORTS */
8894 /* Description: Shortcuts between local events and tasks */
8895 
8896 /* Bit 12 : Shortcut between event LASTRX and task STOP */
8897 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
8898 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
8899 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
8900 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
8901 
8902 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
8903 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
8904 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
8905 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8906 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8907 
8908 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
8909 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
8910 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
8911 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
8912 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
8913 
8914 /* Bit 9 : Shortcut between event LASTTX and task STOP */
8915 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
8916 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
8917 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
8918 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
8919 
8920 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
8921 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
8922 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
8923 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
8924 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8925 
8926 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
8927 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
8928 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
8929 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
8930 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
8931 
8932 /* Register: TWIM_INTEN */
8933 /* Description: Enable or disable interrupt */
8934 
8935 /* Bit 24 : Enable or disable interrupt for event LASTTX */
8936 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
8937 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
8938 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
8939 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
8940 
8941 /* Bit 23 : Enable or disable interrupt for event LASTRX */
8942 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
8943 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
8944 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
8945 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
8946 
8947 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
8948 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
8949 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
8950 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
8951 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
8952 
8953 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
8954 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
8955 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
8956 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
8957 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
8958 
8959 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
8960 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
8961 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
8962 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
8963 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
8964 
8965 /* Bit 9 : Enable or disable interrupt for event ERROR */
8966 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
8967 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
8968 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
8969 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
8970 
8971 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8972 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8973 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8974 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8975 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8976 
8977 /* Register: TWIM_INTENSET */
8978 /* Description: Enable interrupt */
8979 
8980 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
8981 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
8982 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
8983 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8984 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8985 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
8986 
8987 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
8988 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
8989 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
8990 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8991 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8992 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
8993 
8994 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
8995 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
8996 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
8997 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8998 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8999 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9000 
9001 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9002 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9003 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9004 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9005 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9006 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9007 
9008 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
9009 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9010 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9011 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9012 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9013 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
9014 
9015 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9016 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9017 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9018 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9019 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9020 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
9021 
9022 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9023 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9024 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9025 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9026 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9027 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9028 
9029 /* Register: TWIM_INTENCLR */
9030 /* Description: Disable interrupt */
9031 
9032 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
9033 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9034 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9035 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9036 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9037 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
9038 
9039 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
9040 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9041 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9042 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9043 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9044 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
9045 
9046 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9047 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9048 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9049 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9050 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9051 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9052 
9053 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9054 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9055 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9056 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9057 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9058 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9059 
9060 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9061 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9062 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9063 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9064 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9065 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9066 
9067 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9068 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9069 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9070 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9071 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9072 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9073 
9074 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9075 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9076 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9077 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9078 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9079 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9080 
9081 /* Register: TWIM_ERRORSRC */
9082 /* Description: Error source */
9083 
9084 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9085 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9086 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9087 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9088 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9089 
9090 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9091 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
9092 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
9093 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
9094 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
9095 
9096 /* Bit 0 : Overrun error */
9097 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
9098 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
9099 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
9100 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
9101 
9102 /* Register: TWIM_ENABLE */
9103 /* Description: Enable TWIM */
9104 
9105 /* Bits 3..0 : Enable or disable TWIM */
9106 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9107 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9108 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
9109 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
9110 
9111 /* Register: TWIM_PSEL_SCL */
9112 /* Description: Pin select for SCL signal */
9113 
9114 /* Bit 31 : Connection */
9115 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9116 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9117 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9118 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9119 
9120 /* Bits 4..0 : Pin number */
9121 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9122 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9123 
9124 /* Register: TWIM_PSEL_SDA */
9125 /* Description: Pin select for SDA signal */
9126 
9127 /* Bit 31 : Connection */
9128 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9129 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9130 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9131 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9132 
9133 /* Bits 4..0 : Pin number */
9134 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9135 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9136 
9137 /* Register: TWIM_FREQUENCY */
9138 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9139 
9140 /* Bits 31..0 : TWI master clock frequency */
9141 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9142 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9143 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
9144 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
9145 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
9146 
9147 /* Register: TWIM_RXD_PTR */
9148 /* Description: Data pointer */
9149 
9150 /* Bits 31..0 : Data pointer */
9151 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9152 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9153 
9154 /* Register: TWIM_RXD_MAXCNT */
9155 /* Description: Maximum number of bytes in receive buffer */
9156 
9157 /* Bits 12..0 : Maximum number of bytes in receive buffer */
9158 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9159 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9160 
9161 /* Register: TWIM_RXD_AMOUNT */
9162 /* Description: Number of bytes transferred in the last transaction */
9163 
9164 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9165 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9166 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9167 
9168 /* Register: TWIM_RXD_LIST */
9169 /* Description: EasyDMA list type */
9170 
9171 /* Bits 1..0 : List type */
9172 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9173 #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9174 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9175 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9176 
9177 /* Register: TWIM_TXD_PTR */
9178 /* Description: Data pointer */
9179 
9180 /* Bits 31..0 : Data pointer */
9181 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9182 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9183 
9184 /* Register: TWIM_TXD_MAXCNT */
9185 /* Description: Maximum number of bytes in transmit buffer */
9186 
9187 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
9188 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9189 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9190 
9191 /* Register: TWIM_TXD_AMOUNT */
9192 /* Description: Number of bytes transferred in the last transaction */
9193 
9194 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9195 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9196 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9197 
9198 /* Register: TWIM_TXD_LIST */
9199 /* Description: EasyDMA list type */
9200 
9201 /* Bits 1..0 : List type */
9202 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9203 #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9204 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9205 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9206 
9207 /* Register: TWIM_ADDRESS */
9208 /* Description: Address used in the TWI transfer */
9209 
9210 /* Bits 6..0 : Address used in the TWI transfer */
9211 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9212 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9213 
9214 
9215 /* Peripheral: TWIS */
9216 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
9217 
9218 /* Register: TWIS_TASKS_STOP */
9219 /* Description: Stop TWI transaction */
9220 
9221 /* Bit 0 : Stop TWI transaction */
9222 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9223 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9224 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9225 
9226 /* Register: TWIS_TASKS_SUSPEND */
9227 /* Description: Suspend TWI transaction */
9228 
9229 /* Bit 0 : Suspend TWI transaction */
9230 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9231 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9232 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9233 
9234 /* Register: TWIS_TASKS_RESUME */
9235 /* Description: Resume TWI transaction */
9236 
9237 /* Bit 0 : Resume TWI transaction */
9238 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
9239 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
9240 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9241 
9242 /* Register: TWIS_TASKS_PREPARERX */
9243 /* Description: Prepare the TWI slave to respond to a write command */
9244 
9245 /* Bit 0 : Prepare the TWI slave to respond to a write command */
9246 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
9247 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
9248 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
9249 
9250 /* Register: TWIS_TASKS_PREPARETX */
9251 /* Description: Prepare the TWI slave to respond to a read command */
9252 
9253 /* Bit 0 : Prepare the TWI slave to respond to a read command */
9254 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
9255 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
9256 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
9257 
9258 /* Register: TWIS_SUBSCRIBE_STOP */
9259 /* Description: Subscribe configuration for task STOP */
9260 
9261 /* Bit 31 :   */
9262 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
9263 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
9264 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
9265 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9266 
9267 /* Bits 3..0 : Channel that task STOP will subscribe to */
9268 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9269 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9270 
9271 /* Register: TWIS_SUBSCRIBE_SUSPEND */
9272 /* Description: Subscribe configuration for task SUSPEND */
9273 
9274 /* Bit 31 :   */
9275 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */
9276 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */
9277 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */
9278 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
9279 
9280 /* Bits 3..0 : Channel that task SUSPEND will subscribe to */
9281 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9282 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9283 
9284 /* Register: TWIS_SUBSCRIBE_RESUME */
9285 /* Description: Subscribe configuration for task RESUME */
9286 
9287 /* Bit 31 :   */
9288 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */
9289 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */
9290 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */
9291 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
9292 
9293 /* Bits 3..0 : Channel that task RESUME will subscribe to */
9294 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9295 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9296 
9297 /* Register: TWIS_SUBSCRIBE_PREPARERX */
9298 /* Description: Subscribe configuration for task PREPARERX */
9299 
9300 /* Bit 31 :   */
9301 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */
9302 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */
9303 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */
9304 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
9305 
9306 /* Bits 3..0 : Channel that task PREPARERX will subscribe to */
9307 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9308 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9309 
9310 /* Register: TWIS_SUBSCRIBE_PREPARETX */
9311 /* Description: Subscribe configuration for task PREPARETX */
9312 
9313 /* Bit 31 :   */
9314 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */
9315 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */
9316 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */
9317 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
9318 
9319 /* Bits 3..0 : Channel that task PREPARETX will subscribe to */
9320 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9321 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9322 
9323 /* Register: TWIS_EVENTS_STOPPED */
9324 /* Description: TWI stopped */
9325 
9326 /* Bit 0 : TWI stopped */
9327 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9328 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9329 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9330 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9331 
9332 /* Register: TWIS_EVENTS_ERROR */
9333 /* Description: TWI error */
9334 
9335 /* Bit 0 : TWI error */
9336 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9337 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9338 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9339 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9340 
9341 /* Register: TWIS_EVENTS_RXSTARTED */
9342 /* Description: Receive sequence started */
9343 
9344 /* Bit 0 : Receive sequence started */
9345 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
9346 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
9347 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9348 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9349 
9350 /* Register: TWIS_EVENTS_TXSTARTED */
9351 /* Description: Transmit sequence started */
9352 
9353 /* Bit 0 : Transmit sequence started */
9354 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
9355 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
9356 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9357 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9358 
9359 /* Register: TWIS_EVENTS_WRITE */
9360 /* Description: Write command received */
9361 
9362 /* Bit 0 : Write command received */
9363 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
9364 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
9365 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
9366 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
9367 
9368 /* Register: TWIS_EVENTS_READ */
9369 /* Description: Read command received */
9370 
9371 /* Bit 0 : Read command received */
9372 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
9373 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
9374 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
9375 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
9376 
9377 /* Register: TWIS_PUBLISH_STOPPED */
9378 /* Description: Publish configuration for event STOPPED */
9379 
9380 /* Bit 31 :   */
9381 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */
9382 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */
9383 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */
9384 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
9385 
9386 /* Bits 3..0 : Channel that event STOPPED will publish to. */
9387 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9388 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9389 
9390 /* Register: TWIS_PUBLISH_ERROR */
9391 /* Description: Publish configuration for event ERROR */
9392 
9393 /* Bit 31 :   */
9394 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
9395 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
9396 #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
9397 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
9398 
9399 /* Bits 3..0 : Channel that event ERROR will publish to. */
9400 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9401 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9402 
9403 /* Register: TWIS_PUBLISH_RXSTARTED */
9404 /* Description: Publish configuration for event RXSTARTED */
9405 
9406 /* Bit 31 :   */
9407 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
9408 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
9409 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9410 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9411 
9412 /* Bits 3..0 : Channel that event RXSTARTED will publish to. */
9413 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9414 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9415 
9416 /* Register: TWIS_PUBLISH_TXSTARTED */
9417 /* Description: Publish configuration for event TXSTARTED */
9418 
9419 /* Bit 31 :   */
9420 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
9421 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
9422 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
9423 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9424 
9425 /* Bits 3..0 : Channel that event TXSTARTED will publish to. */
9426 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9427 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9428 
9429 /* Register: TWIS_PUBLISH_WRITE */
9430 /* Description: Publish configuration for event WRITE */
9431 
9432 /* Bit 31 :   */
9433 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */
9434 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */
9435 #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */
9436 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
9437 
9438 /* Bits 3..0 : Channel that event WRITE will publish to. */
9439 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9440 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9441 
9442 /* Register: TWIS_PUBLISH_READ */
9443 /* Description: Publish configuration for event READ */
9444 
9445 /* Bit 31 :   */
9446 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */
9447 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */
9448 #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */
9449 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
9450 
9451 /* Bits 3..0 : Channel that event READ will publish to. */
9452 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9453 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9454 
9455 /* Register: TWIS_SHORTS */
9456 /* Description: Shortcuts between local events and tasks */
9457 
9458 /* Bit 14 : Shortcut between event READ and task SUSPEND */
9459 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
9460 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
9461 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9462 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9463 
9464 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
9465 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
9466 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
9467 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9468 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9469 
9470 /* Register: TWIS_INTEN */
9471 /* Description: Enable or disable interrupt */
9472 
9473 /* Bit 26 : Enable or disable interrupt for event READ */
9474 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
9475 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
9476 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
9477 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9478 
9479 /* Bit 25 : Enable or disable interrupt for event WRITE */
9480 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9481 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
9482 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
9483 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9484 
9485 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9486 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9487 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9488 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9489 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9490 
9491 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9492 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9493 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9494 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9495 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9496 
9497 /* Bit 9 : Enable or disable interrupt for event ERROR */
9498 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9499 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
9500 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9501 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9502 
9503 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9504 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9505 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9506 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9507 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9508 
9509 /* Register: TWIS_INTENSET */
9510 /* Description: Enable interrupt */
9511 
9512 /* Bit 26 : Write '1' to enable interrupt for event READ */
9513 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
9514 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
9515 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9516 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9517 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9518 
9519 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
9520 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9521 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
9522 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9523 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9524 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9525 
9526 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9527 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9528 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9529 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9530 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9531 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9532 
9533 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9534 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9535 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9536 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9537 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9538 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9539 
9540 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9541 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9542 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9543 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9544 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9545 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
9546 
9547 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9548 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9549 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9550 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9551 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9552 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9553 
9554 /* Register: TWIS_INTENCLR */
9555 /* Description: Disable interrupt */
9556 
9557 /* Bit 26 : Write '1' to disable interrupt for event READ */
9558 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
9559 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
9560 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9561 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9562 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
9563 
9564 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
9565 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9566 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
9567 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9568 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9569 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
9570 
9571 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9572 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9573 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9574 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9575 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9576 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9577 
9578 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9579 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9580 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9581 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9582 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9583 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9584 
9585 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9586 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9587 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9588 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9589 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9590 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9591 
9592 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9593 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9594 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9595 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9596 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9597 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9598 
9599 /* Register: TWIS_ERRORSRC */
9600 /* Description: Error source */
9601 
9602 /* Bit 3 : TX buffer over-read detected, and prevented */
9603 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
9604 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
9605 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
9606 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
9607 
9608 /* Bit 2 : NACK sent after receiving a data byte */
9609 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9610 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9611 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9612 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9613 
9614 /* Bit 0 : RX buffer overflow detected, and prevented */
9615 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
9616 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
9617 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
9618 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
9619 
9620 /* Register: TWIS_MATCH */
9621 /* Description: Status register indicating which address had a match */
9622 
9623 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
9624 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
9625 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
9626 
9627 /* Register: TWIS_ENABLE */
9628 /* Description: Enable TWIS */
9629 
9630 /* Bits 3..0 : Enable or disable TWIS */
9631 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9632 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9633 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
9634 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
9635 
9636 /* Register: TWIS_PSEL_SCL */
9637 /* Description: Pin select for SCL signal */
9638 
9639 /* Bit 31 : Connection */
9640 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9641 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9642 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9643 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9644 
9645 /* Bits 4..0 : Pin number */
9646 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9647 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9648 
9649 /* Register: TWIS_PSEL_SDA */
9650 /* Description: Pin select for SDA signal */
9651 
9652 /* Bit 31 : Connection */
9653 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9654 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9655 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9656 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9657 
9658 /* Bits 4..0 : Pin number */
9659 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9660 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9661 
9662 /* Register: TWIS_RXD_PTR */
9663 /* Description: RXD Data pointer */
9664 
9665 /* Bits 31..0 : RXD Data pointer */
9666 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9667 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9668 
9669 /* Register: TWIS_RXD_MAXCNT */
9670 /* Description: Maximum number of bytes in RXD buffer */
9671 
9672 /* Bits 12..0 : Maximum number of bytes in RXD buffer */
9673 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9674 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9675 
9676 /* Register: TWIS_RXD_AMOUNT */
9677 /* Description: Number of bytes transferred in the last RXD transaction */
9678 
9679 /* Bits 12..0 : Number of bytes transferred in the last RXD transaction */
9680 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9681 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9682 
9683 /* Register: TWIS_TXD_PTR */
9684 /* Description: TXD Data pointer */
9685 
9686 /* Bits 31..0 : TXD Data pointer */
9687 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9688 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9689 
9690 /* Register: TWIS_TXD_MAXCNT */
9691 /* Description: Maximum number of bytes in TXD buffer */
9692 
9693 /* Bits 12..0 : Maximum number of bytes in TXD buffer */
9694 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9695 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9696 
9697 /* Register: TWIS_TXD_AMOUNT */
9698 /* Description: Number of bytes transferred in the last TXD transaction */
9699 
9700 /* Bits 12..0 : Number of bytes transferred in the last TXD transaction */
9701 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9702 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9703 
9704 /* Register: TWIS_ADDRESS */
9705 /* Description: Description collection: TWI slave address n */
9706 
9707 /* Bits 6..0 : TWI slave address */
9708 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9709 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9710 
9711 /* Register: TWIS_CONFIG */
9712 /* Description: Configuration register for the address match mechanism */
9713 
9714 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9715 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
9716 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
9717 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
9718 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
9719 
9720 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
9721 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
9722 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
9723 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
9724 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
9725 
9726 /* Register: TWIS_ORC */
9727 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
9728 
9729 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
9730 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
9731 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
9732 
9733 
9734 /* Peripheral: UARTE */
9735 /* Description: UART with EasyDMA 0 */
9736 
9737 /* Register: UARTE_TASKS_STARTRX */
9738 /* Description: Start UART receiver */
9739 
9740 /* Bit 0 : Start UART receiver */
9741 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
9742 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
9743 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9744 
9745 /* Register: UARTE_TASKS_STOPRX */
9746 /* Description: Stop UART receiver */
9747 
9748 /* Bit 0 : Stop UART receiver */
9749 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
9750 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
9751 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
9752 
9753 /* Register: UARTE_TASKS_STARTTX */
9754 /* Description: Start UART transmitter */
9755 
9756 /* Bit 0 : Start UART transmitter */
9757 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
9758 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
9759 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9760 
9761 /* Register: UARTE_TASKS_STOPTX */
9762 /* Description: Stop UART transmitter */
9763 
9764 /* Bit 0 : Stop UART transmitter */
9765 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
9766 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
9767 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
9768 
9769 /* Register: UARTE_TASKS_FLUSHRX */
9770 /* Description: Flush RX FIFO into RX buffer */
9771 
9772 /* Bit 0 : Flush RX FIFO into RX buffer */
9773 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
9774 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
9775 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
9776 
9777 /* Register: UARTE_SUBSCRIBE_STARTRX */
9778 /* Description: Subscribe configuration for task STARTRX */
9779 
9780 /* Bit 31 :   */
9781 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */
9782 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */
9783 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */
9784 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
9785 
9786 /* Bits 3..0 : Channel that task STARTRX will subscribe to */
9787 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9788 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9789 
9790 /* Register: UARTE_SUBSCRIBE_STOPRX */
9791 /* Description: Subscribe configuration for task STOPRX */
9792 
9793 /* Bit 31 :   */
9794 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */
9795 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */
9796 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */
9797 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
9798 
9799 /* Bits 3..0 : Channel that task STOPRX will subscribe to */
9800 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9801 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9802 
9803 /* Register: UARTE_SUBSCRIBE_STARTTX */
9804 /* Description: Subscribe configuration for task STARTTX */
9805 
9806 /* Bit 31 :   */
9807 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */
9808 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */
9809 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */
9810 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
9811 
9812 /* Bits 3..0 : Channel that task STARTTX will subscribe to */
9813 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9814 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9815 
9816 /* Register: UARTE_SUBSCRIBE_STOPTX */
9817 /* Description: Subscribe configuration for task STOPTX */
9818 
9819 /* Bit 31 :   */
9820 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */
9821 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */
9822 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */
9823 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
9824 
9825 /* Bits 3..0 : Channel that task STOPTX will subscribe to */
9826 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9827 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9828 
9829 /* Register: UARTE_SUBSCRIBE_FLUSHRX */
9830 /* Description: Subscribe configuration for task FLUSHRX */
9831 
9832 /* Bit 31 :   */
9833 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */
9834 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */
9835 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */
9836 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
9837 
9838 /* Bits 3..0 : Channel that task FLUSHRX will subscribe to */
9839 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9840 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9841 
9842 /* Register: UARTE_EVENTS_CTS */
9843 /* Description: CTS is activated (set low). Clear To Send. */
9844 
9845 /* Bit 0 : CTS is activated (set low). Clear To Send. */
9846 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
9847 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
9848 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
9849 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
9850 
9851 /* Register: UARTE_EVENTS_NCTS */
9852 /* Description: CTS is deactivated (set high). Not Clear To Send. */
9853 
9854 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
9855 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
9856 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
9857 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
9858 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
9859 
9860 /* Register: UARTE_EVENTS_RXDRDY */
9861 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
9862 
9863 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
9864 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
9865 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
9866 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
9867 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
9868 
9869 /* Register: UARTE_EVENTS_ENDRX */
9870 /* Description: Receive buffer is filled up */
9871 
9872 /* Bit 0 : Receive buffer is filled up */
9873 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
9874 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
9875 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
9876 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
9877 
9878 /* Register: UARTE_EVENTS_TXDRDY */
9879 /* Description: Data sent from TXD */
9880 
9881 /* Bit 0 : Data sent from TXD */
9882 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
9883 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
9884 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
9885 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
9886 
9887 /* Register: UARTE_EVENTS_ENDTX */
9888 /* Description: Last TX byte transmitted */
9889 
9890 /* Bit 0 : Last TX byte transmitted */
9891 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
9892 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
9893 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
9894 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
9895 
9896 /* Register: UARTE_EVENTS_ERROR */
9897 /* Description: Error detected */
9898 
9899 /* Bit 0 : Error detected */
9900 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9901 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9902 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9903 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9904 
9905 /* Register: UARTE_EVENTS_RXTO */
9906 /* Description: Receiver timeout */
9907 
9908 /* Bit 0 : Receiver timeout */
9909 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
9910 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
9911 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
9912 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
9913 
9914 /* Register: UARTE_EVENTS_RXSTARTED */
9915 /* Description: UART receiver has started */
9916 
9917 /* Bit 0 : UART receiver has started */
9918 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
9919 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
9920 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9921 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9922 
9923 /* Register: UARTE_EVENTS_TXSTARTED */
9924 /* Description: UART transmitter has started */
9925 
9926 /* Bit 0 : UART transmitter has started */
9927 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
9928 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
9929 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9930 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9931 
9932 /* Register: UARTE_EVENTS_TXSTOPPED */
9933 /* Description: Transmitter stopped */
9934 
9935 /* Bit 0 : Transmitter stopped */
9936 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
9937 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
9938 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
9939 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
9940 
9941 /* Register: UARTE_PUBLISH_CTS */
9942 /* Description: Publish configuration for event CTS */
9943 
9944 /* Bit 31 :   */
9945 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */
9946 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */
9947 #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */
9948 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
9949 
9950 /* Bits 3..0 : Channel that event CTS will publish to. */
9951 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9952 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9953 
9954 /* Register: UARTE_PUBLISH_NCTS */
9955 /* Description: Publish configuration for event NCTS */
9956 
9957 /* Bit 31 :   */
9958 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */
9959 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */
9960 #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */
9961 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
9962 
9963 /* Bits 3..0 : Channel that event NCTS will publish to. */
9964 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9965 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9966 
9967 /* Register: UARTE_PUBLISH_RXDRDY */
9968 /* Description: Publish configuration for event RXDRDY */
9969 
9970 /* Bit 31 :   */
9971 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
9972 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */
9973 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
9974 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
9975 
9976 /* Bits 3..0 : Channel that event RXDRDY will publish to. */
9977 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9978 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9979 
9980 /* Register: UARTE_PUBLISH_ENDRX */
9981 /* Description: Publish configuration for event ENDRX */
9982 
9983 /* Bit 31 :   */
9984 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */
9985 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */
9986 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */
9987 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
9988 
9989 /* Bits 3..0 : Channel that event ENDRX will publish to. */
9990 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
9991 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
9992 
9993 /* Register: UARTE_PUBLISH_TXDRDY */
9994 /* Description: Publish configuration for event TXDRDY */
9995 
9996 /* Bit 31 :   */
9997 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */
9998 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */
9999 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */
10000 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
10001 
10002 /* Bits 3..0 : Channel that event TXDRDY will publish to. */
10003 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10004 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10005 
10006 /* Register: UARTE_PUBLISH_ENDTX */
10007 /* Description: Publish configuration for event ENDTX */
10008 
10009 /* Bit 31 :   */
10010 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */
10011 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */
10012 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */
10013 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
10014 
10015 /* Bits 3..0 : Channel that event ENDTX will publish to. */
10016 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10017 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10018 
10019 /* Register: UARTE_PUBLISH_ERROR */
10020 /* Description: Publish configuration for event ERROR */
10021 
10022 /* Bit 31 :   */
10023 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
10024 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
10025 #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
10026 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
10027 
10028 /* Bits 3..0 : Channel that event ERROR will publish to. */
10029 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10030 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10031 
10032 /* Register: UARTE_PUBLISH_RXTO */
10033 /* Description: Publish configuration for event RXTO */
10034 
10035 /* Bit 31 :   */
10036 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */
10037 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */
10038 #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */
10039 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
10040 
10041 /* Bits 3..0 : Channel that event RXTO will publish to. */
10042 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10043 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10044 
10045 /* Register: UARTE_PUBLISH_RXSTARTED */
10046 /* Description: Publish configuration for event RXSTARTED */
10047 
10048 /* Bit 31 :   */
10049 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
10050 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
10051 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10052 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10053 
10054 /* Bits 3..0 : Channel that event RXSTARTED will publish to. */
10055 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10056 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10057 
10058 /* Register: UARTE_PUBLISH_TXSTARTED */
10059 /* Description: Publish configuration for event TXSTARTED */
10060 
10061 /* Bit 31 :   */
10062 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
10063 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */
10064 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
10065 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10066 
10067 /* Bits 3..0 : Channel that event TXSTARTED will publish to. */
10068 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10069 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10070 
10071 /* Register: UARTE_PUBLISH_TXSTOPPED */
10072 /* Description: Publish configuration for event TXSTOPPED */
10073 
10074 /* Bit 31 :   */
10075 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
10076 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
10077 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
10078 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
10079 
10080 /* Bits 3..0 : Channel that event TXSTOPPED will publish to. */
10081 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10082 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10083 
10084 /* Register: UARTE_SHORTS */
10085 /* Description: Shortcuts between local events and tasks */
10086 
10087 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
10088 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
10089 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
10090 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
10091 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10092 
10093 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
10094 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
10095 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
10096 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10097 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10098 
10099 /* Register: UARTE_INTEN */
10100 /* Description: Enable or disable interrupt */
10101 
10102 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
10103 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10104 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10105 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
10106 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
10107 
10108 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10109 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10110 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10111 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
10112 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10113 
10114 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10115 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10116 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10117 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
10118 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10119 
10120 /* Bit 17 : Enable or disable interrupt for event RXTO */
10121 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10122 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
10123 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
10124 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
10125 
10126 /* Bit 9 : Enable or disable interrupt for event ERROR */
10127 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10128 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
10129 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
10130 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10131 
10132 /* Bit 8 : Enable or disable interrupt for event ENDTX */
10133 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10134 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10135 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
10136 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
10137 
10138 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
10139 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10140 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10141 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
10142 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
10143 
10144 /* Bit 4 : Enable or disable interrupt for event ENDRX */
10145 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10146 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10147 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
10148 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
10149 
10150 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10151 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10152 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10153 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
10154 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
10155 
10156 /* Bit 1 : Enable or disable interrupt for event NCTS */
10157 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10158 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
10159 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
10160 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
10161 
10162 /* Bit 0 : Enable or disable interrupt for event CTS */
10163 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
10164 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
10165 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
10166 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
10167 
10168 /* Register: UARTE_INTENSET */
10169 /* Description: Enable interrupt */
10170 
10171 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
10172 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10173 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10174 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10175 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10176 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
10177 
10178 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10179 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10180 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10181 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10182 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10183 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10184 
10185 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10186 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10187 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10188 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10189 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10190 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10191 
10192 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10193 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10194 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
10195 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10196 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10197 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
10198 
10199 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10200 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10201 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10202 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10203 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10204 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
10205 
10206 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
10207 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10208 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10209 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10210 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10211 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10212 
10213 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10214 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10215 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10216 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10217 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10218 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10219 
10220 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
10221 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10222 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10223 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10224 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10225 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10226 
10227 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10228 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10229 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10230 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10231 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10232 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10233 
10234 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10235 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10236 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
10237 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10238 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10239 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
10240 
10241 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10242 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
10243 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
10244 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10245 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10246 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
10247 
10248 /* Register: UARTE_INTENCLR */
10249 /* Description: Disable interrupt */
10250 
10251 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
10252 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10253 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10254 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10255 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10256 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
10257 
10258 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10259 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10260 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10261 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10262 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10263 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10264 
10265 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10266 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10267 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10268 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10269 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10270 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10271 
10272 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10273 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10274 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
10275 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10276 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10277 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10278 
10279 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10280 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10281 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10282 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10283 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10284 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10285 
10286 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
10287 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10288 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10289 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10290 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10291 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10292 
10293 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10294 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10295 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10296 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10297 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10298 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10299 
10300 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
10301 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10302 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10303 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10304 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10305 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10306 
10307 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10308 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10309 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10310 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10311 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10312 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10313 
10314 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10315 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10316 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
10317 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10318 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10319 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10320 
10321 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10322 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
10323 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
10324 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10325 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10326 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10327 
10328 /* Register: UARTE_ERRORSRC */
10329 /* Description: Error source Note : this register is read / write one to clear. */
10330 
10331 /* Bit 3 : Break condition */
10332 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
10333 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
10334 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
10335 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10336 
10337 /* Bit 2 : Framing error occurred */
10338 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10339 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
10340 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
10341 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10342 
10343 /* Bit 1 : Parity error */
10344 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10345 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
10346 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
10347 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10348 
10349 /* Bit 0 : Overrun error */
10350 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
10351 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
10352 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
10353 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10354 
10355 /* Register: UARTE_ENABLE */
10356 /* Description: Enable UART */
10357 
10358 /* Bits 3..0 : Enable or disable UARTE */
10359 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10360 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10361 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
10362 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
10363 
10364 /* Register: UARTE_PSEL_RTS */
10365 /* Description: Pin select for RTS signal */
10366 
10367 /* Bit 31 : Connection */
10368 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10369 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10370 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
10371 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10372 
10373 /* Bits 4..0 : Pin number */
10374 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10375 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
10376 
10377 /* Register: UARTE_PSEL_TXD */
10378 /* Description: Pin select for TXD signal */
10379 
10380 /* Bit 31 : Connection */
10381 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10382 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10383 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
10384 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10385 
10386 /* Bits 4..0 : Pin number */
10387 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10388 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
10389 
10390 /* Register: UARTE_PSEL_CTS */
10391 /* Description: Pin select for CTS signal */
10392 
10393 /* Bit 31 : Connection */
10394 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10395 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10396 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
10397 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10398 
10399 /* Bits 4..0 : Pin number */
10400 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10401 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
10402 
10403 /* Register: UARTE_PSEL_RXD */
10404 /* Description: Pin select for RXD signal */
10405 
10406 /* Bit 31 : Connection */
10407 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10408 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10409 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
10410 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10411 
10412 /* Bits 4..0 : Pin number */
10413 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10414 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
10415 
10416 /* Register: UARTE_BAUDRATE */
10417 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
10418 
10419 /* Bits 31..0 : Baud rate */
10420 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
10421 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
10422 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
10423 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
10424 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
10425 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
10426 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
10427 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
10428 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
10429 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
10430 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
10431 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
10432 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
10433 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
10434 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
10435 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
10436 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
10437 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
10438 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
10439 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
10440 
10441 /* Register: UARTE_RXD_PTR */
10442 /* Description: Data pointer */
10443 
10444 /* Bits 31..0 : Data pointer */
10445 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10446 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10447 
10448 /* Register: UARTE_RXD_MAXCNT */
10449 /* Description: Maximum number of bytes in receive buffer */
10450 
10451 /* Bits 12..0 : Maximum number of bytes in receive buffer */
10452 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10453 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10454 
10455 /* Register: UARTE_RXD_AMOUNT */
10456 /* Description: Number of bytes transferred in the last transaction */
10457 
10458 /* Bits 12..0 : Number of bytes transferred in the last transaction */
10459 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10460 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10461 
10462 /* Register: UARTE_TXD_PTR */
10463 /* Description: Data pointer */
10464 
10465 /* Bits 31..0 : Data pointer */
10466 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10467 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10468 
10469 /* Register: UARTE_TXD_MAXCNT */
10470 /* Description: Maximum number of bytes in transmit buffer */
10471 
10472 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
10473 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10474 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10475 
10476 /* Register: UARTE_TXD_AMOUNT */
10477 /* Description: Number of bytes transferred in the last transaction */
10478 
10479 /* Bits 12..0 : Number of bytes transferred in the last transaction */
10480 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10481 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10482 
10483 /* Register: UARTE_CONFIG */
10484 /* Description: Configuration of parity and hardware flow control */
10485 
10486 /* Bit 4 : Stop bits */
10487 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
10488 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
10489 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
10490 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
10491 
10492 /* Bits 3..1 : Parity */
10493 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10494 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
10495 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
10496 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
10497 
10498 /* Bit 0 : Hardware flow control */
10499 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
10500 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
10501 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
10502 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10503 
10504 
10505 /* Peripheral: UICR */
10506 /* Description: User information configuration registers User information configuration registers */
10507 
10508 /* Register: UICR_APPROTECT */
10509 /* Description: Access port protection */
10510 
10511 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
10512           memory mapped addresses */
10513 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10514 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10515 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
10516 #define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
10517 
10518 /* Register: UICR_XOSC32M */
10519 /* Description: Oscillator control */
10520 
10521 /* Bits 5..0 : Pierce current DAC control signals */
10522 #define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */
10523 #define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */
10524 
10525 /* Register: UICR_HFXOSRC */
10526 /* Description: HFXO clock source selection */
10527 
10528 /* Bit 0 : HFXO clock source selection */
10529 #define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */
10530 #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */
10531 #define UICR_HFXOSRC_HFXOSRC_TCXO (0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */
10532 #define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */
10533 
10534 /* Register: UICR_HFXOCNT */
10535 /* Description: HFXO startup counter */
10536 
10537 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
10538 #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */
10539 #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */
10540 #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */
10541 #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */
10542 
10543 /* Register: UICR_SECUREAPPROTECT */
10544 /* Description: Secure access port protection */
10545 
10546 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure
10547           memory mapped addresses */
10548 #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10549 #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10550 #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
10551 #define UICR_SECUREAPPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
10552 
10553 /* Register: UICR_ERASEPROTECT */
10554 /* Description: Erase protection */
10555 
10556 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */
10557 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
10558 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
10559 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */
10560 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */
10561 
10562 /* Register: UICR_OTP */
10563 /* Description: Description collection: OTP bits [31+n*32:0+n*32]. */
10564 
10565 /* Bits 31..0 : Bits [31+n*32:0+n*32] of OTP region */
10566 #define UICR_OTP_OTP_Pos (0UL) /*!< Position of OTP field. */
10567 #define UICR_OTP_OTP_Msk (0xFFFFFFFFUL << UICR_OTP_OTP_Pos) /*!< Bit mask of OTP field. */
10568 
10569 /* Register: UICR_KEYSLOT_CONFIG_DEST */
10570 /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3])
10571           will be pushed by KMU. Note that this address MUST match that of a peripherals
10572           APB mapped write-only key registers, else the KMU can push this key value into
10573           an address range which the CPU can potentially read! */
10574 
10575 /* Bits 31..0 : Secure APB destination address */
10576 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */
10577 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */
10578 
10579 /* Register: UICR_KEYSLOT_CONFIG_PERM */
10580 /* Description: Description cluster: Define permissions for the key slot with ID=n+1. Bits 0-15 and 16-31 can only be written once. */
10581 
10582 /* Bit 16 : Revocation state for the key slot */
10583 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */
10584 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */
10585 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */
10586 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */
10587 
10588 /* Bit 2 : Push permission for key slot */
10589 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */
10590 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */
10591 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
10592 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */
10593 
10594 /* Bit 1 : Read permission for key slot */
10595 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
10596 #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */
10597 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */
10598 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
10599 
10600 /* Bit 0 : Write permission for key slot */
10601 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */
10602 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
10603 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */
10604 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
10605 
10606 /* Register: UICR_KEYSLOT_KEY_VALUE */
10607 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
10608 
10609 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
10610 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
10611 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
10612 
10613 
10614 /* Peripheral: VMC */
10615 /* Description: Volatile Memory controller 0 */
10616 
10617 /* Register: VMC_RAM_POWER */
10618 /* Description: Description cluster: RAMn power control register */
10619 
10620 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
10621 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
10622 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
10623 #define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
10624 #define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
10625 
10626 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
10627 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
10628 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
10629 #define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
10630 #define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
10631 
10632 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
10633 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
10634 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
10635 #define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
10636 #define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
10637 
10638 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
10639 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
10640 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
10641 #define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
10642 #define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
10643 
10644 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
10645 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
10646 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
10647 #define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
10648 #define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */
10649 
10650 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10651 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10652 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
10653 #define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
10654 #define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */
10655 
10656 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10657 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10658 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
10659 #define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
10660 #define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */
10661 
10662 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
10663 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
10664 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
10665 #define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
10666 #define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */
10667 
10668 /* Register: VMC_RAM_POWERSET */
10669 /* Description: Description cluster: RAMn power control set register */
10670 
10671 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
10672 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
10673 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
10674 #define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
10675 
10676 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
10677 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
10678 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
10679 #define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
10680 
10681 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
10682 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
10683 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
10684 #define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
10685 
10686 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
10687 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
10688 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
10689 #define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
10690 
10691 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
10692 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
10693 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
10694 #define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
10695 
10696 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10697 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10698 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
10699 #define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
10700 
10701 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10702 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10703 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
10704 #define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
10705 
10706 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
10707 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
10708 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
10709 #define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
10710 
10711 /* Register: VMC_RAM_POWERCLR */
10712 /* Description: Description cluster: RAMn power control clear register */
10713 
10714 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */
10715 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
10716 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
10717 #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
10718 
10719 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */
10720 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
10721 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
10722 #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
10723 
10724 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */
10725 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
10726 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
10727 #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
10728 
10729 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */
10730 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
10731 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
10732 #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
10733 
10734 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */
10735 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
10736 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
10737 #define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
10738 
10739 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */
10740 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
10741 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
10742 #define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
10743 
10744 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10745 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10746 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
10747 #define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
10748 
10749 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */
10750 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
10751 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
10752 #define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
10753 
10754 
10755 /* Peripheral: WDT */
10756 /* Description: Watchdog Timer 0 */
10757 
10758 /* Register: WDT_TASKS_START */
10759 /* Description: Start the watchdog */
10760 
10761 /* Bit 0 : Start the watchdog */
10762 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
10763 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
10764 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10765 
10766 /* Register: WDT_SUBSCRIBE_START */
10767 /* Description: Subscribe configuration for task START */
10768 
10769 /* Bit 31 :   */
10770 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
10771 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
10772 #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
10773 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
10774 
10775 /* Bits 3..0 : Channel that task START will subscribe to */
10776 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10777 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10778 
10779 /* Register: WDT_EVENTS_TIMEOUT */
10780 /* Description: Watchdog timeout */
10781 
10782 /* Bit 0 : Watchdog timeout */
10783 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
10784 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
10785 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
10786 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
10787 
10788 /* Register: WDT_PUBLISH_TIMEOUT */
10789 /* Description: Publish configuration for event TIMEOUT */
10790 
10791 /* Bit 31 :   */
10792 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */
10793 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */
10794 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */
10795 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
10796 
10797 /* Bits 3..0 : Channel that event TIMEOUT will publish to. */
10798 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
10799 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
10800 
10801 /* Register: WDT_INTENSET */
10802 /* Description: Enable interrupt */
10803 
10804 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
10805 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
10806 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
10807 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10808 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10809 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
10810 
10811 /* Register: WDT_INTENCLR */
10812 /* Description: Disable interrupt */
10813 
10814 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
10815 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
10816 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
10817 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10818 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10819 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
10820 
10821 /* Register: WDT_RUNSTATUS */
10822 /* Description: Run status */
10823 
10824 /* Bit 0 : Indicates whether or not the watchdog is running */
10825 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */
10826 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */
10827 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */
10828 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */
10829 
10830 /* Register: WDT_REQSTATUS */
10831 /* Description: Request status */
10832 
10833 /* Bit 7 : Request status for RR[7] register */
10834 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
10835 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
10836 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
10837 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
10838 
10839 /* Bit 6 : Request status for RR[6] register */
10840 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
10841 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
10842 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
10843 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
10844 
10845 /* Bit 5 : Request status for RR[5] register */
10846 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
10847 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
10848 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
10849 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
10850 
10851 /* Bit 4 : Request status for RR[4] register */
10852 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
10853 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
10854 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
10855 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
10856 
10857 /* Bit 3 : Request status for RR[3] register */
10858 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
10859 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
10860 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
10861 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
10862 
10863 /* Bit 2 : Request status for RR[2] register */
10864 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
10865 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
10866 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
10867 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
10868 
10869 /* Bit 1 : Request status for RR[1] register */
10870 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
10871 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
10872 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
10873 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
10874 
10875 /* Bit 0 : Request status for RR[0] register */
10876 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
10877 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
10878 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
10879 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
10880 
10881 /* Register: WDT_CRV */
10882 /* Description: Counter reload value */
10883 
10884 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
10885 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
10886 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
10887 
10888 /* Register: WDT_RREN */
10889 /* Description: Enable register for reload request registers */
10890 
10891 /* Bit 7 : Enable or disable RR[7] register */
10892 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
10893 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
10894 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
10895 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
10896 
10897 /* Bit 6 : Enable or disable RR[6] register */
10898 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
10899 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
10900 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
10901 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
10902 
10903 /* Bit 5 : Enable or disable RR[5] register */
10904 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
10905 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
10906 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
10907 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
10908 
10909 /* Bit 4 : Enable or disable RR[4] register */
10910 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
10911 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
10912 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
10913 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
10914 
10915 /* Bit 3 : Enable or disable RR[3] register */
10916 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
10917 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
10918 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
10919 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
10920 
10921 /* Bit 2 : Enable or disable RR[2] register */
10922 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
10923 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
10924 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
10925 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
10926 
10927 /* Bit 1 : Enable or disable RR[1] register */
10928 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
10929 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
10930 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
10931 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
10932 
10933 /* Bit 0 : Enable or disable RR[0] register */
10934 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
10935 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
10936 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
10937 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
10938 
10939 /* Register: WDT_CONFIG */
10940 /* Description: Configuration register */
10941 
10942 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
10943 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
10944 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
10945 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
10946 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
10947 
10948 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
10949 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
10950 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
10951 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
10952 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
10953 
10954 /* Register: WDT_RR */
10955 /* Description: Description collection: Reload request n */
10956 
10957 /* Bits 31..0 : Reload request register */
10958 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
10959 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
10960 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
10961 
10962 
10963 /*lint --flb "Leave library region" */
10964 #endif
10965