1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf9160.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 03. December 2018 34 * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:26 35 * from File 'nrf9160.svd', 36 * last modified on Monday, 03.12.2018 10:18:21 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf9160 47 * @{ 48 */ 49 50 51 #ifndef NRF9160_H 52 #define NRF9160_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 80 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 81 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 82 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 83 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 84 /* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */ 85 SPU_IRQn = 3, /*!< 3 SPU */ 86 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 87 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8, /*!< 8 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 */ 88 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9, /*!< 9 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 */ 89 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10, /*!< 10 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 */ 90 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11, /*!< 11 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 */ 91 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 92 SAADC_IRQn = 14, /*!< 14 SAADC */ 93 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 94 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 95 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 96 RTC0_IRQn = 20, /*!< 20 RTC0 */ 97 RTC1_IRQn = 21, /*!< 21 RTC1 */ 98 WDT_IRQn = 24, /*!< 24 WDT */ 99 EGU0_IRQn = 27, /*!< 27 EGU0 */ 100 EGU1_IRQn = 28, /*!< 28 EGU1 */ 101 EGU2_IRQn = 29, /*!< 29 EGU2 */ 102 EGU3_IRQn = 30, /*!< 30 EGU3 */ 103 EGU4_IRQn = 31, /*!< 31 EGU4 */ 104 EGU5_IRQn = 32, /*!< 32 EGU5 */ 105 PWM0_IRQn = 33, /*!< 33 PWM0 */ 106 PWM1_IRQn = 34, /*!< 34 PWM1 */ 107 PWM2_IRQn = 35, /*!< 35 PWM2 */ 108 PWM3_IRQn = 36, /*!< 36 PWM3 */ 109 PDM_IRQn = 38, /*!< 38 PDM */ 110 I2S_IRQn = 40, /*!< 40 I2S */ 111 IPC_IRQn = 42, /*!< 42 IPC */ 112 FPU_IRQn = 44, /*!< 44 FPU */ 113 GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 114 KMU_IRQn = 57, /*!< 57 KMU */ 115 CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 116 } IRQn_Type; 117 118 119 120 /* =========================================================================================================================== */ 121 /* ================ Processor and Core Peripheral Section ================ */ 122 /* =========================================================================================================================== */ 123 124 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 125 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 126 #define __DSP_PRESENT 1 /*!< DSP present or not */ 127 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 128 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 129 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 130 #define __MPU_PRESENT 1 /*!< MPU present or not */ 131 #define __FPU_PRESENT 1 /*!< FPU present or not */ 132 #define __FPU_DP 0 /*!< Double Precision FPU */ 133 #define __SAU_REGION_PRESENT 0 /*!< SAU present or not */ 134 135 136 /** @} */ /* End of group Configuration_of_CMSIS */ 137 138 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 139 #include "system_nrf9160.h" /*!< nrf9160 System */ 140 141 #ifndef __IM /*!< Fallback for older CMSIS versions */ 142 #define __IM __I 143 #endif 144 #ifndef __OM /*!< Fallback for older CMSIS versions */ 145 #define __OM __O 146 #endif 147 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 148 #define __IOM __IO 149 #endif 150 151 152 /* =========================================================================================================================== */ 153 /* ================ Device Specific Cluster Section ================ */ 154 /* =========================================================================================================================== */ 155 156 157 /** @addtogroup Device_Peripheral_clusters 158 * @{ 159 */ 160 161 162 /** 163 * @brief FICR_INFO [INFO] (Device info) 164 */ 165 typedef struct { 166 __IM uint32_t RESERVED; 167 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 168 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 169 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 170 configuration */ 171 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 172 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 173 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 174 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 175 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 176 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 177 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 178 179 180 /** 181 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 182 */ 183 typedef struct { 184 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 185 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 186 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 187 188 189 /** 190 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 191 */ 192 typedef struct { 193 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 194 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 195 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 196 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 197 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 198 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 199 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 200 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 201 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 202 203 204 /** 205 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 206 */ 207 typedef struct { 208 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 209 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 210 ) will be pushed by KMU. Note that this 211 address MUST match that of a peripherals 212 APB mapped write-only key registers, else 213 the KMU can push this key value into an 214 address range which the CPU can potentially 215 read! */ 216 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 217 key slot with ID=n+1. Bits 0-15 and 16-31 218 can only be written once. */ 219 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 220 221 222 /** 223 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 224 */ 225 typedef struct { 226 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 227 of value assigned to KMU key slot ID=n+1 */ 228 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 229 230 231 /** 232 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 233 */ 234 typedef struct { 235 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 236 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 237 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 238 239 240 /** 241 * @brief TAD_PSEL [PSEL] (Unspecified) 242 */ 243 typedef struct { 244 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin number configuration for TRACECLK */ 245 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin number configuration for TRACEDATA[0] */ 246 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin number configuration for TRACEDATA[1] */ 247 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin number configuration for TRACEDATA[2] */ 248 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin number configuration for TRACEDATA[3] */ 249 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 250 251 252 /** 253 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 254 */ 255 typedef struct { 256 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 257 from the external domain n List capabilities 258 of the external domain n */ 259 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 260 261 262 /** 263 * @brief SPU_DPPI [DPPI] (Unspecified) 264 */ 265 typedef struct { 266 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 267 non-secure attribute for the DPPI channels. */ 268 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 269 of the corresponding PERM register */ 270 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 271 272 273 /** 274 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 275 */ 276 typedef struct { 277 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 278 non-secure attribute for pins 0 to 31 of 279 port n. */ 280 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 281 of the corresponding PERM register */ 282 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 283 284 285 /** 286 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 287 */ 288 typedef struct { 289 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 290 can contain the non-secure callable (NSC) 291 region n */ 292 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 293 callable (NSC) region n */ 294 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 295 296 297 /** 298 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 299 */ 300 typedef struct { 301 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 302 can contain the non-secure callable (NSC) 303 region n */ 304 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 305 callable (NSC) region n */ 306 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 307 308 309 /** 310 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 311 */ 312 typedef struct { 313 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 314 region n */ 315 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 316 317 318 /** 319 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 320 */ 321 typedef struct { 322 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 323 region n */ 324 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 325 326 327 /** 328 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 329 */ 330 typedef struct { 331 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 332 permissions for the peripheral with ID n */ 333 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 334 335 336 /** 337 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 338 */ 339 typedef struct { 340 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ 341 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger 342 to the CPU has been read */ 343 __IM uint32_t RESERVED[30]; 344 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ 345 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU 346 to the debugger status has been read */ 347 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 348 349 350 /** 351 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 352 */ 353 typedef struct { 354 __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock ERASEALL mechanism */ 355 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Unlock ERASEPROTECT and perform ERASEALL */ 356 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 357 358 359 /** 360 * @brief SPIM_PSEL [PSEL] (Unspecified) 361 */ 362 typedef struct { 363 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 364 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 365 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 366 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 367 368 369 /** 370 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 371 */ 372 typedef struct { 373 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 374 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 375 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 376 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 377 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 378 379 380 /** 381 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 382 */ 383 typedef struct { 384 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 385 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 386 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 387 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 388 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 389 390 391 /** 392 * @brief SPIS_PSEL [PSEL] (Unspecified) 393 */ 394 typedef struct { 395 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 396 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 397 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 398 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 399 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 400 401 402 /** 403 * @brief SPIS_RXD [RXD] (Unspecified) 404 */ 405 typedef struct { 406 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 407 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 408 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 409 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 410 411 412 /** 413 * @brief SPIS_TXD [TXD] (Unspecified) 414 */ 415 typedef struct { 416 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 417 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 418 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 419 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 420 421 422 /** 423 * @brief TWIM_PSEL [PSEL] (Unspecified) 424 */ 425 typedef struct { 426 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 427 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 428 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 429 430 431 /** 432 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 433 */ 434 typedef struct { 435 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 436 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 437 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 438 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 439 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 440 441 442 /** 443 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 444 */ 445 typedef struct { 446 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 447 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 448 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 449 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 450 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 451 452 453 /** 454 * @brief TWIS_PSEL [PSEL] (Unspecified) 455 */ 456 typedef struct { 457 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 458 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 459 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 460 461 462 /** 463 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 464 */ 465 typedef struct { 466 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 467 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 468 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 469 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 470 471 472 /** 473 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 474 */ 475 typedef struct { 476 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 477 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 478 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 479 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 480 481 482 /** 483 * @brief UARTE_PSEL [PSEL] (Unspecified) 484 */ 485 typedef struct { 486 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 487 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 488 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 489 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 490 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 491 492 493 /** 494 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 495 */ 496 typedef struct { 497 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 498 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 499 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 500 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 501 502 503 /** 504 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 505 */ 506 typedef struct { 507 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 508 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 509 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 510 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 511 512 513 /** 514 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 515 */ 516 typedef struct { 517 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 518 above CH[n].LIMIT.HIGH */ 519 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 520 below CH[n].LIMIT.LOW */ 521 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 522 523 524 /** 525 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 526 */ 527 typedef struct { 528 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 529 event CH[n].LIMITH */ 530 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 531 event CH[n].LIMITL */ 532 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 533 534 535 /** 536 * @brief SAADC_CH [CH] (Unspecified) 537 */ 538 typedef struct { 539 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 540 for CH[n] */ 541 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 542 for CH[n] */ 543 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 544 CH[n] */ 545 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 546 monitoring a channel */ 547 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 548 549 550 /** 551 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 552 */ 553 typedef struct { 554 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 555 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 556 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 557 START */ 558 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 559 560 561 /** 562 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 563 */ 564 typedef struct { 565 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 566 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 567 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 568 569 570 /** 571 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 572 */ 573 typedef struct { 574 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 575 for task CHG[n].EN */ 576 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 577 for task CHG[n].DIS */ 578 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 579 580 581 /** 582 * @brief PWM_SEQ [SEQ] (Unspecified) 583 */ 584 typedef struct { 585 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 586 of this sequence */ 587 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 588 in this sequence */ 589 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 590 periods between samples loaded into compare 591 register */ 592 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 593 __IM uint32_t RESERVED[4]; 594 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 595 596 597 /** 598 * @brief PWM_PSEL [PSEL] (Unspecified) 599 */ 600 typedef struct { 601 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 602 PWM channel n */ 603 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 604 605 606 /** 607 * @brief PDM_PSEL [PSEL] (Unspecified) 608 */ 609 typedef struct { 610 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 611 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 612 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 613 614 615 /** 616 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 617 */ 618 typedef struct { 619 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 620 EasyDMA */ 621 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 622 mode */ 623 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 624 625 626 /** 627 * @brief I2S_CONFIG [CONFIG] (Unspecified) 628 */ 629 typedef struct { 630 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 631 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 632 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 633 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 634 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 635 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 636 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 637 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 638 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 639 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 640 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 641 642 643 /** 644 * @brief I2S_RXD [RXD] (Unspecified) 645 */ 646 typedef struct { 647 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 648 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 649 650 651 /** 652 * @brief I2S_TXD [TXD] (Unspecified) 653 */ 654 typedef struct { 655 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 656 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 657 658 659 /** 660 * @brief I2S_RXTXD [RXTXD] (Unspecified) 661 */ 662 typedef struct { 663 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 664 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 665 666 667 /** 668 * @brief I2S_PSEL [PSEL] (Unspecified) 669 */ 670 typedef struct { 671 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 672 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 673 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 674 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 675 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 676 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 677 678 679 /** 680 * @brief VMC_RAM [RAM] (Unspecified) 681 */ 682 typedef struct { 683 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 684 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 685 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 686 register */ 687 __IM uint32_t RESERVED; 688 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 689 690 691 /** @} */ /* End of group Device_Peripheral_clusters */ 692 693 694 /* =========================================================================================================================== */ 695 /* ================ Device Specific Peripheral Section ================ */ 696 /* =========================================================================================================================== */ 697 698 699 /** @addtogroup Device_Peripheral_peripherals 700 * @{ 701 */ 702 703 704 705 /* =========================================================================================================================== */ 706 /* ================ FICR_S ================ */ 707 /* =========================================================================================================================== */ 708 709 710 /** 711 * @brief Factory Information Configuration Registers (FICR_S) 712 */ 713 714 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 715 __IM uint32_t RESERVED[128]; 716 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 717 __IM uint32_t RESERVED1[53]; 718 __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 719 __IM uint32_t RESERVED2[64]; 720 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 721 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 722 723 724 725 /* =========================================================================================================================== */ 726 /* ================ UICR_S ================ */ 727 /* =========================================================================================================================== */ 728 729 730 /** 731 * @brief User information configuration registers User information configuration registers (UICR_S) 732 */ 733 734 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 735 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 736 __IM uint32_t RESERVED[4]; 737 __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 738 __IM uint32_t RESERVED1; 739 __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 740 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 741 __IM uint32_t RESERVED2[2]; 742 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 743 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 744 __IM uint32_t RESERVED3[53]; 745 __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: OTP bits [31+n*32:0+n*32]. */ 746 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 747 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 748 749 750 751 /* =========================================================================================================================== */ 752 /* ================ TAD_S ================ */ 753 /* =========================================================================================================================== */ 754 755 756 /** 757 * @brief Trace and debug control (TAD_S) 758 */ 759 760 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 761 __IM uint32_t RESERVED[320]; 762 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 763 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 764 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */ 765 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 766 767 768 769 /* =========================================================================================================================== */ 770 /* ================ SPU_S ================ */ 771 /* =========================================================================================================================== */ 772 773 774 /** 775 * @brief System protection unit (SPU_S) 776 */ 777 778 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 779 __IM uint32_t RESERVED[64]; 780 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 781 RAM memory space */ 782 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 783 flash memory space */ 784 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 785 or several peripherals */ 786 __IM uint32_t RESERVED1[29]; 787 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 788 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 789 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 790 __IM uint32_t RESERVED2[93]; 791 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 792 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 793 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 794 __IM uint32_t RESERVED3[61]; 795 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 796 __IM uint32_t RESERVED4[15]; 797 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 798 __IM uint32_t RESERVED5[15]; 799 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 800 __IM uint32_t RESERVED6[14]; 801 __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 802 __IM uint32_t RESERVED7[14]; 803 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 804 __IM uint32_t RESERVED8[12]; 805 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 806 __IM uint32_t RESERVED9[44]; 807 __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 808 __IM uint32_t RESERVED10[32]; 809 __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 810 __IM uint32_t RESERVED11[32]; 811 __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 812 } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 813 814 815 816 /* =========================================================================================================================== */ 817 /* ================ REGULATORS_NS ================ */ 818 /* =========================================================================================================================== */ 819 820 821 /** 822 * @brief Voltage regulators control 0 (REGULATORS_NS) 823 */ 824 825 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 826 __IM uint32_t RESERVED[320]; 827 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 828 __IM uint32_t RESERVED1[3]; 829 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 830 __IM uint32_t RESERVED2[25]; 831 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator */ 832 } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 833 834 835 836 /* =========================================================================================================================== */ 837 /* ================ CLOCK_NS ================ */ 838 /* =========================================================================================================================== */ 839 840 841 /** 842 * @brief Clock management 0 (CLOCK_NS) 843 */ 844 845 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 846 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 847 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 848 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 849 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 850 __IM uint32_t RESERVED[28]; 851 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 852 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 853 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 854 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 855 __IM uint32_t RESERVED1[28]; 856 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 857 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 858 __IM uint32_t RESERVED2[30]; 859 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 860 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 861 __IM uint32_t RESERVED3[94]; 862 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 863 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 864 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 865 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 866 __IM uint32_t RESERVED4[62]; 867 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 868 triggered */ 869 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 870 by triggering HFCLKSTART task and if it 871 has been started (STATE) */ 872 __IM uint32_t RESERVED5; 873 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 874 triggered */ 875 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 876 requested (SRC) when triggering LFCLKSTART 877 task and if the source has been started 878 (STATE) */ 879 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 880 task has been triggered */ 881 __IM uint32_t RESERVED6[62]; 882 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 883 starts a clock source selected with this 884 register. */ 885 } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 886 887 888 889 /* =========================================================================================================================== */ 890 /* ================ POWER_NS ================ */ 891 /* =========================================================================================================================== */ 892 893 894 /** 895 * @brief Power control 0 (POWER_NS) 896 */ 897 898 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 899 __IM uint32_t RESERVED[30]; 900 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 901 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 902 __IM uint32_t RESERVED1[30]; 903 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 904 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 905 __IM uint32_t RESERVED2[2]; 906 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 907 __IM uint32_t RESERVED3[2]; 908 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 909 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 910 __IM uint32_t RESERVED4[27]; 911 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 912 __IM uint32_t RESERVED5[2]; 913 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 914 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 915 __IM uint32_t RESERVED6[89]; 916 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 917 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 918 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 919 __IM uint32_t RESERVED7[61]; 920 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 921 __IM uint32_t RESERVED8[15]; 922 __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 923 __IM uint32_t RESERVED9[54]; 924 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 925 register */ 926 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 927 928 929 930 /* =========================================================================================================================== */ 931 /* ================ CTRL_AP_PERI_S ================ */ 932 /* =========================================================================================================================== */ 933 934 935 /** 936 * @brief Control access port (CTRL_AP_PERI_S) 937 */ 938 939 typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 940 __IM uint32_t RESERVED[256]; 941 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 942 __IM uint32_t RESERVED1[30]; 943 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 944 } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 945 946 947 948 /* =========================================================================================================================== */ 949 /* ================ SPIM0_NS ================ */ 950 /* =========================================================================================================================== */ 951 952 953 /** 954 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 955 */ 956 957 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 958 __IM uint32_t RESERVED[4]; 959 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 960 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 961 __IM uint32_t RESERVED1; 962 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 963 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 964 __IM uint32_t RESERVED2[27]; 965 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 966 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 967 __IM uint32_t RESERVED3; 968 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 969 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 970 __IM uint32_t RESERVED4[24]; 971 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 972 __IM uint32_t RESERVED5[2]; 973 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 974 __IM uint32_t RESERVED6; 975 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 976 __IM uint32_t RESERVED7; 977 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 978 __IM uint32_t RESERVED8[10]; 979 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 980 __IM uint32_t RESERVED9[13]; 981 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 982 __IM uint32_t RESERVED10[2]; 983 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 984 __IM uint32_t RESERVED11; 985 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 986 __IM uint32_t RESERVED12; 987 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 988 __IM uint32_t RESERVED13[10]; 989 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 990 __IM uint32_t RESERVED14[12]; 991 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 992 __IM uint32_t RESERVED15[64]; 993 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 994 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 995 __IM uint32_t RESERVED16[125]; 996 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 997 __IM uint32_t RESERVED17; 998 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 999 __IM uint32_t RESERVED18[4]; 1000 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1001 source selected. */ 1002 __IM uint32_t RESERVED19[3]; 1003 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1004 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1005 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1006 __IM uint32_t RESERVED20[26]; 1007 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1008 case and over-read of the TXD buffer. */ 1009 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1010 1011 1012 1013 /* =========================================================================================================================== */ 1014 /* ================ SPIS0_NS ================ */ 1015 /* =========================================================================================================================== */ 1016 1017 1018 /** 1019 * @brief SPI Slave 0 (SPIS0_NS) 1020 */ 1021 1022 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1023 __IM uint32_t RESERVED[9]; 1024 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1025 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1026 to acquire it */ 1027 __IM uint32_t RESERVED1[30]; 1028 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1029 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1030 __IM uint32_t RESERVED2[22]; 1031 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1032 __IM uint32_t RESERVED3[2]; 1033 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1034 __IM uint32_t RESERVED4[5]; 1035 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1036 __IM uint32_t RESERVED5[22]; 1037 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1038 __IM uint32_t RESERVED6[2]; 1039 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1040 __IM uint32_t RESERVED7[5]; 1041 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1042 __IM uint32_t RESERVED8[21]; 1043 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1044 __IM uint32_t RESERVED9[64]; 1045 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1046 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1047 __IM uint32_t RESERVED10[61]; 1048 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1049 __IM uint32_t RESERVED11[15]; 1050 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1051 __IM uint32_t RESERVED12[47]; 1052 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1053 __IM uint32_t RESERVED13; 1054 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1055 __IM uint32_t RESERVED14[7]; 1056 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1057 __IM uint32_t RESERVED15; 1058 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1059 __IM uint32_t RESERVED16; 1060 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1061 __IM uint32_t RESERVED17; 1062 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1063 of an ignored transaction. */ 1064 __IM uint32_t RESERVED18[24]; 1065 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1066 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1067 1068 1069 1070 /* =========================================================================================================================== */ 1071 /* ================ TWIM0_NS ================ */ 1072 /* =========================================================================================================================== */ 1073 1074 1075 /** 1076 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1077 */ 1078 1079 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1080 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1081 __IM uint32_t RESERVED; 1082 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1083 __IM uint32_t RESERVED1[2]; 1084 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1085 TWI master is not suspended. */ 1086 __IM uint32_t RESERVED2; 1087 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1088 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1089 __IM uint32_t RESERVED3[23]; 1090 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1091 __IM uint32_t RESERVED4; 1092 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1093 __IM uint32_t RESERVED5[2]; 1094 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1095 __IM uint32_t RESERVED6; 1096 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1097 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1098 __IM uint32_t RESERVED7[24]; 1099 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1100 __IM uint32_t RESERVED8[7]; 1101 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1102 __IM uint32_t RESERVED9[8]; 1103 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1104 task has been issued, TWI traffic is now 1105 suspended. */ 1106 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1107 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1108 __IM uint32_t RESERVED10[2]; 1109 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1110 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1111 byte */ 1112 __IM uint32_t RESERVED11[8]; 1113 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1114 __IM uint32_t RESERVED12[7]; 1115 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1116 __IM uint32_t RESERVED13[8]; 1117 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1118 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1119 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1120 __IM uint32_t RESERVED14[2]; 1121 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1122 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1123 __IM uint32_t RESERVED15[7]; 1124 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1125 __IM uint32_t RESERVED16[63]; 1126 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1127 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1128 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1129 __IM uint32_t RESERVED17[110]; 1130 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1131 __IM uint32_t RESERVED18[14]; 1132 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1133 __IM uint32_t RESERVED19; 1134 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1135 __IM uint32_t RESERVED20[5]; 1136 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1137 source selected. */ 1138 __IM uint32_t RESERVED21[3]; 1139 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1140 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1141 __IM uint32_t RESERVED22[13]; 1142 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1143 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1144 1145 1146 1147 /* =========================================================================================================================== */ 1148 /* ================ TWIS0_NS ================ */ 1149 /* =========================================================================================================================== */ 1150 1151 1152 /** 1153 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1154 */ 1155 1156 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1157 __IM uint32_t RESERVED[5]; 1158 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1159 __IM uint32_t RESERVED1; 1160 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1161 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1162 __IM uint32_t RESERVED2[3]; 1163 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1164 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1165 __IM uint32_t RESERVED3[23]; 1166 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1167 __IM uint32_t RESERVED4; 1168 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1169 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1170 __IM uint32_t RESERVED5[3]; 1171 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1172 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1173 __IM uint32_t RESERVED6[19]; 1174 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1175 __IM uint32_t RESERVED7[7]; 1176 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1177 __IM uint32_t RESERVED8[9]; 1178 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1179 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1180 __IM uint32_t RESERVED9[4]; 1181 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1182 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1183 __IM uint32_t RESERVED10[6]; 1184 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1185 __IM uint32_t RESERVED11[7]; 1186 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1187 __IM uint32_t RESERVED12[9]; 1188 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1189 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1190 __IM uint32_t RESERVED13[4]; 1191 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1192 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1193 __IM uint32_t RESERVED14[5]; 1194 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1195 __IM uint32_t RESERVED15[63]; 1196 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1197 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1198 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1199 __IM uint32_t RESERVED16[113]; 1200 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1201 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1202 a match */ 1203 __IM uint32_t RESERVED17[10]; 1204 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1205 __IM uint32_t RESERVED18; 1206 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1207 __IM uint32_t RESERVED19[9]; 1208 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1209 __IM uint32_t RESERVED20; 1210 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1211 __IM uint32_t RESERVED21[14]; 1212 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1213 __IM uint32_t RESERVED22; 1214 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1215 mechanism */ 1216 __IM uint32_t RESERVED23[10]; 1217 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1218 of an over-read of the transmit buffer. */ 1219 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1220 1221 1222 1223 /* =========================================================================================================================== */ 1224 /* ================ UARTE0_NS ================ */ 1225 /* =========================================================================================================================== */ 1226 1227 1228 /** 1229 * @brief UART with EasyDMA 0 (UARTE0_NS) 1230 */ 1231 1232 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1233 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1234 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1235 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1236 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1237 __IM uint32_t RESERVED[7]; 1238 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1239 __IM uint32_t RESERVED1[20]; 1240 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1241 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1242 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1243 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1244 __IM uint32_t RESERVED2[7]; 1245 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1246 __IM uint32_t RESERVED3[20]; 1247 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1248 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1249 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1250 transferred to Data RAM) */ 1251 __IM uint32_t RESERVED4; 1252 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1253 __IM uint32_t RESERVED5[2]; 1254 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1255 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1256 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1257 __IM uint32_t RESERVED6[7]; 1258 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1259 __IM uint32_t RESERVED7; 1260 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1261 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1262 __IM uint32_t RESERVED8; 1263 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1264 __IM uint32_t RESERVED9[9]; 1265 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1266 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1267 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1268 __IM uint32_t RESERVED10; 1269 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1270 __IM uint32_t RESERVED11[2]; 1271 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1272 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1273 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1274 __IM uint32_t RESERVED12[7]; 1275 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1276 __IM uint32_t RESERVED13; 1277 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1278 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1279 __IM uint32_t RESERVED14; 1280 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1281 __IM uint32_t RESERVED15[9]; 1282 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1283 __IM uint32_t RESERVED16[63]; 1284 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1285 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1286 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1287 __IM uint32_t RESERVED17[93]; 1288 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1289 one to clear. */ 1290 __IM uint32_t RESERVED18[31]; 1291 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1292 __IM uint32_t RESERVED19; 1293 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1294 __IM uint32_t RESERVED20[3]; 1295 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1296 selected. */ 1297 __IM uint32_t RESERVED21[3]; 1298 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1299 __IM uint32_t RESERVED22; 1300 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1301 __IM uint32_t RESERVED23[7]; 1302 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1303 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1304 1305 1306 1307 /* =========================================================================================================================== */ 1308 /* ================ GPIOTE0_S ================ */ 1309 /* =========================================================================================================================== */ 1310 1311 1312 /** 1313 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1314 */ 1315 1316 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1317 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1318 specified in CONFIG[n].PSEL. Action on pin 1319 is configured in CONFIG[n].POLARITY. */ 1320 __IM uint32_t RESERVED[4]; 1321 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1322 specified in CONFIG[n].PSEL. Action on pin 1323 is to set it high. */ 1324 __IM uint32_t RESERVED1[4]; 1325 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1326 specified in CONFIG[n].PSEL. Action on pin 1327 is to set it low. */ 1328 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1329 for task OUT[n] */ 1330 __IM uint32_t RESERVED2[4]; 1331 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1332 for task SET[n] */ 1333 __IM uint32_t RESERVED3[4]; 1334 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1335 for task CLR[n] */ 1336 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1337 pin specified in CONFIG[n].PSEL */ 1338 __IM uint32_t RESERVED4[23]; 1339 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1340 with SENSE mechanism enabled */ 1341 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1342 for event IN[n] */ 1343 __IM uint32_t RESERVED5[23]; 1344 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1345 __IM uint32_t RESERVED6[65]; 1346 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1347 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1348 __IM uint32_t RESERVED7[129]; 1349 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1350 SET[n] and CLR[n] tasks and IN[n] event */ 1351 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1352 1353 1354 1355 /* =========================================================================================================================== */ 1356 /* ================ SAADC_NS ================ */ 1357 /* =========================================================================================================================== */ 1358 1359 1360 /** 1361 * @brief Analog to Digital Converter 0 (SAADC_NS) 1362 */ 1363 1364 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 1365 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1366 RAM */ 1367 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1368 are sampled */ 1369 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1370 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1371 __IM uint32_t RESERVED[28]; 1372 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1373 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 1374 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1375 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 1376 __IM uint32_t RESERVED1[28]; 1377 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1378 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1379 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1380 on the mode, multiple conversions might 1381 be needed for a result to be transferred 1382 to RAM. */ 1383 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1384 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1385 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1386 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1387 __IM uint32_t RESERVED2[10]; 1388 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1389 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1390 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 1391 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 1392 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 1393 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 1394 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 1395 __IM uint32_t RESERVED3[74]; 1396 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1397 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1398 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1399 __IM uint32_t RESERVED4[61]; 1400 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1401 __IM uint32_t RESERVED5[63]; 1402 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1403 __IM uint32_t RESERVED6[3]; 1404 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1405 __IM uint32_t RESERVED7[24]; 1406 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1407 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1408 not be combined with SCAN. The RESOLUTION 1409 is applied before averaging, thus for high 1410 OVERSAMPLE a higher RESOLUTION should be 1411 used. */ 1412 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1413 __IM uint32_t RESERVED8[12]; 1414 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1415 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1416 1417 1418 1419 /* =========================================================================================================================== */ 1420 /* ================ TIMER0_NS ================ */ 1421 /* =========================================================================================================================== */ 1422 1423 1424 /** 1425 * @brief Timer/Counter 0 (TIMER0_NS) 1426 */ 1427 1428 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 1429 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1430 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1431 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1432 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1433 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1434 __IM uint32_t RESERVED[11]; 1435 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1436 CC[n] register */ 1437 __IM uint32_t RESERVED1[10]; 1438 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1439 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1440 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1441 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1442 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1443 for task SHUTDOWN */ 1444 __IM uint32_t RESERVED2[11]; 1445 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1446 for task CAPTURE[n] */ 1447 __IM uint32_t RESERVED3[26]; 1448 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1449 match */ 1450 __IM uint32_t RESERVED4[26]; 1451 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1452 for event COMPARE[n] */ 1453 __IM uint32_t RESERVED5[10]; 1454 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1455 __IM uint32_t RESERVED6[64]; 1456 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1457 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1458 __IM uint32_t RESERVED7[126]; 1459 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1460 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1461 __IM uint32_t RESERVED8; 1462 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1463 __IM uint32_t RESERVED9[11]; 1464 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1465 n */ 1466 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1467 1468 1469 1470 /* =========================================================================================================================== */ 1471 /* ================ RTC0_NS ================ */ 1472 /* =========================================================================================================================== */ 1473 1474 1475 /** 1476 * @brief Real-time counter 0 (RTC0_NS) 1477 */ 1478 1479 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 1480 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1481 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1482 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1483 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1484 __IM uint32_t RESERVED[28]; 1485 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1486 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1487 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1488 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1489 __IM uint32_t RESERVED1[28]; 1490 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1491 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1492 __IM uint32_t RESERVED2[14]; 1493 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1494 match */ 1495 __IM uint32_t RESERVED3[12]; 1496 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1497 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1498 __IM uint32_t RESERVED4[14]; 1499 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1500 for event COMPARE[n] */ 1501 __IM uint32_t RESERVED5[77]; 1502 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1503 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1504 __IM uint32_t RESERVED6[13]; 1505 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1506 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1507 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1508 __IM uint32_t RESERVED7[110]; 1509 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1510 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 1511 Must be written when RTC is stopped. */ 1512 __IM uint32_t RESERVED8[13]; 1513 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1514 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1515 1516 1517 1518 /* =========================================================================================================================== */ 1519 /* ================ DPPIC_NS ================ */ 1520 /* =========================================================================================================================== */ 1521 1522 1523 /** 1524 * @brief Distributed Programmable Peripheral Interconnect Controller 0 (DPPIC_NS) 1525 */ 1526 1527 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 1528 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1529 __IM uint32_t RESERVED[20]; 1530 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1531 __IM uint32_t RESERVED1[276]; 1532 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1533 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1534 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1535 __IM uint32_t RESERVED2[189]; 1536 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1537 Writes to this register is ignored if either 1538 SUBSCRIBE_CHG[n].EN/DIS are enabled. */ 1539 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1540 1541 1542 1543 /* =========================================================================================================================== */ 1544 /* ================ WDT_NS ================ */ 1545 /* =========================================================================================================================== */ 1546 1547 1548 /** 1549 * @brief Watchdog Timer 0 (WDT_NS) 1550 */ 1551 1552 typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 1553 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1554 __IM uint32_t RESERVED[31]; 1555 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1556 __IM uint32_t RESERVED1[31]; 1557 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1558 __IM uint32_t RESERVED2[31]; 1559 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1560 __IM uint32_t RESERVED3[96]; 1561 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1562 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1563 __IM uint32_t RESERVED4[61]; 1564 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1565 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1566 __IM uint32_t RESERVED5[63]; 1567 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1568 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1569 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1570 __IM uint32_t RESERVED6[60]; 1571 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1572 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1573 1574 1575 1576 /* =========================================================================================================================== */ 1577 /* ================ EGU0_NS ================ */ 1578 /* =========================================================================================================================== */ 1579 1580 1581 /** 1582 * @brief Event Generator Unit 0 (EGU0_NS) 1583 */ 1584 1585 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1586 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1587 the corresponding TRIGGERED[n] event */ 1588 __IM uint32_t RESERVED[16]; 1589 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1590 for task TRIGGER[n] */ 1591 __IM uint32_t RESERVED1[16]; 1592 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1593 by triggering the corresponding TRIGGER[n] 1594 task */ 1595 __IM uint32_t RESERVED2[16]; 1596 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1597 for event TRIGGERED[n] */ 1598 __IM uint32_t RESERVED3[80]; 1599 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1600 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1601 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1602 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1603 1604 1605 1606 /* =========================================================================================================================== */ 1607 /* ================ PWM0_NS ================ */ 1608 /* =========================================================================================================================== */ 1609 1610 1611 /** 1612 * @brief Pulse width modulation unit 0 (PWM0_NS) 1613 */ 1614 1615 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 1616 __IM uint32_t RESERVED; 1617 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1618 the end of current PWM period, and stops 1619 sequence playback */ 1620 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1621 on all enabled channels from sequence n, 1622 and starts playing that sequence at the 1623 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1624 Causes PWM generation to start if not running. */ 1625 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1626 all enabled channels if DECODER.MODE=NextStep. 1627 Does not cause PWM generation to start if 1628 not running. */ 1629 __IM uint32_t RESERVED1[28]; 1630 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1631 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 1632 for task SEQSTART[n] */ 1633 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 1634 __IM uint32_t RESERVED2[28]; 1635 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1636 are no longer generated */ 1637 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1638 on sequence n */ 1639 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1640 sequence n, when last value from RAM has 1641 been applied to wave counter */ 1642 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1643 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1644 of times defined in LOOP.CNT */ 1645 __IM uint32_t RESERVED3[25]; 1646 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1647 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 1648 for event SEQSTARTED[n] */ 1649 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 1650 for event SEQEND[n] */ 1651 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 1652 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 1653 __IM uint32_t RESERVED4[24]; 1654 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1655 __IM uint32_t RESERVED5[63]; 1656 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1657 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1658 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1659 __IM uint32_t RESERVED6[125]; 1660 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1661 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1662 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1663 counts */ 1664 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1665 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1666 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1667 __IM uint32_t RESERVED7[2]; 1668 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1669 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1670 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1671 1672 1673 1674 /* =========================================================================================================================== */ 1675 /* ================ PDM_NS ================ */ 1676 /* =========================================================================================================================== */ 1677 1678 1679 /** 1680 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 1681 */ 1682 1683 typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 1684 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1685 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1686 __IM uint32_t RESERVED[30]; 1687 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1688 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1689 __IM uint32_t RESERVED1[30]; 1690 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1691 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1692 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1693 by SAMPLE.MAXCNT (or the last sample after 1694 a STOP task has been received) to Data RAM */ 1695 __IM uint32_t RESERVED2[29]; 1696 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1697 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1698 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 1699 __IM uint32_t RESERVED3[93]; 1700 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1701 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1702 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1703 __IM uint32_t RESERVED4[125]; 1704 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1705 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1706 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1707 signals */ 1708 __IM uint32_t RESERVED5[3]; 1709 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1710 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1711 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 1712 sample rate. Change PDMCLKCTRL accordingly. */ 1713 __IM uint32_t RESERVED6[7]; 1714 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1715 __IM uint32_t RESERVED7[6]; 1716 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1717 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1718 1719 1720 1721 /* =========================================================================================================================== */ 1722 /* ================ I2S_NS ================ */ 1723 /* =========================================================================================================================== */ 1724 1725 1726 /** 1727 * @brief Inter-IC Sound 0 (I2S_NS) 1728 */ 1729 1730 typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 1731 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 1732 generator when this is enabled. */ 1733 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 1734 Triggering this task will cause the STOPPED 1735 event to be generated. */ 1736 __IM uint32_t RESERVED[30]; 1737 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1738 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1739 __IM uint32_t RESERVED1[31]; 1740 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 1741 double-buffers. When the I2S module is started 1742 and RX is enabled, this event will be generated 1743 for every RXTXD.MAXCNT words that are received 1744 on the SDIN pin. */ 1745 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 1746 __IM uint32_t RESERVED2[2]; 1747 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 1748 double-buffers. When the I2S module is started 1749 and TX is enabled, this event will be generated 1750 for every RXTXD.MAXCNT words that are sent 1751 on the SDOUT pin. */ 1752 __IM uint32_t RESERVED3[27]; 1753 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 1754 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 1755 __IM uint32_t RESERVED4[2]; 1756 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 1757 __IM uint32_t RESERVED5[90]; 1758 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1759 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1760 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1761 __IM uint32_t RESERVED6[125]; 1762 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 1763 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 1764 __IM uint32_t RESERVED7[3]; 1765 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 1766 __IM uint32_t RESERVED8; 1767 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 1768 __IM uint32_t RESERVED9[3]; 1769 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 1770 __IM uint32_t RESERVED10[3]; 1771 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1772 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 1773 1774 1775 1776 /* =========================================================================================================================== */ 1777 /* ================ IPC_NS ================ */ 1778 /* =========================================================================================================================== */ 1779 1780 1781 /** 1782 * @brief Inter Processor Communication 0 (IPC_NS) 1783 */ 1784 1785 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 1786 __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on channel 1787 enabled in SEND_CNF[n]. */ 1788 __IM uint32_t RESERVED[24]; 1789 __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1790 for task SEND[n] */ 1791 __IM uint32_t RESERVED1[24]; 1792 __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 1793 or more of the enabled channels in RECEIVE_CNF[n]. */ 1794 __IM uint32_t RESERVED2[24]; 1795 __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1796 for event RECEIVE[n] */ 1797 __IM uint32_t RESERVED3[88]; 1798 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1799 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1800 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1801 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1802 __IM uint32_t RESERVED4[128]; 1803 __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 1804 for TASKS_SEND[n]. */ 1805 __IM uint32_t RESERVED5[24]; 1806 __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1807 for EVENTS_RECEIVE[n]. */ 1808 __IM uint32_t RESERVED6[24]; 1809 __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory. */ 1810 } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 1811 1812 1813 1814 /* =========================================================================================================================== */ 1815 /* ================ FPU_NS ================ */ 1816 /* =========================================================================================================================== */ 1817 1818 1819 /** 1820 * @brief FPU 0 (FPU_NS) 1821 */ 1822 1823 typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 1824 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1825 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 1826 1827 1828 1829 /* =========================================================================================================================== */ 1830 /* ================ KMU_NS ================ */ 1831 /* =========================================================================================================================== */ 1832 1833 1834 /** 1835 * @brief Key management unit 0 (KMU_NS) 1836 */ 1837 1838 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 1839 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 1840 __IM uint32_t RESERVED[63]; 1841 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key successfully pushed over secure APB */ 1842 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key has been revoked and cannot be tasked for 1843 selection */ 1844 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 1845 defined, or error during push operation */ 1846 __IM uint32_t RESERVED1[125]; 1847 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1848 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1849 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1850 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1851 __IM uint32_t RESERVED2[63]; 1852 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 1853 __IM uint32_t RESERVED3[60]; 1854 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot ID to be read over AHB or pushed 1855 over secure APB when TASKS_PUSH_KEYSLOT 1856 is started */ 1857 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 1858 1859 1860 1861 /* =========================================================================================================================== */ 1862 /* ================ NVMC_NS ================ */ 1863 /* =========================================================================================================================== */ 1864 1865 1866 /** 1867 * @brief Non-volatile memory controller 0 (NVMC_NS) 1868 */ 1869 1870 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 1871 __IM uint32_t RESERVED[256]; 1872 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1873 __IM uint32_t RESERVED1; 1874 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1875 __IM uint32_t RESERVED2[62]; 1876 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1877 __IM uint32_t RESERVED3; 1878 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1879 __IM uint32_t RESERVED4[3]; 1880 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1881 __IM uint32_t RESERVED5[8]; 1882 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1883 __IM uint32_t RESERVED6; 1884 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1885 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 1886 __IM uint32_t RESERVED7[13]; 1887 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 1888 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 1889 __IM uint32_t RESERVED8[93]; 1890 __IOM uint32_t FORCEONNVM; /*!< (@ 0x00000700) Force on all NVM supplies. Also see the internal 1891 section in the NVMC chapter. */ 1892 __IM uint32_t RESERVED9[9]; 1893 __IOM uint32_t FORCEOFFNVM; /*!< (@ 0x00000728) Force off NVM supply. Also see the internal section 1894 in the NVMC chapter. */ 1895 } NRF_NVMC_Type; /*!< Size = 1836 (0x72c) */ 1896 1897 1898 1899 /* =========================================================================================================================== */ 1900 /* ================ VMC_NS ================ */ 1901 /* =========================================================================================================================== */ 1902 1903 1904 /** 1905 * @brief Volatile Memory controller 0 (VMC_NS) 1906 */ 1907 1908 typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 1909 __IM uint32_t RESERVED[384]; 1910 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 1911 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 1912 1913 1914 1915 /* =========================================================================================================================== */ 1916 /* ================ CRYPTOCELL_S ================ */ 1917 /* =========================================================================================================================== */ 1918 1919 1920 /** 1921 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) 1922 */ 1923 1924 typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 1925 __IM uint32_t RESERVED[320]; 1926 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 1927 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 1928 1929 1930 1931 /* =========================================================================================================================== */ 1932 /* ================ P0_NS ================ */ 1933 /* =========================================================================================================================== */ 1934 1935 1936 /** 1937 * @brief GPIO Port 0 (P0_NS) 1938 */ 1939 1940 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 1941 __IM uint32_t RESERVED; 1942 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 1943 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 1944 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 1945 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 1946 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 1947 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 1948 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 1949 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 1950 have met the criteria set in the PIN_CNF[n].SENSE 1951 registers */ 1952 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behaviour 1953 and LDETECT mode (For non-secure pin only) */ 1954 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behaviour 1955 and LDETECT mode (For secure pin only) */ 1956 __IM uint32_t RESERVED1[117]; 1957 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 1958 pins */ 1959 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 1960 1961 1962 /** @} */ /* End of group Device_Peripheral_peripherals */ 1963 1964 1965 /* =========================================================================================================================== */ 1966 /* ================ Device Specific Peripheral Address Map ================ */ 1967 /* =========================================================================================================================== */ 1968 1969 1970 /** @addtogroup Device_Peripheral_peripheralAddr 1971 * @{ 1972 */ 1973 1974 #define NRF_FICR_S_BASE 0x00FF0000UL 1975 #define NRF_UICR_S_BASE 0x00FF8000UL 1976 #define NRF_TAD_S_BASE 0xE0080000UL 1977 #define NRF_SPU_S_BASE 0x50003000UL 1978 #define NRF_REGULATORS_NS_BASE 0x40004000UL 1979 #define NRF_REGULATORS_S_BASE 0x50004000UL 1980 #define NRF_CLOCK_NS_BASE 0x40005000UL 1981 #define NRF_POWER_NS_BASE 0x40005000UL 1982 #define NRF_CLOCK_S_BASE 0x50005000UL 1983 #define NRF_POWER_S_BASE 0x50005000UL 1984 #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 1985 #define NRF_SPIM0_NS_BASE 0x40008000UL 1986 #define NRF_SPIS0_NS_BASE 0x40008000UL 1987 #define NRF_TWIM0_NS_BASE 0x40008000UL 1988 #define NRF_TWIS0_NS_BASE 0x40008000UL 1989 #define NRF_UARTE0_NS_BASE 0x40008000UL 1990 #define NRF_SPIM0_S_BASE 0x50008000UL 1991 #define NRF_SPIS0_S_BASE 0x50008000UL 1992 #define NRF_TWIM0_S_BASE 0x50008000UL 1993 #define NRF_TWIS0_S_BASE 0x50008000UL 1994 #define NRF_UARTE0_S_BASE 0x50008000UL 1995 #define NRF_SPIM1_NS_BASE 0x40009000UL 1996 #define NRF_SPIS1_NS_BASE 0x40009000UL 1997 #define NRF_TWIM1_NS_BASE 0x40009000UL 1998 #define NRF_TWIS1_NS_BASE 0x40009000UL 1999 #define NRF_UARTE1_NS_BASE 0x40009000UL 2000 #define NRF_SPIM1_S_BASE 0x50009000UL 2001 #define NRF_SPIS1_S_BASE 0x50009000UL 2002 #define NRF_TWIM1_S_BASE 0x50009000UL 2003 #define NRF_TWIS1_S_BASE 0x50009000UL 2004 #define NRF_UARTE1_S_BASE 0x50009000UL 2005 #define NRF_SPIM2_NS_BASE 0x4000A000UL 2006 #define NRF_SPIS2_NS_BASE 0x4000A000UL 2007 #define NRF_TWIM2_NS_BASE 0x4000A000UL 2008 #define NRF_TWIS2_NS_BASE 0x4000A000UL 2009 #define NRF_UARTE2_NS_BASE 0x4000A000UL 2010 #define NRF_SPIM2_S_BASE 0x5000A000UL 2011 #define NRF_SPIS2_S_BASE 0x5000A000UL 2012 #define NRF_TWIM2_S_BASE 0x5000A000UL 2013 #define NRF_TWIS2_S_BASE 0x5000A000UL 2014 #define NRF_UARTE2_S_BASE 0x5000A000UL 2015 #define NRF_SPIM3_NS_BASE 0x4000B000UL 2016 #define NRF_SPIS3_NS_BASE 0x4000B000UL 2017 #define NRF_TWIM3_NS_BASE 0x4000B000UL 2018 #define NRF_TWIS3_NS_BASE 0x4000B000UL 2019 #define NRF_UARTE3_NS_BASE 0x4000B000UL 2020 #define NRF_SPIM3_S_BASE 0x5000B000UL 2021 #define NRF_SPIS3_S_BASE 0x5000B000UL 2022 #define NRF_TWIM3_S_BASE 0x5000B000UL 2023 #define NRF_TWIS3_S_BASE 0x5000B000UL 2024 #define NRF_UARTE3_S_BASE 0x5000B000UL 2025 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 2026 #define NRF_SAADC_NS_BASE 0x4000E000UL 2027 #define NRF_SAADC_S_BASE 0x5000E000UL 2028 #define NRF_TIMER0_NS_BASE 0x4000F000UL 2029 #define NRF_TIMER0_S_BASE 0x5000F000UL 2030 #define NRF_TIMER1_NS_BASE 0x40010000UL 2031 #define NRF_TIMER1_S_BASE 0x50010000UL 2032 #define NRF_TIMER2_NS_BASE 0x40011000UL 2033 #define NRF_TIMER2_S_BASE 0x50011000UL 2034 #define NRF_RTC0_NS_BASE 0x40014000UL 2035 #define NRF_RTC0_S_BASE 0x50014000UL 2036 #define NRF_RTC1_NS_BASE 0x40015000UL 2037 #define NRF_RTC1_S_BASE 0x50015000UL 2038 #define NRF_DPPIC_NS_BASE 0x40017000UL 2039 #define NRF_DPPIC_S_BASE 0x50017000UL 2040 #define NRF_WDT_NS_BASE 0x40018000UL 2041 #define NRF_WDT_S_BASE 0x50018000UL 2042 #define NRF_EGU0_NS_BASE 0x4001B000UL 2043 #define NRF_EGU0_S_BASE 0x5001B000UL 2044 #define NRF_EGU1_NS_BASE 0x4001C000UL 2045 #define NRF_EGU1_S_BASE 0x5001C000UL 2046 #define NRF_EGU2_NS_BASE 0x4001D000UL 2047 #define NRF_EGU2_S_BASE 0x5001D000UL 2048 #define NRF_EGU3_NS_BASE 0x4001E000UL 2049 #define NRF_EGU3_S_BASE 0x5001E000UL 2050 #define NRF_EGU4_NS_BASE 0x4001F000UL 2051 #define NRF_EGU4_S_BASE 0x5001F000UL 2052 #define NRF_EGU5_NS_BASE 0x40020000UL 2053 #define NRF_EGU5_S_BASE 0x50020000UL 2054 #define NRF_PWM0_NS_BASE 0x40021000UL 2055 #define NRF_PWM0_S_BASE 0x50021000UL 2056 #define NRF_PWM1_NS_BASE 0x40022000UL 2057 #define NRF_PWM1_S_BASE 0x50022000UL 2058 #define NRF_PWM2_NS_BASE 0x40023000UL 2059 #define NRF_PWM2_S_BASE 0x50023000UL 2060 #define NRF_PWM3_NS_BASE 0x40024000UL 2061 #define NRF_PWM3_S_BASE 0x50024000UL 2062 #define NRF_PDM_NS_BASE 0x40026000UL 2063 #define NRF_PDM_S_BASE 0x50026000UL 2064 #define NRF_I2S_NS_BASE 0x40028000UL 2065 #define NRF_I2S_S_BASE 0x50028000UL 2066 #define NRF_IPC_NS_BASE 0x4002A000UL 2067 #define NRF_IPC_S_BASE 0x5002A000UL 2068 #define NRF_FPU_NS_BASE 0x4002C000UL 2069 #define NRF_FPU_S_BASE 0x5002C000UL 2070 #define NRF_GPIOTE1_NS_BASE 0x40031000UL 2071 #define NRF_KMU_NS_BASE 0x40039000UL 2072 #define NRF_NVMC_NS_BASE 0x40039000UL 2073 #define NRF_KMU_S_BASE 0x50039000UL 2074 #define NRF_NVMC_S_BASE 0x50039000UL 2075 #define NRF_VMC_NS_BASE 0x4003A000UL 2076 #define NRF_VMC_S_BASE 0x5003A000UL 2077 #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 2078 #define NRF_P0_NS_BASE 0x40842500UL 2079 #define NRF_P0_S_BASE 0x50842500UL 2080 2081 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2082 2083 2084 /* =========================================================================================================================== */ 2085 /* ================ Peripheral declaration ================ */ 2086 /* =========================================================================================================================== */ 2087 2088 2089 /** @addtogroup Device_Peripheral_declaration 2090 * @{ 2091 */ 2092 2093 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 2094 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 2095 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 2096 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 2097 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 2098 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 2099 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 2100 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 2101 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 2102 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 2103 #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 2104 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 2105 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 2106 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 2107 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 2108 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 2109 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 2110 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 2111 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 2112 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 2113 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 2114 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 2115 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 2116 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 2117 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 2118 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 2119 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 2120 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 2121 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 2122 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 2123 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 2124 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 2125 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 2126 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 2127 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 2128 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 2129 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 2130 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 2131 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 2132 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 2133 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 2134 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 2135 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 2136 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 2137 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 2138 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 2139 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 2140 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 2141 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 2142 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 2143 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 2144 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 2145 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 2146 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 2147 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 2148 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 2149 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2150 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 2151 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2152 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 2153 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 2154 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 2155 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 2156 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 2157 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 2158 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 2159 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 2160 #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 2161 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 2162 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 2163 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 2164 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 2165 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 2166 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 2167 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 2168 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 2169 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 2170 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 2171 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 2172 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 2173 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 2174 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 2175 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 2176 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 2177 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 2178 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 2179 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 2180 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 2181 #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 2182 #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 2183 #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 2184 #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 2185 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 2186 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 2187 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 2188 #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) 2189 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 2190 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 2191 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2192 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 2193 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 2194 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2195 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 2196 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 2197 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2198 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 2199 2200 /** @} */ /* End of group Device_Peripheral_declaration */ 2201 2202 2203 #ifdef __cplusplus 2204 } 2205 #endif 2206 2207 #endif /* NRF9160_H */ 2208 2209 2210 /** @} */ /* End of group nrf9160 */ 2211 2212 /** @} */ /* End of group Nordic Semiconductor */ 2213