xref: /nrf52832-nimble/nordic/nrfx/mdk/nrf52_bitfields.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b) 
1 /*
2 
3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
4 
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7 
8 1. Redistributions of source code must retain the above copyright notice, this
9    list of conditions and the following disclaimer.
10 
11 2. Redistributions in binary form must reproduce the above copyright
12    notice, this list of conditions and the following disclaimer in the
13    documentation and/or other materials provided with the distribution.
14 
15 3. Neither the name of Nordic Semiconductor ASA nor the names of its
16    contributors may be used to endorse or promote products derived from this
17    software without specific prior written permission.
18 
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE.
30 
31 */
32 
33 #ifndef __NRF52_BITS_H
34 #define __NRF52_BITS_H
35 
36 /*lint ++flb "Enter library region" */
37 
38 /* Peripheral: AAR */
39 /* Description: Accelerated Address Resolver */
40 
41 /* Register: AAR_INTENSET */
42 /* Description: Enable interrupt */
43 
44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
45 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
46 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
48 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
49 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
50 
51 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
52 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
53 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
55 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
56 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
57 
58 /* Bit 0 : Write '1' to Enable interrupt for END event */
59 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
60 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
62 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
63 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
64 
65 /* Register: AAR_INTENCLR */
66 /* Description: Disable interrupt */
67 
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
69 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
70 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
72 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
73 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
74 
75 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
76 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
77 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
79 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
80 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
81 
82 /* Bit 0 : Write '1' to Disable interrupt for END event */
83 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
84 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
86 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
87 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
88 
89 /* Register: AAR_STATUS */
90 /* Description: Resolution status */
91 
92 /* Bits 3..0 : The IRK that was used last time an address was resolved */
93 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
94 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
95 
96 /* Register: AAR_ENABLE */
97 /* Description: Enable AAR */
98 
99 /* Bits 1..0 : Enable or disable AAR */
100 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
101 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
102 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
103 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
104 
105 /* Register: AAR_NIRK */
106 /* Description: Number of IRKs */
107 
108 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
109 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
110 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
111 
112 /* Register: AAR_IRKPTR */
113 /* Description: Pointer to IRK data structure */
114 
115 /* Bits 31..0 : Pointer to the IRK data structure */
116 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
117 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
118 
119 /* Register: AAR_ADDRPTR */
120 /* Description: Pointer to the resolvable address */
121 
122 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
123 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
124 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
125 
126 /* Register: AAR_SCRATCHPTR */
127 /* Description: Pointer to data area used for temporary storage */
128 
129 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
130 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
131 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
132 
133 
134 /* Peripheral: BPROT */
135 /* Description: Block Protect */
136 
137 /* Register: BPROT_CONFIG0 */
138 /* Description: Block protect configuration register 0 */
139 
140 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
141 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
142 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
143 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
144 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
145 
146 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
147 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
148 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
149 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
150 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
151 
152 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
153 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
154 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
155 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
156 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
157 
158 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
159 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
160 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
161 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
162 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
163 
164 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
165 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
166 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
167 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
168 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
169 
170 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
171 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
172 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
173 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
174 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
175 
176 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
177 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
178 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
179 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
180 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
181 
182 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
183 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
184 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
185 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
186 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
187 
188 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
189 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
190 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
191 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
192 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
193 
194 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
195 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
196 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
197 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
198 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
199 
200 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
201 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
202 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
203 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
204 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
205 
206 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
207 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
208 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
209 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
210 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
211 
212 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
213 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
214 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
215 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
216 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
217 
218 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
219 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
220 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
221 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
222 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
223 
224 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
225 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
226 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
227 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
228 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
229 
230 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
231 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
232 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
233 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
234 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
235 
236 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
237 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
238 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
239 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
240 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
241 
242 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
243 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
244 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
245 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
246 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
247 
248 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
249 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
250 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
251 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
252 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
253 
254 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
255 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
256 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
257 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
258 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
259 
260 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
261 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
262 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
263 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
264 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
265 
266 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
267 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
268 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
269 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
270 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
271 
272 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
273 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
274 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
275 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
276 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
277 
278 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
279 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
280 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
281 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
282 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
283 
284 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
285 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
286 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
287 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
288 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
289 
290 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
291 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
292 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
293 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
294 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
295 
296 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
297 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
298 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
299 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
300 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
301 
302 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
303 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
304 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
305 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
306 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
307 
308 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
309 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
310 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
311 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
312 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
313 
314 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
315 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
316 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
317 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
318 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
319 
320 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
321 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
322 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
323 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
324 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
325 
326 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
327 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
328 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
329 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
330 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
331 
332 /* Register: BPROT_CONFIG1 */
333 /* Description: Block protect configuration register 1 */
334 
335 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
336 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
337 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
338 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
339 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
340 
341 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
342 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
343 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
344 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
345 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
346 
347 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
348 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
349 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
350 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
351 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
352 
353 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
354 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
355 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
356 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
357 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
358 
359 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
360 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
361 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
362 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
363 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
364 
365 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
366 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
367 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
368 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
369 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
370 
371 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
372 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
373 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
374 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
375 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
376 
377 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
378 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
379 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
380 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
381 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
382 
383 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
384 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
385 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
386 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
387 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
388 
389 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
390 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
391 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
392 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
393 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
394 
395 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
396 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
397 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
398 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
399 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
400 
401 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
402 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
403 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
404 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
405 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
406 
407 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
408 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
409 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
410 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
411 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
412 
413 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
414 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
415 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
416 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
417 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
418 
419 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
420 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
421 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
422 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
423 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
424 
425 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
426 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
427 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
428 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
429 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
430 
431 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
432 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
433 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
434 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
435 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
436 
437 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
438 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
439 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
440 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
441 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
442 
443 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
444 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
445 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
446 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
447 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
448 
449 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
450 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
451 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
452 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
453 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
454 
455 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
456 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
457 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
458 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
459 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
460 
461 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
462 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
463 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
464 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
465 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
466 
467 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
468 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
469 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
470 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
471 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
472 
473 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
474 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
475 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
476 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
477 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
478 
479 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
480 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
481 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
482 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
483 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
484 
485 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
486 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
487 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
488 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
489 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
490 
491 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
492 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
493 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
494 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
495 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
496 
497 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
498 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
499 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
500 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
501 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
502 
503 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
504 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
505 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
506 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
507 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
508 
509 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
510 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
511 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
512 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
513 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
514 
515 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
516 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
517 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
518 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
519 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
520 
521 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
522 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
523 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
524 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
525 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
526 
527 /* Register: BPROT_DISABLEINDEBUG */
528 /* Description: Disable protection mechanism in debug interface mode */
529 
530 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
531 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
532 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
533 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
534 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
535 
536 /* Register: BPROT_CONFIG2 */
537 /* Description: Block protect configuration register 2 */
538 
539 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
540 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
541 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
542 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
543 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
544 
545 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
546 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
547 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
548 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
549 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
550 
551 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
552 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
553 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
554 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
555 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
556 
557 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
558 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
559 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
560 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
561 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
562 
563 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
564 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
565 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
566 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
567 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
568 
569 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
570 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
571 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
572 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
573 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
574 
575 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
576 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
577 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
578 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
579 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
580 
581 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
582 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
583 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
584 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
585 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
586 
587 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
588 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
589 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
590 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
591 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
592 
593 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
594 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
595 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
596 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
597 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
598 
599 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
600 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
601 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
602 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
603 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
604 
605 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
606 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
607 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
608 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
609 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
610 
611 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
612 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
613 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
614 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
615 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
616 
617 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
618 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
619 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
620 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
621 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
622 
623 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
624 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
625 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
626 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
627 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
628 
629 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
630 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
631 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
632 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
633 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
634 
635 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
636 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
637 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
638 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
639 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
640 
641 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
642 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
643 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
644 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
645 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
646 
647 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
648 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
649 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
650 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
651 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
652 
653 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
654 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
655 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
656 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
657 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
658 
659 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
660 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
661 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
662 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
663 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
664 
665 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
666 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
667 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
668 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
669 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
670 
671 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
672 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
673 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
674 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
675 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
676 
677 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
678 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
679 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
680 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
681 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
682 
683 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
684 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
685 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
686 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
687 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
688 
689 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
690 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
691 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
692 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
693 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
694 
695 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
696 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
697 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
698 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
699 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
700 
701 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
702 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
703 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
704 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
705 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
706 
707 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
708 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
709 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
710 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
711 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
712 
713 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
714 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
715 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
716 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
717 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
718 
719 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
720 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
721 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
722 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
723 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
724 
725 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
726 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
727 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
728 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
729 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
730 
731 /* Register: BPROT_CONFIG3 */
732 /* Description: Block protect configuration register 3 */
733 
734 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
735 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
736 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
737 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
738 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
739 
740 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
741 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
742 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
743 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
744 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
745 
746 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
747 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
748 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
749 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
750 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
751 
752 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
753 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
754 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
755 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
756 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
757 
758 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
759 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
760 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
761 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
762 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
763 
764 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
765 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
766 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
767 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
768 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
769 
770 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
771 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
772 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
773 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
774 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
775 
776 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
777 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
778 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
779 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
780 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
781 
782 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
783 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
784 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
785 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
786 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
787 
788 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
789 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
790 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
791 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
792 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
793 
794 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
795 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
796 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
797 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
798 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
799 
800 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
801 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
802 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
803 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
804 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
805 
806 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
807 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
808 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
809 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
810 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
811 
812 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
813 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
814 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
815 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
816 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
817 
818 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
819 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
820 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
821 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
822 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
823 
824 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
825 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
826 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
827 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
828 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
829 
830 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
831 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
832 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
833 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
834 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
835 
836 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
837 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
838 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
839 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
840 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
841 
842 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
843 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
844 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
845 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
846 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
847 
848 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
849 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
850 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
851 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
852 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
853 
854 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
855 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
856 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
857 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
858 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
859 
860 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
861 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
862 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
863 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
864 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
865 
866 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
867 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
868 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
869 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
870 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
871 
872 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
873 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
874 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
875 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
876 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
877 
878 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
879 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
880 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
881 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
882 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
883 
884 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
885 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
886 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
887 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
888 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
889 
890 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
891 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
892 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
893 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
894 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
895 
896 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
897 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
898 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
899 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
900 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
901 
902 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
903 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
904 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
905 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
906 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
907 
908 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
909 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
910 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
911 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
912 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
913 
914 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
915 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
916 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
917 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
918 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
919 
920 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
921 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
922 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
923 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
924 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
925 
926 
927 /* Peripheral: CCM */
928 /* Description: AES CCM Mode Encryption */
929 
930 /* Register: CCM_SHORTS */
931 /* Description: Shortcut register */
932 
933 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
934 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
935 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
936 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
937 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
938 
939 /* Register: CCM_INTENSET */
940 /* Description: Enable interrupt */
941 
942 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
943 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
944 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
945 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
946 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
947 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
948 
949 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
950 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
951 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
952 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
953 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
954 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
955 
956 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
957 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
958 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
959 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
960 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
961 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
962 
963 /* Register: CCM_INTENCLR */
964 /* Description: Disable interrupt */
965 
966 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
967 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
968 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
969 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
970 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
971 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
972 
973 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
974 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
975 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
976 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
977 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
978 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
979 
980 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
981 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
982 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
983 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
984 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
985 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
986 
987 /* Register: CCM_MICSTATUS */
988 /* Description: MIC check result */
989 
990 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
991 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
992 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
993 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
994 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
995 
996 /* Register: CCM_ENABLE */
997 /* Description: Enable */
998 
999 /* Bits 1..0 : Enable or disable CCM */
1000 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1001 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1002 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1003 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1004 
1005 /* Register: CCM_MODE */
1006 /* Description: Operation mode */
1007 
1008 /* Bit 24 : Packet length configuration */
1009 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
1010 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
1011 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
1012 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
1013 
1014 /* Bit 16 : Data rate that the CCM shall run in synch with */
1015 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
1016 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
1017 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
1018 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
1019 
1020 /* Bit 0 : The mode of operation to be used */
1021 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
1022 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
1023 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
1024 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
1025 
1026 /* Register: CCM_CNFPTR */
1027 /* Description: Pointer to data structure holding AES key and NONCE vector */
1028 
1029 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
1030 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
1031 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
1032 
1033 /* Register: CCM_INPTR */
1034 /* Description: Input pointer */
1035 
1036 /* Bits 31..0 : Input pointer */
1037 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
1038 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
1039 
1040 /* Register: CCM_OUTPTR */
1041 /* Description: Output pointer */
1042 
1043 /* Bits 31..0 : Output pointer */
1044 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
1045 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
1046 
1047 /* Register: CCM_SCRATCHPTR */
1048 /* Description: Pointer to data area used for temporary storage */
1049 
1050 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
1051 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
1052 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
1053 
1054 
1055 /* Peripheral: CLOCK */
1056 /* Description: Clock control */
1057 
1058 /* Register: CLOCK_INTENSET */
1059 /* Description: Enable interrupt */
1060 
1061 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
1062 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1063 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
1064 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
1065 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1066 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
1067 
1068 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
1069 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
1070 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
1071 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1072 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1073 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1074 
1075 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
1076 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1077 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1078 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1079 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1080 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1081 
1082 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
1083 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1084 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1085 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1086 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1087 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1088 
1089 /* Register: CLOCK_INTENCLR */
1090 /* Description: Disable interrupt */
1091 
1092 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
1093 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1094 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
1095 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
1096 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1097 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
1098 
1099 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
1100 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
1101 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
1102 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1103 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1104 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1105 
1106 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
1107 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1108 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1109 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1110 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1111 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1112 
1113 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
1114 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1115 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1116 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1117 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1118 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1119 
1120 /* Register: CLOCK_HFCLKRUN */
1121 /* Description: Status indicating that HFCLKSTART task has been triggered */
1122 
1123 /* Bit 0 : HFCLKSTART task triggered or not */
1124 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1125 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1126 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1127 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1128 
1129 /* Register: CLOCK_HFCLKSTAT */
1130 /* Description: HFCLK status */
1131 
1132 /* Bit 16 : HFCLK state */
1133 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1134 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1135 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
1136 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
1137 
1138 /* Bit 0 : Source of HFCLK */
1139 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1140 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1141 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
1142 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
1143 
1144 /* Register: CLOCK_LFCLKRUN */
1145 /* Description: Status indicating that LFCLKSTART task has been triggered */
1146 
1147 /* Bit 0 : LFCLKSTART task triggered or not */
1148 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1149 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1150 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1151 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1152 
1153 /* Register: CLOCK_LFCLKSTAT */
1154 /* Description: LFCLK status */
1155 
1156 /* Bit 16 : LFCLK state */
1157 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1158 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1159 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
1160 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
1161 
1162 /* Bits 1..0 : Source of LFCLK */
1163 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1164 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1165 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1166 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1167 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1168 
1169 /* Register: CLOCK_LFCLKSRCCOPY */
1170 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
1171 
1172 /* Bits 1..0 : Clock source */
1173 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
1174 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
1175 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1176 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1177 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1178 
1179 /* Register: CLOCK_LFCLKSRC */
1180 /* Description: Clock source for the LFCLK */
1181 
1182 /* Bit 17 : Enable or disable external source for LFCLK */
1183 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
1184 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
1185 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
1186 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
1187 
1188 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
1189 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
1190 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
1191 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
1192 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
1193 
1194 /* Bits 1..0 : Clock source */
1195 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1196 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1197 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1198 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1199 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1200 
1201 /* Register: CLOCK_CTIV */
1202 /* Description: Calibration timer interval */
1203 
1204 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
1205 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
1206 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
1207 
1208 /* Register: CLOCK_TRACECONFIG */
1209 /* Description: Clocking options for the Trace Port debug interface */
1210 
1211 /* Bits 17..16 : Pin multiplexing of trace signals. */
1212 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
1213 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
1214 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
1215 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
1216 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
1217 
1218 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
1219 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
1220 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
1221 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
1222 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
1223 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
1224 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
1225 
1226 
1227 /* Peripheral: COMP */
1228 /* Description: Comparator */
1229 
1230 /* Register: COMP_SHORTS */
1231 /* Description: Shortcut register */
1232 
1233 /* Bit 4 : Shortcut between CROSS event and STOP task */
1234 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
1235 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
1236 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1237 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1238 
1239 /* Bit 3 : Shortcut between UP event and STOP task */
1240 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
1241 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
1242 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1243 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1244 
1245 /* Bit 2 : Shortcut between DOWN event and STOP task */
1246 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1247 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
1248 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1249 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1250 
1251 /* Bit 1 : Shortcut between READY event and STOP task */
1252 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1253 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
1254 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1255 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1256 
1257 /* Bit 0 : Shortcut between READY event and SAMPLE task */
1258 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
1259 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
1260 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1261 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1262 
1263 /* Register: COMP_INTEN */
1264 /* Description: Enable or disable interrupt */
1265 
1266 /* Bit 3 : Enable or disable interrupt for CROSS event */
1267 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1268 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
1269 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1270 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1271 
1272 /* Bit 2 : Enable or disable interrupt for UP event */
1273 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1274 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
1275 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1276 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1277 
1278 /* Bit 1 : Enable or disable interrupt for DOWN event */
1279 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1280 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
1281 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1282 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1283 
1284 /* Bit 0 : Enable or disable interrupt for READY event */
1285 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
1286 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
1287 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1288 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1289 
1290 /* Register: COMP_INTENSET */
1291 /* Description: Enable interrupt */
1292 
1293 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
1294 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1295 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
1296 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1297 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1298 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1299 
1300 /* Bit 2 : Write '1' to Enable interrupt for UP event */
1301 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1302 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
1303 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1304 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1305 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1306 
1307 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
1308 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1309 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
1310 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1311 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1312 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1313 
1314 /* Bit 0 : Write '1' to Enable interrupt for READY event */
1315 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
1316 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
1317 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1318 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1319 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1320 
1321 /* Register: COMP_INTENCLR */
1322 /* Description: Disable interrupt */
1323 
1324 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
1325 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1326 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1327 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1328 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1329 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1330 
1331 /* Bit 2 : Write '1' to Disable interrupt for UP event */
1332 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1333 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1334 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1335 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1336 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1337 
1338 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
1339 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1340 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1341 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1342 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1343 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1344 
1345 /* Bit 0 : Write '1' to Disable interrupt for READY event */
1346 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1347 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1348 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1349 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1350 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1351 
1352 /* Register: COMP_RESULT */
1353 /* Description: Compare result */
1354 
1355 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1356 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1357 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1358 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1359 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1360 
1361 /* Register: COMP_ENABLE */
1362 /* Description: COMP enable */
1363 
1364 /* Bits 1..0 : Enable or disable COMP */
1365 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1366 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1367 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1368 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1369 
1370 /* Register: COMP_PSEL */
1371 /* Description: Pin select */
1372 
1373 /* Bits 2..0 : Analog pin select */
1374 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1375 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1376 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1377 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1378 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1379 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1380 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1381 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1382 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1383 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
1384 
1385 /* Register: COMP_REFSEL */
1386 /* Description: Reference source select for single-ended mode */
1387 
1388 /* Bits 2..0 : Reference select */
1389 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1390 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1391 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1392 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1393 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1394 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1395 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
1396 
1397 /* Register: COMP_EXTREFSEL */
1398 /* Description: External reference select */
1399 
1400 /* Bits 2..0 : External analog reference select */
1401 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1402 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1403 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1404 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1405 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1406 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1407 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1408 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1409 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1410 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1411 
1412 /* Register: COMP_TH */
1413 /* Description: Threshold configuration for hysteresis unit */
1414 
1415 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1416 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1417 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1418 
1419 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1420 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1421 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1422 
1423 /* Register: COMP_MODE */
1424 /* Description: Mode configuration */
1425 
1426 /* Bit 8 : Main operation modes */
1427 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1428 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1429 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1430 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1431 
1432 /* Bits 1..0 : Speed and power modes */
1433 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1434 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1435 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1436 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1437 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1438 
1439 /* Register: COMP_HYST */
1440 /* Description: Comparator hysteresis enable */
1441 
1442 /* Bit 0 : Comparator hysteresis */
1443 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1444 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1445 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1446 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1447 
1448 /* Register: COMP_ISOURCE */
1449 /* Description: Current source select on analog input */
1450 
1451 /* Bits 1..0 : Comparator hysteresis */
1452 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
1453 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
1454 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
1455 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1456 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1457 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
1458 
1459 
1460 /* Peripheral: ECB */
1461 /* Description: AES ECB Mode Encryption */
1462 
1463 /* Register: ECB_INTENSET */
1464 /* Description: Enable interrupt */
1465 
1466 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
1467 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1468 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1469 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1470 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1471 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1472 
1473 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
1474 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1475 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1476 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1477 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1478 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1479 
1480 /* Register: ECB_INTENCLR */
1481 /* Description: Disable interrupt */
1482 
1483 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
1484 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1485 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1486 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1487 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1488 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1489 
1490 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
1491 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1492 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1493 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1494 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1495 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1496 
1497 /* Register: ECB_ECBDATAPTR */
1498 /* Description: ECB block encrypt memory pointers */
1499 
1500 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1501 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1502 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1503 
1504 
1505 /* Peripheral: EGU */
1506 /* Description: Event Generator Unit 0 */
1507 
1508 /* Register: EGU_INTEN */
1509 /* Description: Enable or disable interrupt */
1510 
1511 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1512 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1513 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1514 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1515 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1516 
1517 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1518 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1519 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1520 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1521 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1522 
1523 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1524 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1525 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1526 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1527 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1528 
1529 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1530 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1531 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1532 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1533 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1534 
1535 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1536 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1537 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1538 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1539 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1540 
1541 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1542 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1543 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1544 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1545 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1546 
1547 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1548 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1549 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1550 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1551 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1552 
1553 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1554 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1555 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1556 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1557 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1558 
1559 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1560 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1561 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1562 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1563 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1564 
1565 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1566 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1567 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1568 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1569 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1570 
1571 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1572 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1573 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1574 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1575 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1576 
1577 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1578 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1579 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1580 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1581 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1582 
1583 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1584 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1585 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1586 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1587 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1588 
1589 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1590 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1591 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1592 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1593 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1594 
1595 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1596 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1597 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1598 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1599 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1600 
1601 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1602 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1603 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1604 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1605 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1606 
1607 /* Register: EGU_INTENSET */
1608 /* Description: Enable interrupt */
1609 
1610 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
1611 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1612 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1613 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1614 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1615 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1616 
1617 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
1618 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1619 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1620 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1621 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1622 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1623 
1624 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
1625 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1626 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1627 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1628 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1629 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1630 
1631 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
1632 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1633 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1634 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1635 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1636 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1637 
1638 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
1639 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1640 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1641 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1642 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1643 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1644 
1645 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
1646 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1647 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1648 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1649 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1650 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1651 
1652 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
1653 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1654 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1655 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1656 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1657 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1658 
1659 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
1660 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1661 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1662 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1663 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1664 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1665 
1666 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
1667 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1668 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1669 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1670 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1671 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1672 
1673 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
1674 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1675 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1676 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1677 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1678 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1679 
1680 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
1681 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1682 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1683 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1684 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1685 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1686 
1687 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
1688 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1689 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1690 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1691 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1692 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1693 
1694 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
1695 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1696 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1697 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1698 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1699 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1700 
1701 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1702 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1703 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1704 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1705 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1706 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1707 
1708 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
1709 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1710 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1711 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1712 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1713 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1714 
1715 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
1716 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1717 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1718 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1719 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1720 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1721 
1722 /* Register: EGU_INTENCLR */
1723 /* Description: Disable interrupt */
1724 
1725 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
1726 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1727 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1728 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1729 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1730 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1731 
1732 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
1733 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1734 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1735 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1736 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1737 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1738 
1739 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
1740 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1741 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1742 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1743 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1744 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1745 
1746 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
1747 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1748 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1749 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1750 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1751 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1752 
1753 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
1754 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1755 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1756 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1757 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1758 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1759 
1760 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
1761 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1762 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1763 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1764 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1765 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1766 
1767 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
1768 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1769 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1770 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1771 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1772 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1773 
1774 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
1775 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1776 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1777 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1778 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1779 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1780 
1781 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
1782 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1783 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1784 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1785 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1786 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1787 
1788 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
1789 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1790 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1791 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1792 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1793 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1794 
1795 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
1796 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1797 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1798 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1799 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1800 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1801 
1802 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
1803 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1804 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1805 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1806 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1807 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1808 
1809 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
1810 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1811 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1812 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1813 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1814 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1815 
1816 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1817 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1818 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1819 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1820 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1821 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1822 
1823 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
1824 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1825 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1826 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1827 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1828 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1829 
1830 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
1831 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1832 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1833 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1834 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1835 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1836 
1837 
1838 /* Peripheral: FICR */
1839 /* Description: Factory Information Configuration Registers */
1840 
1841 /* Register: FICR_CODEPAGESIZE */
1842 /* Description: Code memory page size */
1843 
1844 /* Bits 31..0 : Code memory page size */
1845 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1846 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1847 
1848 /* Register: FICR_CODESIZE */
1849 /* Description: Code memory size */
1850 
1851 /* Bits 31..0 : Code memory size in number of pages */
1852 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1853 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1854 
1855 /* Register: FICR_DEVICEID */
1856 /* Description: Description collection[0]:  Device identifier */
1857 
1858 /* Bits 31..0 : 64 bit unique device identifier */
1859 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1860 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1861 
1862 /* Register: FICR_ER */
1863 /* Description: Description collection[0]:  Encryption Root, word 0 */
1864 
1865 /* Bits 31..0 : Encryption Root, word n */
1866 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1867 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1868 
1869 /* Register: FICR_IR */
1870 /* Description: Description collection[0]:  Identity Root, word 0 */
1871 
1872 /* Bits 31..0 : Identity Root, word n */
1873 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1874 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1875 
1876 /* Register: FICR_DEVICEADDRTYPE */
1877 /* Description: Device address type */
1878 
1879 /* Bit 0 : Device address type */
1880 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1881 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1882 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1883 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1884 
1885 /* Register: FICR_DEVICEADDR */
1886 /* Description: Description collection[0]:  Device address 0 */
1887 
1888 /* Bits 31..0 : 48 bit device address */
1889 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1890 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1891 
1892 /* Register: FICR_INFO_PART */
1893 /* Description: Part code */
1894 
1895 /* Bits 31..0 : Part code */
1896 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1897 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1898 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
1899 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1900 
1901 /* Register: FICR_INFO_VARIANT */
1902 /* Description: Part Variant, Hardware version and Production configuration */
1903 
1904 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
1905 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1906 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1907 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1908 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
1909 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
1910 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
1911 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
1912 #define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */
1913 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1914 
1915 /* Register: FICR_INFO_PACKAGE */
1916 /* Description: Package option */
1917 
1918 /* Bits 31..0 : Package option */
1919 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1920 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1921 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
1922 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
1923 #define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
1924 #define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */
1925 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1926 
1927 /* Register: FICR_INFO_RAM */
1928 /* Description: RAM variant */
1929 
1930 /* Bits 31..0 : RAM variant */
1931 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1932 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1933 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
1934 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
1935 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
1936 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1937 
1938 /* Register: FICR_INFO_FLASH */
1939 /* Description: Flash variant */
1940 
1941 /* Bits 31..0 : Flash variant */
1942 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1943 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1944 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
1945 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
1946 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
1947 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1948 
1949 /* Register: FICR_TEMP_A0 */
1950 /* Description: Slope definition A0. */
1951 
1952 /* Bits 11..0 : A (slope definition) register. */
1953 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1954 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1955 
1956 /* Register: FICR_TEMP_A1 */
1957 /* Description: Slope definition A1. */
1958 
1959 /* Bits 11..0 : A (slope definition) register. */
1960 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1961 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1962 
1963 /* Register: FICR_TEMP_A2 */
1964 /* Description: Slope definition A2. */
1965 
1966 /* Bits 11..0 : A (slope definition) register. */
1967 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1968 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1969 
1970 /* Register: FICR_TEMP_A3 */
1971 /* Description: Slope definition A3. */
1972 
1973 /* Bits 11..0 : A (slope definition) register. */
1974 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1975 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1976 
1977 /* Register: FICR_TEMP_A4 */
1978 /* Description: Slope definition A4. */
1979 
1980 /* Bits 11..0 : A (slope definition) register. */
1981 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1982 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
1983 
1984 /* Register: FICR_TEMP_A5 */
1985 /* Description: Slope definition A5. */
1986 
1987 /* Bits 11..0 : A (slope definition) register. */
1988 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
1989 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
1990 
1991 /* Register: FICR_TEMP_B0 */
1992 /* Description: y-intercept B0. */
1993 
1994 /* Bits 13..0 : B (y-intercept) */
1995 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
1996 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
1997 
1998 /* Register: FICR_TEMP_B1 */
1999 /* Description: y-intercept B1. */
2000 
2001 /* Bits 13..0 : B (y-intercept) */
2002 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
2003 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
2004 
2005 /* Register: FICR_TEMP_B2 */
2006 /* Description: y-intercept B2. */
2007 
2008 /* Bits 13..0 : B (y-intercept) */
2009 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
2010 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
2011 
2012 /* Register: FICR_TEMP_B3 */
2013 /* Description: y-intercept B3. */
2014 
2015 /* Bits 13..0 : B (y-intercept) */
2016 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
2017 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
2018 
2019 /* Register: FICR_TEMP_B4 */
2020 /* Description: y-intercept B4. */
2021 
2022 /* Bits 13..0 : B (y-intercept) */
2023 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
2024 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
2025 
2026 /* Register: FICR_TEMP_B5 */
2027 /* Description: y-intercept B5. */
2028 
2029 /* Bits 13..0 : B (y-intercept) */
2030 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
2031 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
2032 
2033 /* Register: FICR_TEMP_T0 */
2034 /* Description: Segment end T0. */
2035 
2036 /* Bits 7..0 : T (segment end)register. */
2037 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
2038 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
2039 
2040 /* Register: FICR_TEMP_T1 */
2041 /* Description: Segment end T1. */
2042 
2043 /* Bits 7..0 : T (segment end)register. */
2044 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
2045 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
2046 
2047 /* Register: FICR_TEMP_T2 */
2048 /* Description: Segment end T2. */
2049 
2050 /* Bits 7..0 : T (segment end)register. */
2051 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
2052 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
2053 
2054 /* Register: FICR_TEMP_T3 */
2055 /* Description: Segment end T3. */
2056 
2057 /* Bits 7..0 : T (segment end)register. */
2058 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
2059 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
2060 
2061 /* Register: FICR_TEMP_T4 */
2062 /* Description: Segment end T4. */
2063 
2064 /* Bits 7..0 : T (segment end)register. */
2065 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
2066 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
2067 
2068 /* Register: FICR_NFC_TAGHEADER0 */
2069 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2070 
2071 /* Bits 31..24 : Unique identifier byte 3 */
2072 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
2073 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
2074 
2075 /* Bits 23..16 : Unique identifier byte 2 */
2076 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
2077 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
2078 
2079 /* Bits 15..8 : Unique identifier byte 1 */
2080 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
2081 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
2082 
2083 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
2084 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
2085 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
2086 
2087 /* Register: FICR_NFC_TAGHEADER1 */
2088 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2089 
2090 /* Bits 31..24 : Unique identifier byte 7 */
2091 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
2092 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
2093 
2094 /* Bits 23..16 : Unique identifier byte 6 */
2095 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
2096 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
2097 
2098 /* Bits 15..8 : Unique identifier byte 5 */
2099 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
2100 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
2101 
2102 /* Bits 7..0 : Unique identifier byte 4 */
2103 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
2104 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
2105 
2106 /* Register: FICR_NFC_TAGHEADER2 */
2107 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2108 
2109 /* Bits 31..24 : Unique identifier byte 11 */
2110 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
2111 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
2112 
2113 /* Bits 23..16 : Unique identifier byte 10 */
2114 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
2115 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
2116 
2117 /* Bits 15..8 : Unique identifier byte 9 */
2118 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
2119 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
2120 
2121 /* Bits 7..0 : Unique identifier byte 8 */
2122 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
2123 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
2124 
2125 /* Register: FICR_NFC_TAGHEADER3 */
2126 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2127 
2128 /* Bits 31..24 : Unique identifier byte 15 */
2129 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
2130 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
2131 
2132 /* Bits 23..16 : Unique identifier byte 14 */
2133 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
2134 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
2135 
2136 /* Bits 15..8 : Unique identifier byte 13 */
2137 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
2138 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
2139 
2140 /* Bits 7..0 : Unique identifier byte 12 */
2141 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
2142 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
2143 
2144 
2145 /* Peripheral: GPIOTE */
2146 /* Description: GPIO Tasks and Events */
2147 
2148 /* Register: GPIOTE_INTENSET */
2149 /* Description: Enable interrupt */
2150 
2151 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
2152 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
2153 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
2154 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2155 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2156 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2157 
2158 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
2159 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
2160 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
2161 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2162 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2163 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2164 
2165 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
2166 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
2167 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
2168 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2169 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2170 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2171 
2172 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
2173 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
2174 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
2175 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2176 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2177 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2178 
2179 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
2180 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
2181 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
2182 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2183 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2184 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2185 
2186 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
2187 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
2188 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
2189 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2190 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2191 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2192 
2193 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2194 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2195 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
2196 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2197 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2198 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2199 
2200 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
2201 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2202 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
2203 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2204 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2205 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2206 
2207 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
2208 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
2209 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
2210 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2211 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2212 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2213 
2214 /* Register: GPIOTE_INTENCLR */
2215 /* Description: Disable interrupt */
2216 
2217 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
2218 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2219 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2220 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2221 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2222 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2223 
2224 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
2225 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
2226 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
2227 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2228 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2229 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2230 
2231 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
2232 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
2233 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
2234 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2235 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2236 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2237 
2238 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
2239 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
2240 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
2241 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2242 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2243 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2244 
2245 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
2246 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
2247 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
2248 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2249 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2250 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2251 
2252 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
2253 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
2254 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
2255 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2256 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2257 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2258 
2259 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2260 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2261 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
2262 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2263 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2264 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2265 
2266 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
2267 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2268 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
2269 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2270 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2271 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2272 
2273 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
2274 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
2275 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
2276 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2277 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2278 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2279 
2280 /* Register: GPIOTE_CONFIG */
2281 /* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
2282 
2283 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2284 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2285 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2286 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2287 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2288 
2289 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2290 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2291 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2292 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2293 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2294 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2295 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2296 
2297 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
2298 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2299 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2300 
2301 /* Bits 1..0 : Mode */
2302 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2303 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2304 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2305 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2306 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2307 
2308 
2309 /* Peripheral: I2S */
2310 /* Description: Inter-IC Sound */
2311 
2312 /* Register: I2S_INTEN */
2313 /* Description: Enable or disable interrupt */
2314 
2315 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2316 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2317 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2318 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2319 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2320 
2321 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2322 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2323 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2324 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2325 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2326 
2327 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2328 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2329 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2330 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2331 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2332 
2333 /* Register: I2S_INTENSET */
2334 /* Description: Enable interrupt */
2335 
2336 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
2337 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2338 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2339 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2340 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2341 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2342 
2343 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2344 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2345 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2346 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2347 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2348 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2349 
2350 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
2351 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2352 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2353 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2354 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2355 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2356 
2357 /* Register: I2S_INTENCLR */
2358 /* Description: Disable interrupt */
2359 
2360 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
2361 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2362 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2363 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2364 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2365 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2366 
2367 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2368 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2369 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2370 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2371 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2372 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2373 
2374 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
2375 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2376 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2377 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2378 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2379 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2380 
2381 /* Register: I2S_ENABLE */
2382 /* Description: Enable I2S module. */
2383 
2384 /* Bit 0 : Enable I2S module. */
2385 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2386 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2387 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2388 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2389 
2390 /* Register: I2S_CONFIG_MODE */
2391 /* Description: I2S mode. */
2392 
2393 /* Bit 0 : I2S mode. */
2394 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2395 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
2396 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
2397 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
2398 
2399 /* Register: I2S_CONFIG_RXEN */
2400 /* Description: Reception (RX) enable. */
2401 
2402 /* Bit 0 : Reception (RX) enable. */
2403 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
2404 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
2405 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
2406 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2407 
2408 /* Register: I2S_CONFIG_TXEN */
2409 /* Description: Transmission (TX) enable. */
2410 
2411 /* Bit 0 : Transmission (TX) enable. */
2412 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
2413 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
2414 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
2415 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2416 
2417 /* Register: I2S_CONFIG_MCKEN */
2418 /* Description: Master clock generator enable. */
2419 
2420 /* Bit 0 : Master clock generator enable. */
2421 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
2422 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
2423 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
2424 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
2425 
2426 /* Register: I2S_CONFIG_MCKFREQ */
2427 /* Description: Master clock generator frequency. */
2428 
2429 /* Bits 31..0 : Master clock generator frequency. */
2430 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
2431 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
2432 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
2433 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
2434 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
2435 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
2436 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
2437 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
2438 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
2439 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
2440 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
2441 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
2442 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
2443 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
2444 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
2445 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
2446 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
2447 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
2448 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
2449 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
2450 
2451 /* Register: I2S_CONFIG_RATIO */
2452 /* Description: MCK / LRCK ratio. */
2453 
2454 /* Bits 3..0 : MCK / LRCK ratio. */
2455 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
2456 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
2457 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
2458 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2459 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2460 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
2461 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
2462 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
2463 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
2464 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
2465 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
2466 
2467 /* Register: I2S_CONFIG_SWIDTH */
2468 /* Description: Sample width. */
2469 
2470 /* Bits 1..0 : Sample width. */
2471 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2472 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2473 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2474 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2475 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2476 
2477 /* Register: I2S_CONFIG_ALIGN */
2478 /* Description: Alignment of sample within a frame. */
2479 
2480 /* Bit 0 : Alignment of sample within a frame. */
2481 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2482 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2483 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2484 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2485 
2486 /* Register: I2S_CONFIG_FORMAT */
2487 /* Description: Frame format. */
2488 
2489 /* Bit 0 : Frame format. */
2490 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2491 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2492 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2493 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2494 
2495 /* Register: I2S_CONFIG_CHANNELS */
2496 /* Description: Enable channels. */
2497 
2498 /* Bits 1..0 : Enable channels. */
2499 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2500 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2501 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2502 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2503 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2504 
2505 /* Register: I2S_RXD_PTR */
2506 /* Description: Receive buffer RAM start address. */
2507 
2508 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2509 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2510 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2511 
2512 /* Register: I2S_TXD_PTR */
2513 /* Description: Transmit buffer RAM start address. */
2514 
2515 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2516 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2517 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2518 
2519 /* Register: I2S_RXTXD_MAXCNT */
2520 /* Description: Size of RXD and TXD buffers. */
2521 
2522 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2523 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2524 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2525 
2526 /* Register: I2S_PSEL_MCK */
2527 /* Description: Pin select for MCK signal. */
2528 
2529 /* Bit 31 : Connection */
2530 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2531 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2532 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2533 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2534 
2535 /* Bits 4..0 : Pin number */
2536 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2537 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2538 
2539 /* Register: I2S_PSEL_SCK */
2540 /* Description: Pin select for SCK signal. */
2541 
2542 /* Bit 31 : Connection */
2543 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2544 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2545 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2546 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2547 
2548 /* Bits 4..0 : Pin number */
2549 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2550 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2551 
2552 /* Register: I2S_PSEL_LRCK */
2553 /* Description: Pin select for LRCK signal. */
2554 
2555 /* Bit 31 : Connection */
2556 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2557 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2558 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2559 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2560 
2561 /* Bits 4..0 : Pin number */
2562 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2563 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2564 
2565 /* Register: I2S_PSEL_SDIN */
2566 /* Description: Pin select for SDIN signal. */
2567 
2568 /* Bit 31 : Connection */
2569 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2570 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2571 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2572 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2573 
2574 /* Bits 4..0 : Pin number */
2575 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2576 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2577 
2578 /* Register: I2S_PSEL_SDOUT */
2579 /* Description: Pin select for SDOUT signal. */
2580 
2581 /* Bit 31 : Connection */
2582 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2583 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2584 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2585 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2586 
2587 /* Bits 4..0 : Pin number */
2588 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2589 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2590 
2591 
2592 /* Peripheral: LPCOMP */
2593 /* Description: Low Power Comparator */
2594 
2595 /* Register: LPCOMP_SHORTS */
2596 /* Description: Shortcut register */
2597 
2598 /* Bit 4 : Shortcut between CROSS event and STOP task */
2599 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
2600 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
2601 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2602 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2603 
2604 /* Bit 3 : Shortcut between UP event and STOP task */
2605 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
2606 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
2607 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2608 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2609 
2610 /* Bit 2 : Shortcut between DOWN event and STOP task */
2611 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2612 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
2613 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2614 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2615 
2616 /* Bit 1 : Shortcut between READY event and STOP task */
2617 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2618 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
2619 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2620 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2621 
2622 /* Bit 0 : Shortcut between READY event and SAMPLE task */
2623 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
2624 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
2625 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2626 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2627 
2628 /* Register: LPCOMP_INTENSET */
2629 /* Description: Enable interrupt */
2630 
2631 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
2632 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2633 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
2634 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2635 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2636 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2637 
2638 /* Bit 2 : Write '1' to Enable interrupt for UP event */
2639 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2640 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2641 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2642 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2643 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2644 
2645 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
2646 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2647 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
2648 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2649 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2650 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2651 
2652 /* Bit 0 : Write '1' to Enable interrupt for READY event */
2653 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
2654 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
2655 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2656 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2657 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2658 
2659 /* Register: LPCOMP_INTENCLR */
2660 /* Description: Disable interrupt */
2661 
2662 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
2663 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2664 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
2665 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2666 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2667 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2668 
2669 /* Bit 2 : Write '1' to Disable interrupt for UP event */
2670 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2671 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2672 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2673 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2674 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2675 
2676 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
2677 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2678 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
2679 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2680 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2681 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2682 
2683 /* Bit 0 : Write '1' to Disable interrupt for READY event */
2684 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
2685 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
2686 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2687 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2688 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2689 
2690 /* Register: LPCOMP_RESULT */
2691 /* Description: Compare result */
2692 
2693 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
2694 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
2695 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
2696 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
2697 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
2698 
2699 /* Register: LPCOMP_ENABLE */
2700 /* Description: Enable LPCOMP */
2701 
2702 /* Bits 1..0 : Enable or disable LPCOMP */
2703 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2704 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2705 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2706 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2707 
2708 /* Register: LPCOMP_PSEL */
2709 /* Description: Input pin select */
2710 
2711 /* Bits 2..0 : Analog pin select */
2712 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
2713 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
2714 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
2715 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
2716 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2717 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
2718 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
2719 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
2720 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
2721 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
2722 
2723 /* Register: LPCOMP_REFSEL */
2724 /* Description: Reference select */
2725 
2726 /* Bits 3..0 : Reference select */
2727 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
2728 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
2729 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
2730 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2731 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2732 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
2733 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
2734 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
2735 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
2736 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
2737 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
2738 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
2739 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
2740 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
2741 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
2742 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
2743 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
2744 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
2745 
2746 /* Register: LPCOMP_EXTREFSEL */
2747 /* Description: External reference select */
2748 
2749 /* Bit 0 : External analog reference select */
2750 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
2751 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
2752 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
2753 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
2754 
2755 /* Register: LPCOMP_ANADETECT */
2756 /* Description: Analog detect configuration */
2757 
2758 /* Bits 1..0 : Analog detect configuration */
2759 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
2760 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
2761 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
2762 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
2763 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2764 
2765 /* Register: LPCOMP_HYST */
2766 /* Description: Comparator hysteresis enable */
2767 
2768 /* Bit 0 : Comparator hysteresis enable */
2769 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
2770 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
2771 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
2772 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
2773 
2774 
2775 /* Peripheral: MWU */
2776 /* Description: Memory Watch Unit */
2777 
2778 /* Register: MWU_INTEN */
2779 /* Description: Enable or disable interrupt */
2780 
2781 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2782 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2783 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2784 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2785 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2786 
2787 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2788 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2789 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2790 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2791 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2792 
2793 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2794 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2795 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2796 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2797 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2798 
2799 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2800 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2801 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2802 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2803 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2804 
2805 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2806 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2807 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2808 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2809 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2810 
2811 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2812 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2813 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2814 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2815 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2816 
2817 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2818 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2819 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2820 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2821 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2822 
2823 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2824 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2825 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2826 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2827 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2828 
2829 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2830 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2831 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2832 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2833 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2834 
2835 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2836 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2837 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2838 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2839 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2840 
2841 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2842 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2843 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2844 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2845 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2846 
2847 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2848 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2849 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2850 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2851 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2852 
2853 /* Register: MWU_INTENSET */
2854 /* Description: Enable interrupt */
2855 
2856 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
2857 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2858 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2859 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2860 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2861 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2862 
2863 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
2864 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2865 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2866 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2867 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2868 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2869 
2870 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
2871 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2872 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2873 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2874 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2875 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2876 
2877 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
2878 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2879 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2880 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2881 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2882 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2883 
2884 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
2885 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2886 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2887 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2888 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2889 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2890 
2891 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
2892 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2893 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2894 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2895 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2896 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2897 
2898 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2899 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2900 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2901 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2902 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2903 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2904 
2905 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2906 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2907 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2908 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2909 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2910 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2911 
2912 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
2913 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2914 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2915 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2916 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2917 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2918 
2919 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2920 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2921 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2922 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2923 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2924 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2925 
2926 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
2927 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2928 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2929 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2930 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2931 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2932 
2933 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
2934 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2935 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2936 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2937 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2938 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2939 
2940 /* Register: MWU_INTENCLR */
2941 /* Description: Disable interrupt */
2942 
2943 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
2944 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2945 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2946 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2947 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2948 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2949 
2950 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
2951 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2952 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2953 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2954 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2955 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2956 
2957 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
2958 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2959 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2960 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2961 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2962 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2963 
2964 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
2965 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2966 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2967 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2968 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2969 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2970 
2971 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
2972 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2973 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2974 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2975 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2976 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2977 
2978 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
2979 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2980 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2981 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2982 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2983 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2984 
2985 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
2986 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2987 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2988 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2989 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2990 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2991 
2992 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
2993 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2994 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2995 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2996 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2997 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
2998 
2999 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
3000 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3001 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3002 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3003 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3004 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3005 
3006 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3007 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3008 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3009 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3010 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3011 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3012 
3013 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
3014 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3015 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3016 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3017 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3018 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3019 
3020 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
3021 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3022 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3023 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3024 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3025 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3026 
3027 /* Register: MWU_NMIEN */
3028 /* Description: Enable or disable non-maskable interrupt */
3029 
3030 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
3031 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3032 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3033 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3034 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3035 
3036 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
3037 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3038 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3039 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3040 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3041 
3042 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
3043 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3044 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3045 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3046 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3047 
3048 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
3049 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3050 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3051 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3052 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3053 
3054 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
3055 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3056 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3057 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
3058 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3059 
3060 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
3061 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3062 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3063 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
3064 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3065 
3066 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
3067 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3068 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3069 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
3070 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3071 
3072 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
3073 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3074 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3075 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
3076 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3077 
3078 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
3079 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3080 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3081 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
3082 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3083 
3084 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3085 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3086 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3087 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
3088 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3089 
3090 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
3091 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3092 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3093 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
3094 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3095 
3096 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
3097 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3098 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3099 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3100 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3101 
3102 /* Register: MWU_NMIENSET */
3103 /* Description: Enable non-maskable interrupt */
3104 
3105 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
3106 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3107 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3108 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3109 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3110 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3111 
3112 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
3113 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3114 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3115 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3116 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3117 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3118 
3119 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
3120 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3121 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3122 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3123 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3124 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3125 
3126 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
3127 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3128 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3129 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3130 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3131 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3132 
3133 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
3134 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3135 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3136 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3137 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3138 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3139 
3140 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
3141 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3142 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3143 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3144 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3145 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3146 
3147 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3148 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3149 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3150 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3151 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3152 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3153 
3154 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3155 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3156 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3157 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3158 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3159 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3160 
3161 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
3162 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3163 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3164 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3165 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3166 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3167 
3168 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3169 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3170 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3171 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3172 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3173 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3174 
3175 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
3176 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3177 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3178 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3179 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3180 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3181 
3182 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
3183 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3184 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3185 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3186 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3187 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3188 
3189 /* Register: MWU_NMIENCLR */
3190 /* Description: Disable non-maskable interrupt */
3191 
3192 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
3193 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3194 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3195 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3196 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3197 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3198 
3199 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
3200 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3201 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3202 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3203 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3204 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3205 
3206 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
3207 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3208 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3209 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3210 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3211 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3212 
3213 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
3214 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3215 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3216 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3217 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3218 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3219 
3220 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
3221 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3222 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3223 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3224 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3225 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3226 
3227 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
3228 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3229 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3230 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3231 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3232 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3233 
3234 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3235 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3236 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3237 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3238 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3239 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3240 
3241 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3242 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3243 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3244 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3245 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3246 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3247 
3248 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
3249 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3250 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3251 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3252 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3253 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3254 
3255 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3256 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3257 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3258 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3259 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3260 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3261 
3262 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
3263 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3264 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3265 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3266 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3267 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3268 
3269 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
3270 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3271 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3272 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3273 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3274 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3275 
3276 /* Register: MWU_PERREGION_SUBSTATWA */
3277 /* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
3278 
3279 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3280 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3281 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
3282 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
3283 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
3284 
3285 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3286 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3287 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
3288 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
3289 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
3290 
3291 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3292 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3293 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
3294 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
3295 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
3296 
3297 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3298 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3299 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
3300 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
3301 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
3302 
3303 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3304 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3305 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
3306 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
3307 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
3308 
3309 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3310 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3311 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
3312 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
3313 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
3314 
3315 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3316 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3317 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
3318 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
3319 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
3320 
3321 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3322 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3323 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
3324 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
3325 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
3326 
3327 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3328 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3329 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
3330 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
3331 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
3332 
3333 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3334 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3335 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
3336 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
3337 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
3338 
3339 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3340 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3341 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
3342 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
3343 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
3344 
3345 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3346 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3347 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
3348 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
3349 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
3350 
3351 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3352 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3353 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
3354 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
3355 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
3356 
3357 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3358 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3359 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
3360 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
3361 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
3362 
3363 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3364 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3365 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
3366 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
3367 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
3368 
3369 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3370 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3371 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
3372 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
3373 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
3374 
3375 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3376 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3377 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
3378 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
3379 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
3380 
3381 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3382 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3383 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
3384 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
3385 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
3386 
3387 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3388 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3389 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
3390 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
3391 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
3392 
3393 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3394 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3395 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
3396 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
3397 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
3398 
3399 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3400 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3401 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
3402 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
3403 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
3404 
3405 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3406 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3407 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
3408 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
3409 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
3410 
3411 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3412 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3413 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
3414 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
3415 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3416 
3417 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3418 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3419 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
3420 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
3421 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3422 
3423 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3424 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3425 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
3426 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
3427 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3428 
3429 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3430 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3431 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
3432 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
3433 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3434 
3435 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3436 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3437 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
3438 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
3439 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3440 
3441 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3442 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3443 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
3444 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
3445 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3446 
3447 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3448 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3449 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
3450 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
3451 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3452 
3453 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3454 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3455 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
3456 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
3457 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3458 
3459 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3460 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3461 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
3462 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
3463 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3464 
3465 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3466 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3467 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
3468 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
3469 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3470 
3471 /* Register: MWU_PERREGION_SUBSTATRA */
3472 /* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
3473 
3474 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3475 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3476 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
3477 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
3478 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3479 
3480 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3481 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3482 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
3483 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
3484 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3485 
3486 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3487 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3488 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
3489 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
3490 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3491 
3492 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3493 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3494 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
3495 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
3496 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3497 
3498 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3499 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3500 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
3501 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
3502 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3503 
3504 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3505 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3506 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
3507 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
3508 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3509 
3510 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3511 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3512 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
3513 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
3514 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3515 
3516 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3517 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3518 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
3519 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
3520 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3521 
3522 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3523 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3524 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
3525 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
3526 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3527 
3528 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3529 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3530 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
3531 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
3532 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3533 
3534 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3535 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3536 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
3537 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
3538 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3539 
3540 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3541 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3542 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
3543 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
3544 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3545 
3546 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3547 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3548 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
3549 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
3550 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3551 
3552 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3553 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3554 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
3555 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
3556 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3557 
3558 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3559 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3560 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
3561 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
3562 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3563 
3564 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3565 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3566 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
3567 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
3568 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3569 
3570 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3571 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3572 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
3573 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
3574 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3575 
3576 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3577 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3578 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
3579 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
3580 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3581 
3582 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3583 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3584 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
3585 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
3586 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3587 
3588 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3589 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3590 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
3591 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
3592 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3593 
3594 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3595 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3596 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
3597 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
3598 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3599 
3600 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3601 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3602 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
3603 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
3604 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3605 
3606 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3607 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3608 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
3609 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3610 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3611 
3612 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3613 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3614 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
3615 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3616 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3617 
3618 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3619 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3620 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
3621 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3622 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3623 
3624 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3625 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3626 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
3627 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3628 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3629 
3630 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3631 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3632 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
3633 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3634 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3635 
3636 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3637 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3638 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
3639 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3640 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3641 
3642 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3643 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3644 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
3645 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3646 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3647 
3648 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3649 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3650 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
3651 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3652 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3653 
3654 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3655 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3656 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
3657 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3658 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3659 
3660 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3661 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3662 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
3663 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3664 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3665 
3666 /* Register: MWU_REGIONEN */
3667 /* Description: Enable/disable regions watch */
3668 
3669 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3670 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3671 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3672 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3673 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3674 
3675 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3676 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3677 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3678 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3679 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3680 
3681 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3682 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3683 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3684 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3685 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3686 
3687 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3688 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3689 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3690 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3691 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3692 
3693 /* Bit 7 : Enable/disable read access watch in region[3] */
3694 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3695 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3696 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3697 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3698 
3699 /* Bit 6 : Enable/disable write access watch in region[3] */
3700 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3701 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3702 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3703 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3704 
3705 /* Bit 5 : Enable/disable read access watch in region[2] */
3706 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3707 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3708 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3709 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3710 
3711 /* Bit 4 : Enable/disable write access watch in region[2] */
3712 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3713 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3714 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3715 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3716 
3717 /* Bit 3 : Enable/disable read access watch in region[1] */
3718 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3719 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3720 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3721 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3722 
3723 /* Bit 2 : Enable/disable write access watch in region[1] */
3724 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3725 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3726 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3727 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3728 
3729 /* Bit 1 : Enable/disable read access watch in region[0] */
3730 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3731 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3732 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3733 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3734 
3735 /* Bit 0 : Enable/disable write access watch in region[0] */
3736 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3737 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3738 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3739 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3740 
3741 /* Register: MWU_REGIONENSET */
3742 /* Description: Enable regions watch */
3743 
3744 /* Bit 27 : Enable read access watch in PREGION[1] */
3745 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3746 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3747 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3748 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3749 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3750 
3751 /* Bit 26 : Enable write access watch in PREGION[1] */
3752 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3753 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3754 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3755 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3756 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3757 
3758 /* Bit 25 : Enable read access watch in PREGION[0] */
3759 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3760 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3761 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3762 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3763 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3764 
3765 /* Bit 24 : Enable write access watch in PREGION[0] */
3766 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3767 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3768 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3769 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3770 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3771 
3772 /* Bit 7 : Enable read access watch in region[3] */
3773 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3774 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3775 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3776 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3777 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3778 
3779 /* Bit 6 : Enable write access watch in region[3] */
3780 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3781 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3782 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3783 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3784 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3785 
3786 /* Bit 5 : Enable read access watch in region[2] */
3787 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3788 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3789 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3790 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3791 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3792 
3793 /* Bit 4 : Enable write access watch in region[2] */
3794 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3795 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3796 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3797 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3798 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3799 
3800 /* Bit 3 : Enable read access watch in region[1] */
3801 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3802 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3803 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3804 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3805 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3806 
3807 /* Bit 2 : Enable write access watch in region[1] */
3808 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3809 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3810 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3811 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3812 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3813 
3814 /* Bit 1 : Enable read access watch in region[0] */
3815 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3816 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3817 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3818 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3819 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3820 
3821 /* Bit 0 : Enable write access watch in region[0] */
3822 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3823 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3824 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3825 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3826 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3827 
3828 /* Register: MWU_REGIONENCLR */
3829 /* Description: Disable regions watch */
3830 
3831 /* Bit 27 : Disable read access watch in PREGION[1] */
3832 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3833 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3834 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3835 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3836 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3837 
3838 /* Bit 26 : Disable write access watch in PREGION[1] */
3839 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3840 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3841 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3842 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3843 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3844 
3845 /* Bit 25 : Disable read access watch in PREGION[0] */
3846 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3847 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3848 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3849 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3850 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3851 
3852 /* Bit 24 : Disable write access watch in PREGION[0] */
3853 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3854 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3855 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3856 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3857 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3858 
3859 /* Bit 7 : Disable read access watch in region[3] */
3860 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3861 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3862 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3863 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3864 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3865 
3866 /* Bit 6 : Disable write access watch in region[3] */
3867 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3868 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3869 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3870 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3871 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3872 
3873 /* Bit 5 : Disable read access watch in region[2] */
3874 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3875 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3876 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3877 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3878 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3879 
3880 /* Bit 4 : Disable write access watch in region[2] */
3881 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3882 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3883 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3884 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3885 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3886 
3887 /* Bit 3 : Disable read access watch in region[1] */
3888 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3889 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3890 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3891 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3892 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3893 
3894 /* Bit 2 : Disable write access watch in region[1] */
3895 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3896 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3897 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3898 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3899 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3900 
3901 /* Bit 1 : Disable read access watch in region[0] */
3902 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3903 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3904 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3905 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3906 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3907 
3908 /* Bit 0 : Disable write access watch in region[0] */
3909 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3910 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3911 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3912 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3913 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
3914 
3915 /* Register: MWU_REGION_START */
3916 /* Description: Description cluster[0]:  Start address for region 0 */
3917 
3918 /* Bits 31..0 : Start address for region */
3919 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
3920 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
3921 
3922 /* Register: MWU_REGION_END */
3923 /* Description: Description cluster[0]:  End address of region 0 */
3924 
3925 /* Bits 31..0 : End address of region. */
3926 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
3927 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
3928 
3929 /* Register: MWU_PREGION_START */
3930 /* Description: Description cluster[0]:  Reserved for future use */
3931 
3932 /* Bits 31..0 : Reserved for future use */
3933 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
3934 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
3935 
3936 /* Register: MWU_PREGION_END */
3937 /* Description: Description cluster[0]:  Reserved for future use */
3938 
3939 /* Bits 31..0 : Reserved for future use */
3940 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
3941 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
3942 
3943 /* Register: MWU_PREGION_SUBS */
3944 /* Description: Description cluster[0]:  Subregions of region 0 */
3945 
3946 /* Bit 31 : Include or exclude subregion 31 in region */
3947 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
3948 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
3949 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
3950 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
3951 
3952 /* Bit 30 : Include or exclude subregion 30 in region */
3953 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
3954 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
3955 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
3956 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
3957 
3958 /* Bit 29 : Include or exclude subregion 29 in region */
3959 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
3960 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
3961 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
3962 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
3963 
3964 /* Bit 28 : Include or exclude subregion 28 in region */
3965 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
3966 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
3967 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
3968 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
3969 
3970 /* Bit 27 : Include or exclude subregion 27 in region */
3971 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
3972 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
3973 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
3974 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
3975 
3976 /* Bit 26 : Include or exclude subregion 26 in region */
3977 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
3978 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
3979 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
3980 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
3981 
3982 /* Bit 25 : Include or exclude subregion 25 in region */
3983 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
3984 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
3985 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
3986 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
3987 
3988 /* Bit 24 : Include or exclude subregion 24 in region */
3989 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
3990 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
3991 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
3992 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
3993 
3994 /* Bit 23 : Include or exclude subregion 23 in region */
3995 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
3996 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
3997 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
3998 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
3999 
4000 /* Bit 22 : Include or exclude subregion 22 in region */
4001 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
4002 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
4003 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
4004 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
4005 
4006 /* Bit 21 : Include or exclude subregion 21 in region */
4007 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
4008 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
4009 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
4010 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
4011 
4012 /* Bit 20 : Include or exclude subregion 20 in region */
4013 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
4014 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
4015 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
4016 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
4017 
4018 /* Bit 19 : Include or exclude subregion 19 in region */
4019 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
4020 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
4021 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
4022 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
4023 
4024 /* Bit 18 : Include or exclude subregion 18 in region */
4025 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
4026 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
4027 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
4028 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
4029 
4030 /* Bit 17 : Include or exclude subregion 17 in region */
4031 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
4032 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
4033 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
4034 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
4035 
4036 /* Bit 16 : Include or exclude subregion 16 in region */
4037 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
4038 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
4039 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
4040 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
4041 
4042 /* Bit 15 : Include or exclude subregion 15 in region */
4043 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
4044 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
4045 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
4046 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
4047 
4048 /* Bit 14 : Include or exclude subregion 14 in region */
4049 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
4050 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
4051 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
4052 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
4053 
4054 /* Bit 13 : Include or exclude subregion 13 in region */
4055 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
4056 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
4057 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
4058 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
4059 
4060 /* Bit 12 : Include or exclude subregion 12 in region */
4061 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
4062 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
4063 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
4064 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
4065 
4066 /* Bit 11 : Include or exclude subregion 11 in region */
4067 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
4068 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
4069 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
4070 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
4071 
4072 /* Bit 10 : Include or exclude subregion 10 in region */
4073 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
4074 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
4075 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
4076 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
4077 
4078 /* Bit 9 : Include or exclude subregion 9 in region */
4079 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
4080 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
4081 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
4082 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
4083 
4084 /* Bit 8 : Include or exclude subregion 8 in region */
4085 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
4086 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
4087 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
4088 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
4089 
4090 /* Bit 7 : Include or exclude subregion 7 in region */
4091 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
4092 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
4093 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
4094 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
4095 
4096 /* Bit 6 : Include or exclude subregion 6 in region */
4097 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
4098 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
4099 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
4100 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
4101 
4102 /* Bit 5 : Include or exclude subregion 5 in region */
4103 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
4104 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
4105 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
4106 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
4107 
4108 /* Bit 4 : Include or exclude subregion 4 in region */
4109 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
4110 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
4111 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
4112 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
4113 
4114 /* Bit 3 : Include or exclude subregion 3 in region */
4115 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
4116 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
4117 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
4118 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
4119 
4120 /* Bit 2 : Include or exclude subregion 2 in region */
4121 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4122 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
4123 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
4124 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
4125 
4126 /* Bit 1 : Include or exclude subregion 1 in region */
4127 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
4128 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
4129 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
4130 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
4131 
4132 /* Bit 0 : Include or exclude subregion 0 in region */
4133 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
4134 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
4135 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
4136 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4137 
4138 
4139 /* Peripheral: NFCT */
4140 /* Description: NFC-A compatible radio */
4141 
4142 /* Register: NFCT_SHORTS */
4143 /* Description: Shortcut register */
4144 
4145 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
4146 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4147 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
4148 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4149 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4150 
4151 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
4152 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
4153 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
4154 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4155 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4156 
4157 /* Register: NFCT_INTEN */
4158 /* Description: Enable or disable interrupt */
4159 
4160 /* Bit 20 : Enable or disable interrupt for STARTED event */
4161 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4162 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4163 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4164 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4165 
4166 /* Bit 19 : Enable or disable interrupt for SELECTED event */
4167 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4168 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4169 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4170 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4171 
4172 /* Bit 18 : Enable or disable interrupt for COLLISION event */
4173 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4174 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4175 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4176 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4177 
4178 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4179 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4180 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4181 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4182 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4183 
4184 /* Bit 12 : Enable or disable interrupt for ENDTX event */
4185 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4186 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4187 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4188 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4189 
4190 /* Bit 11 : Enable or disable interrupt for ENDRX event */
4191 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4192 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4193 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4194 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4195 
4196 /* Bit 10 : Enable or disable interrupt for RXERROR event */
4197 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4198 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4199 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4200 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4201 
4202 /* Bit 7 : Enable or disable interrupt for ERROR event */
4203 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4204 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
4205 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4206 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4207 
4208 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4209 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4210 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4211 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4212 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4213 
4214 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4215 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4216 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4217 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4218 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4219 
4220 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4221 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4222 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4223 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4224 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4225 
4226 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4227 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4228 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4229 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4230 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4231 
4232 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4233 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4234 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4235 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4236 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4237 
4238 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4239 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4240 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4241 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4242 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4243 
4244 /* Bit 0 : Enable or disable interrupt for READY event */
4245 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
4246 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
4247 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4248 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4249 
4250 /* Register: NFCT_INTENSET */
4251 /* Description: Enable interrupt */
4252 
4253 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
4254 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4255 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4256 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4257 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4258 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4259 
4260 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
4261 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4262 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4263 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4264 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4265 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4266 
4267 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
4268 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4269 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4270 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4271 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4272 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4273 
4274 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
4275 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4276 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4277 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4278 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4279 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4280 
4281 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
4282 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4283 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4284 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4285 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4286 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4287 
4288 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
4289 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4290 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4291 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4292 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4293 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4294 
4295 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
4296 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4297 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4298 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4299 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4300 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4301 
4302 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
4303 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4304 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
4305 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4306 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4307 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4308 
4309 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
4310 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4311 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4312 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4313 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4314 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4315 
4316 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
4317 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4318 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4319 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4320 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4321 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4322 
4323 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
4324 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4325 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4326 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4327 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4328 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4329 
4330 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
4331 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4332 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4333 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4334 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4335 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4336 
4337 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4338 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4339 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4340 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4341 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4342 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4343 
4344 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
4345 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4346 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4347 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4348 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4349 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4350 
4351 /* Bit 0 : Write '1' to Enable interrupt for READY event */
4352 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
4353 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
4354 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4355 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4356 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4357 
4358 /* Register: NFCT_INTENCLR */
4359 /* Description: Disable interrupt */
4360 
4361 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
4362 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4363 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4364 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4365 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4366 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4367 
4368 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
4369 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4370 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4371 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4372 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4373 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4374 
4375 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
4376 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4377 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4378 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4379 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4380 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4381 
4382 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
4383 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4384 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4385 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4386 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4387 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4388 
4389 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
4390 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4391 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4392 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4393 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4394 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4395 
4396 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
4397 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4398 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4399 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4400 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4401 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4402 
4403 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
4404 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4405 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4406 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4407 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4408 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4409 
4410 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
4411 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4412 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
4413 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4414 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4415 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4416 
4417 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
4418 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4419 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4420 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4421 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4422 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4423 
4424 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
4425 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4426 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4427 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4428 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4429 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4430 
4431 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
4432 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4433 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4434 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4435 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4436 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4437 
4438 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
4439 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4440 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4441 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4442 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4443 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4444 
4445 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4446 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4447 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4448 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4449 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4450 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4451 
4452 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
4453 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4454 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4455 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4456 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4457 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4458 
4459 /* Bit 0 : Write '1' to Disable interrupt for READY event */
4460 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4461 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4462 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4463 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4464 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4465 
4466 /* Register: NFCT_ERRORSTATUS */
4467 /* Description: NFC Error Status register */
4468 
4469 /* Bit 3 : Field level is too low at min load resistance */
4470 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
4471 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
4472 
4473 /* Bit 2 : Field level is too high at max load resistance */
4474 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
4475 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
4476 
4477 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
4478 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
4479 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
4480 
4481 /* Register: NFCT_FRAMESTATUS_RX */
4482 /* Description: Result of last incoming frames */
4483 
4484 /* Bit 3 : Overrun detected */
4485 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
4486 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
4487 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
4488 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
4489 
4490 /* Bit 2 : Parity status of received frame */
4491 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4492 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
4493 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
4494 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
4495 
4496 /* Bit 0 : No valid End of Frame detected */
4497 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
4498 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
4499 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
4500 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
4501 
4502 /* Register: NFCT_CURRENTLOADCTRL */
4503 /* Description: Current value driven to the NFC Load Control */
4504 
4505 /* Bits 5..0 : Current value driven to the NFC Load Control */
4506 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
4507 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
4508 
4509 /* Register: NFCT_FIELDPRESENT */
4510 /* Description: Indicates the presence or not of a valid field */
4511 
4512 /* Bit 1 : Indicates if the low level has locked to the field */
4513 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
4514 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
4515 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
4516 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
4517 
4518 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
4519 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
4520 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
4521 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
4522 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
4523 
4524 /* Register: NFCT_FRAMEDELAYMIN */
4525 /* Description: Minimum frame delay */
4526 
4527 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
4528 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
4529 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
4530 
4531 /* Register: NFCT_FRAMEDELAYMAX */
4532 /* Description: Maximum frame delay */
4533 
4534 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
4535 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
4536 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
4537 
4538 /* Register: NFCT_FRAMEDELAYMODE */
4539 /* Description: Configuration register for the Frame Delay Timer */
4540 
4541 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
4542 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
4543 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
4544 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
4545 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
4546 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
4547 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
4548 
4549 /* Register: NFCT_PACKETPTR */
4550 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4551 
4552 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
4553 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4554 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
4555 
4556 /* Register: NFCT_MAXLEN */
4557 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
4558 
4559 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
4560 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
4561 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
4562 
4563 /* Register: NFCT_TXD_FRAMECONFIG */
4564 /* Description: Configuration of outgoing frames */
4565 
4566 /* Bit 4 : CRC mode for outgoing frames */
4567 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
4568 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
4569 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
4570 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
4571 
4572 /* Bit 2 : Adding SoF or not in TX frames */
4573 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4574 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4575 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
4576 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
4577 
4578 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
4579 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
4580 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
4581 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
4582 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
4583 
4584 /* Bit 0 : Adding parity or not in the frame */
4585 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4586 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4587 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
4588 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
4589 
4590 /* Register: NFCT_TXD_AMOUNT */
4591 /* Description: Size of outgoing frame */
4592 
4593 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
4594 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
4595 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
4596 
4597 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
4598 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
4599 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
4600 
4601 /* Register: NFCT_RXD_FRAMECONFIG */
4602 /* Description: Configuration of incoming frames */
4603 
4604 /* Bit 4 : CRC mode for incoming frames */
4605 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
4606 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
4607 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
4608 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
4609 
4610 /* Bit 2 : SoF expected or not in RX frames */
4611 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4612 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4613 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
4614 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
4615 
4616 /* Bit 0 : Parity expected or not in RX frame */
4617 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4618 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4619 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
4620 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
4621 
4622 /* Register: NFCT_RXD_AMOUNT */
4623 /* Description: Size of last incoming frame */
4624 
4625 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
4626 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
4627 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
4628 
4629 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
4630 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
4631 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
4632 
4633 /* Register: NFCT_NFCID1_LAST */
4634 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
4635 
4636 /* Bits 31..24 : NFCID1 byte W */
4637 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
4638 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
4639 
4640 /* Bits 23..16 : NFCID1 byte X */
4641 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
4642 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
4643 
4644 /* Bits 15..8 : NFCID1 byte Y */
4645 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
4646 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
4647 
4648 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
4649 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
4650 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
4651 
4652 /* Register: NFCT_NFCID1_2ND_LAST */
4653 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
4654 
4655 /* Bits 23..16 : NFCID1 byte T */
4656 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
4657 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
4658 
4659 /* Bits 15..8 : NFCID1 byte U */
4660 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
4661 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
4662 
4663 /* Bits 7..0 : NFCID1 byte V */
4664 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
4665 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
4666 
4667 /* Register: NFCT_NFCID1_3RD_LAST */
4668 /* Description: Third last NFCID1 part (10 bytes ID) */
4669 
4670 /* Bits 23..16 : NFCID1 byte Q */
4671 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
4672 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
4673 
4674 /* Bits 15..8 : NFCID1 byte R */
4675 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
4676 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
4677 
4678 /* Bits 7..0 : NFCID1 byte S */
4679 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
4680 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
4681 
4682 /* Register: NFCT_SENSRES */
4683 /* Description: NFC-A SENS_RES auto-response settings */
4684 
4685 /* Bits 15..12 : Reserved for future use. Shall be 0. */
4686 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
4687 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
4688 
4689 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4690 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
4691 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
4692 
4693 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
4694 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
4695 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
4696 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
4697 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
4698 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4699 
4700 /* Bit 5 : Reserved for future use. Shall be 0. */
4701 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
4702 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
4703 
4704 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4705 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
4706 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
4707 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
4708 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
4709 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4710 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
4711 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
4712 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
4713 
4714 /* Register: NFCT_SELRES */
4715 /* Description: NFC-A SEL_RES auto-response settings */
4716 
4717 /* Bit 7 : Reserved for future use. Shall be 0. */
4718 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
4719 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
4720 
4721 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4722 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
4723 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
4724 
4725 /* Bits 4..3 : Reserved for future use. Shall be 0. */
4726 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
4727 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
4728 
4729 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
4730 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4731 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
4732 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
4733 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
4734 
4735 /* Bits 1..0 : Reserved for future use. Shall be 0. */
4736 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
4737 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
4738 
4739 
4740 /* Peripheral: NVMC */
4741 /* Description: Non Volatile Memory Controller */
4742 
4743 /* Register: NVMC_READY */
4744 /* Description: Ready flag */
4745 
4746 /* Bit 0 : NVMC is ready or busy */
4747 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
4748 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
4749 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4750 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4751 
4752 /* Register: NVMC_CONFIG */
4753 /* Description: Configuration register */
4754 
4755 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
4756 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
4757 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
4758 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
4759 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
4760 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4761 
4762 /* Register: NVMC_ERASEPAGE */
4763 /* Description: Register for erasing a page in Code area */
4764 
4765 /* Bits 31..0 : Register for starting erase of a page in Code area */
4766 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
4767 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
4768 
4769 /* Register: NVMC_ERASEPCR1 */
4770 /* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4771 
4772 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4773 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
4774 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
4775 
4776 /* Register: NVMC_ERASEALL */
4777 /* Description: Register for erasing all non-volatile user memory */
4778 
4779 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
4780 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
4781 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
4782 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
4783 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
4784 
4785 /* Register: NVMC_ERASEPCR0 */
4786 /* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4787 
4788 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
4789 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
4790 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
4791 
4792 /* Register: NVMC_ERASEUICR */
4793 /* Description: Register for erasing User Information Configuration Registers */
4794 
4795 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
4796 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
4797 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
4798 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
4799 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
4800 
4801 /* Register: NVMC_ICACHECNF */
4802 /* Description: I-Code cache configuration register. */
4803 
4804 /* Bit 8 : Cache profiling enable */
4805 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
4806 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
4807 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4808 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4809 
4810 /* Bit 0 : Cache enable */
4811 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
4812 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
4813 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
4814 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
4815 
4816 /* Register: NVMC_IHIT */
4817 /* Description: I-Code cache hit counter. */
4818 
4819 /* Bits 31..0 : Number of cache hits */
4820 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
4821 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
4822 
4823 /* Register: NVMC_IMISS */
4824 /* Description: I-Code cache miss counter. */
4825 
4826 /* Bits 31..0 : Number of cache misses */
4827 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
4828 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
4829 
4830 
4831 /* Peripheral: GPIO */
4832 /* Description: GPIO Port 1 */
4833 
4834 /* Register: GPIO_OUT */
4835 /* Description: Write GPIO port */
4836 
4837 /* Bit 31 : Pin 31 */
4838 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4839 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4840 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
4841 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4842 
4843 /* Bit 30 : Pin 30 */
4844 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4845 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4846 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
4847 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4848 
4849 /* Bit 29 : Pin 29 */
4850 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4851 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4852 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
4853 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4854 
4855 /* Bit 28 : Pin 28 */
4856 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4857 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4858 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
4859 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4860 
4861 /* Bit 27 : Pin 27 */
4862 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4863 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4864 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
4865 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4866 
4867 /* Bit 26 : Pin 26 */
4868 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4869 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4870 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
4871 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
4872 
4873 /* Bit 25 : Pin 25 */
4874 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4875 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4876 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
4877 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
4878 
4879 /* Bit 24 : Pin 24 */
4880 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4881 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4882 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
4883 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
4884 
4885 /* Bit 23 : Pin 23 */
4886 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4887 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4888 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
4889 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
4890 
4891 /* Bit 22 : Pin 22 */
4892 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4893 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4894 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
4895 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
4896 
4897 /* Bit 21 : Pin 21 */
4898 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4899 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4900 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
4901 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
4902 
4903 /* Bit 20 : Pin 20 */
4904 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4905 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4906 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
4907 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
4908 
4909 /* Bit 19 : Pin 19 */
4910 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4911 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4912 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
4913 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
4914 
4915 /* Bit 18 : Pin 18 */
4916 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4917 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4918 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
4919 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
4920 
4921 /* Bit 17 : Pin 17 */
4922 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4923 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4924 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
4925 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
4926 
4927 /* Bit 16 : Pin 16 */
4928 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4929 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4930 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
4931 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
4932 
4933 /* Bit 15 : Pin 15 */
4934 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4935 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4936 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
4937 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
4938 
4939 /* Bit 14 : Pin 14 */
4940 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4941 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4942 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
4943 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
4944 
4945 /* Bit 13 : Pin 13 */
4946 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4947 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4948 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
4949 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
4950 
4951 /* Bit 12 : Pin 12 */
4952 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4953 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4954 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
4955 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
4956 
4957 /* Bit 11 : Pin 11 */
4958 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4959 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4960 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
4961 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
4962 
4963 /* Bit 10 : Pin 10 */
4964 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4965 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4966 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
4967 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
4968 
4969 /* Bit 9 : Pin 9 */
4970 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4971 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4972 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
4973 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
4974 
4975 /* Bit 8 : Pin 8 */
4976 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4977 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4978 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
4979 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
4980 
4981 /* Bit 7 : Pin 7 */
4982 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4983 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4984 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
4985 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
4986 
4987 /* Bit 6 : Pin 6 */
4988 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4989 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4990 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
4991 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
4992 
4993 /* Bit 5 : Pin 5 */
4994 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4995 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4996 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
4997 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
4998 
4999 /* Bit 4 : Pin 4 */
5000 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5001 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5002 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
5003 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5004 
5005 /* Bit 3 : Pin 3 */
5006 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5007 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5008 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
5009 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5010 
5011 /* Bit 2 : Pin 2 */
5012 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5013 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5014 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
5015 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5016 
5017 /* Bit 1 : Pin 1 */
5018 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5019 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5020 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
5021 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5022 
5023 /* Bit 0 : Pin 0 */
5024 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5025 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5026 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
5027 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5028 
5029 /* Register: GPIO_OUTSET */
5030 /* Description: Set individual bits in GPIO port */
5031 
5032 /* Bit 31 : Pin 31 */
5033 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5034 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5035 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5036 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5037 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5038 
5039 /* Bit 30 : Pin 30 */
5040 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5041 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5042 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5043 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5044 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5045 
5046 /* Bit 29 : Pin 29 */
5047 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5048 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5049 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5050 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5051 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5052 
5053 /* Bit 28 : Pin 28 */
5054 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5055 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5056 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5057 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5058 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5059 
5060 /* Bit 27 : Pin 27 */
5061 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5062 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5063 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5064 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5065 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5066 
5067 /* Bit 26 : Pin 26 */
5068 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5069 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5070 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5071 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5072 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5073 
5074 /* Bit 25 : Pin 25 */
5075 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5076 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5077 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5078 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5079 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5080 
5081 /* Bit 24 : Pin 24 */
5082 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5083 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5084 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5085 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5086 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5087 
5088 /* Bit 23 : Pin 23 */
5089 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5090 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5091 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5092 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5093 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5094 
5095 /* Bit 22 : Pin 22 */
5096 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5097 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5098 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5099 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5100 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5101 
5102 /* Bit 21 : Pin 21 */
5103 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5104 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5105 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5106 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5107 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5108 
5109 /* Bit 20 : Pin 20 */
5110 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5111 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5112 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5113 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5114 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5115 
5116 /* Bit 19 : Pin 19 */
5117 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5118 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5119 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5120 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5121 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5122 
5123 /* Bit 18 : Pin 18 */
5124 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5125 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5126 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5127 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5128 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5129 
5130 /* Bit 17 : Pin 17 */
5131 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5132 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5133 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5134 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5135 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5136 
5137 /* Bit 16 : Pin 16 */
5138 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5139 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5140 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5141 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5142 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5143 
5144 /* Bit 15 : Pin 15 */
5145 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5146 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5147 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5148 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5149 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5150 
5151 /* Bit 14 : Pin 14 */
5152 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5153 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5154 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5155 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5156 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5157 
5158 /* Bit 13 : Pin 13 */
5159 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5160 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5161 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5162 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5163 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5164 
5165 /* Bit 12 : Pin 12 */
5166 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5167 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5168 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5169 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5170 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5171 
5172 /* Bit 11 : Pin 11 */
5173 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5174 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5175 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5176 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5177 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5178 
5179 /* Bit 10 : Pin 10 */
5180 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5181 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5182 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5183 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5184 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5185 
5186 /* Bit 9 : Pin 9 */
5187 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5188 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5189 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5190 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5191 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5192 
5193 /* Bit 8 : Pin 8 */
5194 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5195 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5196 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5197 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5198 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5199 
5200 /* Bit 7 : Pin 7 */
5201 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5202 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5203 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5204 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5205 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5206 
5207 /* Bit 6 : Pin 6 */
5208 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5209 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5210 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5211 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5212 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5213 
5214 /* Bit 5 : Pin 5 */
5215 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5216 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5217 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5218 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5219 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5220 
5221 /* Bit 4 : Pin 4 */
5222 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5223 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5224 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5225 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5226 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5227 
5228 /* Bit 3 : Pin 3 */
5229 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5230 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5231 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5232 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5233 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5234 
5235 /* Bit 2 : Pin 2 */
5236 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5237 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5238 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5239 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5240 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5241 
5242 /* Bit 1 : Pin 1 */
5243 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5244 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5245 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5246 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5247 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5248 
5249 /* Bit 0 : Pin 0 */
5250 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5251 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5252 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5253 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5254 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5255 
5256 /* Register: GPIO_OUTCLR */
5257 /* Description: Clear individual bits in GPIO port */
5258 
5259 /* Bit 31 : Pin 31 */
5260 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5261 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5262 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5263 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5264 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5265 
5266 /* Bit 30 : Pin 30 */
5267 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5268 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5269 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5270 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5271 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5272 
5273 /* Bit 29 : Pin 29 */
5274 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5275 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5276 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5277 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5278 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5279 
5280 /* Bit 28 : Pin 28 */
5281 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5282 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5283 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5284 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5285 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5286 
5287 /* Bit 27 : Pin 27 */
5288 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5289 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5290 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5291 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5292 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5293 
5294 /* Bit 26 : Pin 26 */
5295 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5296 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5297 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5298 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5299 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5300 
5301 /* Bit 25 : Pin 25 */
5302 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5303 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5304 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5305 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5306 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5307 
5308 /* Bit 24 : Pin 24 */
5309 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5310 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5311 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5312 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5313 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5314 
5315 /* Bit 23 : Pin 23 */
5316 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5317 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5318 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5319 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5320 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5321 
5322 /* Bit 22 : Pin 22 */
5323 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5324 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5325 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5326 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5327 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5328 
5329 /* Bit 21 : Pin 21 */
5330 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5331 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5332 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5333 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5334 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5335 
5336 /* Bit 20 : Pin 20 */
5337 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5338 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5339 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5340 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5341 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5342 
5343 /* Bit 19 : Pin 19 */
5344 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5345 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5346 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5347 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5348 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5349 
5350 /* Bit 18 : Pin 18 */
5351 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5352 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5353 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5354 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5355 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5356 
5357 /* Bit 17 : Pin 17 */
5358 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5359 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5360 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5361 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5362 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5363 
5364 /* Bit 16 : Pin 16 */
5365 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5366 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5367 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5368 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5369 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5370 
5371 /* Bit 15 : Pin 15 */
5372 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5373 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5374 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5375 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5376 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5377 
5378 /* Bit 14 : Pin 14 */
5379 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5380 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5381 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5382 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5383 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5384 
5385 /* Bit 13 : Pin 13 */
5386 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5387 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5388 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5389 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5390 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5391 
5392 /* Bit 12 : Pin 12 */
5393 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5394 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5395 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5396 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5397 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5398 
5399 /* Bit 11 : Pin 11 */
5400 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5401 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5402 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5403 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5404 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5405 
5406 /* Bit 10 : Pin 10 */
5407 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5408 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5409 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5410 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5411 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5412 
5413 /* Bit 9 : Pin 9 */
5414 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5415 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5416 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5417 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5418 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5419 
5420 /* Bit 8 : Pin 8 */
5421 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5422 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5423 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5424 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5425 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5426 
5427 /* Bit 7 : Pin 7 */
5428 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5429 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5430 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5431 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5432 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5433 
5434 /* Bit 6 : Pin 6 */
5435 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5436 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5437 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5438 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5439 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5440 
5441 /* Bit 5 : Pin 5 */
5442 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5443 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5444 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5445 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5446 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5447 
5448 /* Bit 4 : Pin 4 */
5449 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5450 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5451 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5452 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5453 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5454 
5455 /* Bit 3 : Pin 3 */
5456 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5457 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5458 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5459 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5460 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5461 
5462 /* Bit 2 : Pin 2 */
5463 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5464 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5465 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5466 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5467 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5468 
5469 /* Bit 1 : Pin 1 */
5470 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5471 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5472 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5473 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5474 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5475 
5476 /* Bit 0 : Pin 0 */
5477 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5478 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5479 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5480 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5481 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5482 
5483 /* Register: GPIO_IN */
5484 /* Description: Read GPIO port */
5485 
5486 /* Bit 31 : Pin 31 */
5487 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5488 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5489 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
5490 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5491 
5492 /* Bit 30 : Pin 30 */
5493 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5494 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5495 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
5496 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5497 
5498 /* Bit 29 : Pin 29 */
5499 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5500 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5501 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
5502 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5503 
5504 /* Bit 28 : Pin 28 */
5505 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5506 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5507 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
5508 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5509 
5510 /* Bit 27 : Pin 27 */
5511 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5512 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5513 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
5514 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5515 
5516 /* Bit 26 : Pin 26 */
5517 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5518 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5519 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
5520 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5521 
5522 /* Bit 25 : Pin 25 */
5523 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5524 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5525 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
5526 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5527 
5528 /* Bit 24 : Pin 24 */
5529 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5530 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5531 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
5532 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5533 
5534 /* Bit 23 : Pin 23 */
5535 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5536 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5537 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
5538 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5539 
5540 /* Bit 22 : Pin 22 */
5541 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5542 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5543 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
5544 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5545 
5546 /* Bit 21 : Pin 21 */
5547 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5548 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5549 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
5550 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5551 
5552 /* Bit 20 : Pin 20 */
5553 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5554 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5555 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
5556 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5557 
5558 /* Bit 19 : Pin 19 */
5559 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5560 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5561 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
5562 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5563 
5564 /* Bit 18 : Pin 18 */
5565 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5566 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5567 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
5568 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5569 
5570 /* Bit 17 : Pin 17 */
5571 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5572 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5573 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
5574 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5575 
5576 /* Bit 16 : Pin 16 */
5577 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5578 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5579 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
5580 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5581 
5582 /* Bit 15 : Pin 15 */
5583 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5584 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5585 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
5586 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5587 
5588 /* Bit 14 : Pin 14 */
5589 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5590 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5591 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
5592 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5593 
5594 /* Bit 13 : Pin 13 */
5595 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5596 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5597 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
5598 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5599 
5600 /* Bit 12 : Pin 12 */
5601 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5602 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5603 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
5604 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5605 
5606 /* Bit 11 : Pin 11 */
5607 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5608 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5609 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
5610 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5611 
5612 /* Bit 10 : Pin 10 */
5613 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5614 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5615 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
5616 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5617 
5618 /* Bit 9 : Pin 9 */
5619 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5620 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5621 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
5622 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5623 
5624 /* Bit 8 : Pin 8 */
5625 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5626 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5627 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
5628 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5629 
5630 /* Bit 7 : Pin 7 */
5631 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5632 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5633 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
5634 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5635 
5636 /* Bit 6 : Pin 6 */
5637 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5638 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5639 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
5640 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5641 
5642 /* Bit 5 : Pin 5 */
5643 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5644 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5645 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
5646 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5647 
5648 /* Bit 4 : Pin 4 */
5649 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5650 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5651 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
5652 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5653 
5654 /* Bit 3 : Pin 3 */
5655 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5656 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5657 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
5658 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5659 
5660 /* Bit 2 : Pin 2 */
5661 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5662 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5663 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
5664 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5665 
5666 /* Bit 1 : Pin 1 */
5667 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5668 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5669 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
5670 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5671 
5672 /* Bit 0 : Pin 0 */
5673 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5674 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5675 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
5676 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
5677 
5678 /* Register: GPIO_DIR */
5679 /* Description: Direction of GPIO pins */
5680 
5681 /* Bit 31 : Pin 31 */
5682 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5683 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5684 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
5685 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
5686 
5687 /* Bit 30 : Pin 30 */
5688 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5689 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5690 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
5691 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5692 
5693 /* Bit 29 : Pin 29 */
5694 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5695 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5696 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
5697 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5698 
5699 /* Bit 28 : Pin 28 */
5700 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5701 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5702 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
5703 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5704 
5705 /* Bit 27 : Pin 27 */
5706 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5707 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5708 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
5709 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5710 
5711 /* Bit 26 : Pin 26 */
5712 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5713 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5714 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
5715 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5716 
5717 /* Bit 25 : Pin 25 */
5718 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5719 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5720 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
5721 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5722 
5723 /* Bit 24 : Pin 24 */
5724 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5725 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5726 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
5727 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5728 
5729 /* Bit 23 : Pin 23 */
5730 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5731 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5732 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
5733 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5734 
5735 /* Bit 22 : Pin 22 */
5736 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5737 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5738 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
5739 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5740 
5741 /* Bit 21 : Pin 21 */
5742 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5743 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5744 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
5745 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5746 
5747 /* Bit 20 : Pin 20 */
5748 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5749 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5750 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
5751 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5752 
5753 /* Bit 19 : Pin 19 */
5754 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5755 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5756 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
5757 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
5758 
5759 /* Bit 18 : Pin 18 */
5760 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5761 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5762 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
5763 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
5764 
5765 /* Bit 17 : Pin 17 */
5766 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5767 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5768 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
5769 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
5770 
5771 /* Bit 16 : Pin 16 */
5772 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5773 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5774 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
5775 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
5776 
5777 /* Bit 15 : Pin 15 */
5778 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5779 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5780 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
5781 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
5782 
5783 /* Bit 14 : Pin 14 */
5784 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5785 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5786 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
5787 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
5788 
5789 /* Bit 13 : Pin 13 */
5790 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5791 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5792 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
5793 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
5794 
5795 /* Bit 12 : Pin 12 */
5796 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5797 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5798 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
5799 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
5800 
5801 /* Bit 11 : Pin 11 */
5802 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5803 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5804 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
5805 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
5806 
5807 /* Bit 10 : Pin 10 */
5808 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5809 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5810 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
5811 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
5812 
5813 /* Bit 9 : Pin 9 */
5814 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5815 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5816 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
5817 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
5818 
5819 /* Bit 8 : Pin 8 */
5820 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5821 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5822 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
5823 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
5824 
5825 /* Bit 7 : Pin 7 */
5826 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5827 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5828 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
5829 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
5830 
5831 /* Bit 6 : Pin 6 */
5832 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5833 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5834 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
5835 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
5836 
5837 /* Bit 5 : Pin 5 */
5838 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5839 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5840 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
5841 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
5842 
5843 /* Bit 4 : Pin 4 */
5844 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5845 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5846 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
5847 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
5848 
5849 /* Bit 3 : Pin 3 */
5850 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5851 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5852 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
5853 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
5854 
5855 /* Bit 2 : Pin 2 */
5856 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5857 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5858 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
5859 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
5860 
5861 /* Bit 1 : Pin 1 */
5862 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5863 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5864 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
5865 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
5866 
5867 /* Bit 0 : Pin 0 */
5868 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5869 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5870 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
5871 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
5872 
5873 /* Register: GPIO_DIRSET */
5874 /* Description: DIR set register */
5875 
5876 /* Bit 31 : Set as output pin 31 */
5877 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5878 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5879 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
5880 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5881 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5882 
5883 /* Bit 30 : Set as output pin 30 */
5884 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5885 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5886 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
5887 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5888 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5889 
5890 /* Bit 29 : Set as output pin 29 */
5891 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5892 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5893 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
5894 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5895 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5896 
5897 /* Bit 28 : Set as output pin 28 */
5898 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5899 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5900 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
5901 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5902 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5903 
5904 /* Bit 27 : Set as output pin 27 */
5905 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5906 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5907 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
5908 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
5909 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5910 
5911 /* Bit 26 : Set as output pin 26 */
5912 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5913 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5914 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
5915 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
5916 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5917 
5918 /* Bit 25 : Set as output pin 25 */
5919 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5920 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5921 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
5922 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
5923 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5924 
5925 /* Bit 24 : Set as output pin 24 */
5926 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5927 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5928 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
5929 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
5930 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5931 
5932 /* Bit 23 : Set as output pin 23 */
5933 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5934 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5935 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
5936 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
5937 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5938 
5939 /* Bit 22 : Set as output pin 22 */
5940 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5941 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5942 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
5943 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
5944 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5945 
5946 /* Bit 21 : Set as output pin 21 */
5947 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5948 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5949 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
5950 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
5951 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5952 
5953 /* Bit 20 : Set as output pin 20 */
5954 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5955 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5956 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
5957 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
5958 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5959 
5960 /* Bit 19 : Set as output pin 19 */
5961 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5962 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5963 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
5964 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
5965 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5966 
5967 /* Bit 18 : Set as output pin 18 */
5968 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5969 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5970 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
5971 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
5972 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5973 
5974 /* Bit 17 : Set as output pin 17 */
5975 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5976 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5977 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
5978 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
5979 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5980 
5981 /* Bit 16 : Set as output pin 16 */
5982 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5983 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5984 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
5985 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
5986 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5987 
5988 /* Bit 15 : Set as output pin 15 */
5989 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5990 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5991 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
5992 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
5993 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5994 
5995 /* Bit 14 : Set as output pin 14 */
5996 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5997 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5998 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
5999 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6000 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6001 
6002 /* Bit 13 : Set as output pin 13 */
6003 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6004 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6005 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6006 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6007 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6008 
6009 /* Bit 12 : Set as output pin 12 */
6010 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6011 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6012 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6013 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6014 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6015 
6016 /* Bit 11 : Set as output pin 11 */
6017 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6018 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6019 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6020 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6021 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6022 
6023 /* Bit 10 : Set as output pin 10 */
6024 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6025 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6026 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6027 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6028 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6029 
6030 /* Bit 9 : Set as output pin 9 */
6031 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6032 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6033 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6034 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6035 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6036 
6037 /* Bit 8 : Set as output pin 8 */
6038 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6039 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6040 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6041 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6042 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6043 
6044 /* Bit 7 : Set as output pin 7 */
6045 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6046 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6047 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6048 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6049 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6050 
6051 /* Bit 6 : Set as output pin 6 */
6052 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6053 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6054 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6055 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6056 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6057 
6058 /* Bit 5 : Set as output pin 5 */
6059 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6060 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6061 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6062 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6063 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6064 
6065 /* Bit 4 : Set as output pin 4 */
6066 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6067 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6068 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6069 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6070 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6071 
6072 /* Bit 3 : Set as output pin 3 */
6073 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6074 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6075 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6076 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6077 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6078 
6079 /* Bit 2 : Set as output pin 2 */
6080 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6081 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6082 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6083 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6084 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6085 
6086 /* Bit 1 : Set as output pin 1 */
6087 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6088 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6089 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6090 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6091 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6092 
6093 /* Bit 0 : Set as output pin 0 */
6094 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6095 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6096 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6097 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6098 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6099 
6100 /* Register: GPIO_DIRCLR */
6101 /* Description: DIR clear register */
6102 
6103 /* Bit 31 : Set as input pin 31 */
6104 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6105 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6106 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6107 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6108 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6109 
6110 /* Bit 30 : Set as input pin 30 */
6111 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6112 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6113 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6114 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6115 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6116 
6117 /* Bit 29 : Set as input pin 29 */
6118 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6119 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6120 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6121 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6122 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6123 
6124 /* Bit 28 : Set as input pin 28 */
6125 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6126 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6127 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6128 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6129 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6130 
6131 /* Bit 27 : Set as input pin 27 */
6132 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6133 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6134 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6135 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6136 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6137 
6138 /* Bit 26 : Set as input pin 26 */
6139 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6140 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6141 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6142 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6143 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6144 
6145 /* Bit 25 : Set as input pin 25 */
6146 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6147 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6148 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6149 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6150 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6151 
6152 /* Bit 24 : Set as input pin 24 */
6153 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6154 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6155 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6156 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6157 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6158 
6159 /* Bit 23 : Set as input pin 23 */
6160 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6161 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6162 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6163 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6164 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6165 
6166 /* Bit 22 : Set as input pin 22 */
6167 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6168 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6169 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6170 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6171 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6172 
6173 /* Bit 21 : Set as input pin 21 */
6174 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6175 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6176 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6177 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6178 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6179 
6180 /* Bit 20 : Set as input pin 20 */
6181 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6182 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6183 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6184 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6185 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6186 
6187 /* Bit 19 : Set as input pin 19 */
6188 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6189 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6190 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6191 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6192 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6193 
6194 /* Bit 18 : Set as input pin 18 */
6195 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6196 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6197 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6198 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6199 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6200 
6201 /* Bit 17 : Set as input pin 17 */
6202 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6203 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6204 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6205 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6206 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6207 
6208 /* Bit 16 : Set as input pin 16 */
6209 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6210 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6211 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6212 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6213 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6214 
6215 /* Bit 15 : Set as input pin 15 */
6216 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6217 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6218 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6219 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6220 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6221 
6222 /* Bit 14 : Set as input pin 14 */
6223 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6224 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6225 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6226 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6227 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6228 
6229 /* Bit 13 : Set as input pin 13 */
6230 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6231 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6232 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6233 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6234 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6235 
6236 /* Bit 12 : Set as input pin 12 */
6237 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6238 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6239 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6240 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6241 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6242 
6243 /* Bit 11 : Set as input pin 11 */
6244 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6245 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6246 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6247 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6248 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6249 
6250 /* Bit 10 : Set as input pin 10 */
6251 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6252 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6253 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6254 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6255 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6256 
6257 /* Bit 9 : Set as input pin 9 */
6258 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6259 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6260 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6261 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6262 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6263 
6264 /* Bit 8 : Set as input pin 8 */
6265 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6266 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6267 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6268 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6269 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6270 
6271 /* Bit 7 : Set as input pin 7 */
6272 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6273 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6274 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6275 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6276 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6277 
6278 /* Bit 6 : Set as input pin 6 */
6279 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6280 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6281 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6282 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6283 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6284 
6285 /* Bit 5 : Set as input pin 5 */
6286 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6287 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6288 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6289 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6290 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6291 
6292 /* Bit 4 : Set as input pin 4 */
6293 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6294 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6295 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6296 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6297 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6298 
6299 /* Bit 3 : Set as input pin 3 */
6300 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6301 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6302 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6303 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6304 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6305 
6306 /* Bit 2 : Set as input pin 2 */
6307 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6308 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6309 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6310 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6311 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6312 
6313 /* Bit 1 : Set as input pin 1 */
6314 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6315 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6316 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6317 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6318 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6319 
6320 /* Bit 0 : Set as input pin 0 */
6321 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6322 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6323 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6324 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6325 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6326 
6327 /* Register: GPIO_LATCH */
6328 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
6329 
6330 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
6331 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6332 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6333 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
6334 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
6335 
6336 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
6337 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6338 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6339 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
6340 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
6341 
6342 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
6343 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6344 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6345 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
6346 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
6347 
6348 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
6349 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6350 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6351 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
6352 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
6353 
6354 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
6355 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6356 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6357 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
6358 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
6359 
6360 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
6361 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6362 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6363 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
6364 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
6365 
6366 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
6367 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6368 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6369 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
6370 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
6371 
6372 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
6373 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6374 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6375 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
6376 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
6377 
6378 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
6379 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6380 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6381 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
6382 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
6383 
6384 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
6385 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6386 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6387 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
6388 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
6389 
6390 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
6391 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6392 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6393 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
6394 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
6395 
6396 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
6397 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6398 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6399 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
6400 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
6401 
6402 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
6403 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6404 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6405 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
6406 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
6407 
6408 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
6409 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6410 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6411 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
6412 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
6413 
6414 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
6415 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6416 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6417 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
6418 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
6419 
6420 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
6421 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6422 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6423 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
6424 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
6425 
6426 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
6427 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6428 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6429 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
6430 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
6431 
6432 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
6433 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6434 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6435 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
6436 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
6437 
6438 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
6439 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6440 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6441 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
6442 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
6443 
6444 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
6445 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6446 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6447 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
6448 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
6449 
6450 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
6451 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6452 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6453 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
6454 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
6455 
6456 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
6457 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6458 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6459 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
6460 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
6461 
6462 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
6463 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6464 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6465 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
6466 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
6467 
6468 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
6469 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6470 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6471 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
6472 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
6473 
6474 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
6475 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6476 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6477 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
6478 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
6479 
6480 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
6481 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6482 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6483 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
6484 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
6485 
6486 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
6487 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6488 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6489 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
6490 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
6491 
6492 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
6493 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6494 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6495 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
6496 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
6497 
6498 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
6499 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6500 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6501 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
6502 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
6503 
6504 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
6505 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6506 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6507 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
6508 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
6509 
6510 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
6511 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6512 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6513 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
6514 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
6515 
6516 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
6517 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6518 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6519 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
6520 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
6521 
6522 /* Register: GPIO_DETECTMODE */
6523 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
6524 
6525 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
6526 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
6527 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
6528 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
6529 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
6530 
6531 /* Register: GPIO_PIN_CNF */
6532 /* Description: Description collection[0]:  Configuration of GPIO pins */
6533 
6534 /* Bits 17..16 : Pin sensing mechanism */
6535 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
6536 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
6537 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6538 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6539 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
6540 
6541 /* Bits 10..8 : Drive configuration */
6542 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
6543 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
6544 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
6545 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6546 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6547 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6548 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
6549 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
6550 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
6551 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
6552 
6553 /* Bits 3..2 : Pull configuration */
6554 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6555 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
6556 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
6557 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
6558 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
6559 
6560 /* Bit 1 : Connect or disconnect input buffer */
6561 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
6562 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
6563 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
6564 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
6565 
6566 /* Bit 0 : Pin direction. Same physical register as DIR register */
6567 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
6568 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
6569 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
6570 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
6571 
6572 
6573 /* Peripheral: PDM */
6574 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
6575 
6576 /* Register: PDM_INTEN */
6577 /* Description: Enable or disable interrupt */
6578 
6579 /* Bit 2 : Enable or disable interrupt for END event */
6580 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6581 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
6582 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6583 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6584 
6585 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6586 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6587 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6588 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6589 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6590 
6591 /* Bit 0 : Enable or disable interrupt for STARTED event */
6592 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6593 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6594 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6595 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6596 
6597 /* Register: PDM_INTENSET */
6598 /* Description: Enable interrupt */
6599 
6600 /* Bit 2 : Write '1' to Enable interrupt for END event */
6601 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6602 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
6603 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6604 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6605 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6606 
6607 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
6608 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6609 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6610 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6611 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6612 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6613 
6614 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
6615 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6616 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6617 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6618 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6619 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6620 
6621 /* Register: PDM_INTENCLR */
6622 /* Description: Disable interrupt */
6623 
6624 /* Bit 2 : Write '1' to Disable interrupt for END event */
6625 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6626 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6627 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6628 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6629 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6630 
6631 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
6632 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6633 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6634 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6635 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6636 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6637 
6638 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
6639 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6640 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6641 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6642 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6643 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6644 
6645 /* Register: PDM_ENABLE */
6646 /* Description: PDM module enable register */
6647 
6648 /* Bit 0 : Enable or disable PDM module */
6649 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6650 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6651 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6652 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6653 
6654 /* Register: PDM_PDMCLKCTRL */
6655 /* Description: PDM clock generator control */
6656 
6657 /* Bits 31..0 : PDM_CLK frequency */
6658 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
6659 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
6660 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
6661 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
6662 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
6663 
6664 /* Register: PDM_MODE */
6665 /* Description: Defines the routing of the connected PDM microphones' signals */
6666 
6667 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
6668 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
6669 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
6670 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
6671 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
6672 
6673 /* Bit 0 : Mono or stereo operation */
6674 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
6675 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
6676 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
6677 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
6678 
6679 /* Register: PDM_GAINL */
6680 /* Description: Left output gain adjustment */
6681 
6682 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
6683 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
6684 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
6685 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6686 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
6687 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
6688 
6689 /* Register: PDM_GAINR */
6690 /* Description: Right output gain adjustment */
6691 
6692 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
6693 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
6694 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
6695 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6696 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
6697 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
6698 
6699 /* Register: PDM_PSEL_CLK */
6700 /* Description: Pin number configuration for PDM CLK signal */
6701 
6702 /* Bit 31 : Connection */
6703 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6704 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6705 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
6706 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
6707 
6708 /* Bits 4..0 : Pin number */
6709 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
6710 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
6711 
6712 /* Register: PDM_PSEL_DIN */
6713 /* Description: Pin number configuration for PDM DIN signal */
6714 
6715 /* Bit 31 : Connection */
6716 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6717 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6718 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
6719 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
6720 
6721 /* Bits 4..0 : Pin number */
6722 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
6723 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
6724 
6725 /* Register: PDM_SAMPLE_PTR */
6726 /* Description: RAM address pointer to write samples to with EasyDMA */
6727 
6728 /* Bits 31..0 : Address to write PDM samples to over DMA */
6729 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
6730 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
6731 
6732 /* Register: PDM_SAMPLE_MAXCNT */
6733 /* Description: Number of samples to allocate memory for in EasyDMA mode */
6734 
6735 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
6736 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
6737 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
6738 
6739 
6740 /* Peripheral: POWER */
6741 /* Description: Power control */
6742 
6743 /* Register: POWER_INTENSET */
6744 /* Description: Enable interrupt */
6745 
6746 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
6747 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6748 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6749 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6750 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6751 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6752 
6753 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
6754 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6755 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6756 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6757 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6758 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6759 
6760 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6761 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6762 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6763 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6764 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6765 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
6766 
6767 /* Register: POWER_INTENCLR */
6768 /* Description: Disable interrupt */
6769 
6770 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
6771 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6772 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6773 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6774 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6775 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
6776 
6777 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
6778 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6779 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6780 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6781 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6782 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
6783 
6784 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
6785 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6786 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6787 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6788 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6789 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
6790 
6791 /* Register: POWER_RESETREAS */
6792 /* Description: Reset reason */
6793 
6794 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
6795 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
6796 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
6797 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
6798 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
6799 
6800 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
6801 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
6802 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
6803 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
6804 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
6805 
6806 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
6807 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
6808 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
6809 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
6810 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
6811 
6812 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
6813 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
6814 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
6815 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
6816 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
6817 
6818 /* Bit 3 : Reset from CPU lock-up detected */
6819 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
6820 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
6821 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
6822 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
6823 
6824 /* Bit 2 : Reset from soft reset detected */
6825 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
6826 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
6827 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
6828 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
6829 
6830 /* Bit 1 : Reset from watchdog detected */
6831 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
6832 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
6833 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
6834 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
6835 
6836 /* Bit 0 : Reset from pin-reset detected */
6837 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
6838 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
6839 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
6840 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
6841 
6842 /* Register: POWER_RAMSTATUS */
6843 /* Description: Deprecated register -  RAM status register */
6844 
6845 /* Bit 3 : RAM block 3 is on or off/powering up */
6846 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
6847 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
6848 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
6849 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
6850 
6851 /* Bit 2 : RAM block 2 is on or off/powering up */
6852 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
6853 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
6854 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
6855 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
6856 
6857 /* Bit 1 : RAM block 1 is on or off/powering up */
6858 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
6859 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
6860 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
6861 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
6862 
6863 /* Bit 0 : RAM block 0 is on or off/powering up */
6864 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
6865 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
6866 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
6867 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
6868 
6869 /* Register: POWER_SYSTEMOFF */
6870 /* Description: System OFF register */
6871 
6872 /* Bit 0 : Enable System OFF mode */
6873 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
6874 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
6875 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
6876 
6877 /* Register: POWER_POFCON */
6878 /* Description: Power failure comparator configuration */
6879 
6880 /* Bits 4..1 : Power failure comparator threshold setting */
6881 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
6882 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
6883 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
6884 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
6885 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
6886 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
6887 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
6888 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
6889 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
6890 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
6891 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
6892 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
6893 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
6894 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
6895 
6896 /* Bit 0 : Enable or disable power failure comparator */
6897 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
6898 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
6899 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
6900 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
6901 
6902 /* Register: POWER_GPREGRET */
6903 /* Description: General purpose retention register */
6904 
6905 /* Bits 7..0 : General purpose retention register */
6906 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6907 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6908 
6909 /* Register: POWER_GPREGRET2 */
6910 /* Description: General purpose retention register */
6911 
6912 /* Bits 7..0 : General purpose retention register */
6913 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6914 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6915 
6916 /* Register: POWER_RAMON */
6917 /* Description: Deprecated register -  RAM on/off register (this register is retained) */
6918 
6919 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
6920 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
6921 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
6922 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
6923 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
6924 
6925 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
6926 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
6927 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
6928 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
6929 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
6930 
6931 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
6932 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
6933 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
6934 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
6935 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
6936 
6937 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
6938 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
6939 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
6940 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
6941 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
6942 
6943 /* Register: POWER_RAMONB */
6944 /* Description: Deprecated register -  RAM on/off register (this register is retained) */
6945 
6946 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
6947 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
6948 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
6949 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
6950 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
6951 
6952 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
6953 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
6954 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
6955 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
6956 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
6957 
6958 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
6959 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
6960 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
6961 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
6962 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
6963 
6964 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
6965 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
6966 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
6967 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
6968 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
6969 
6970 /* Register: POWER_DCDCEN */
6971 /* Description: DC/DC enable register */
6972 
6973 /* Bit 0 : Enable or disable DC/DC converter */
6974 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
6975 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
6976 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
6977 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
6978 
6979 /* Register: POWER_RAM_POWER */
6980 /* Description: Description cluster[0]:  RAM0 power control register */
6981 
6982 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
6983 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
6984 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
6985 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
6986 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
6987 
6988 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
6989 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
6990 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
6991 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
6992 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
6993 
6994 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
6995 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
6996 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
6997 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
6998 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
6999 
7000 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
7001 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7002 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7003 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
7004 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7005 
7006 /* Register: POWER_RAM_POWERSET */
7007 /* Description: Description cluster[0]:  RAM0 power control set register */
7008 
7009 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7010 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7011 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7012 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7013 
7014 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7015 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7016 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7017 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7018 
7019 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7020 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7021 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7022 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7023 
7024 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
7025 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7026 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7027 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7028 
7029 /* Register: POWER_RAM_POWERCLR */
7030 /* Description: Description cluster[0]:  RAM0 power control clear register */
7031 
7032 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7033 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7034 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7035 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7036 
7037 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7038 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7039 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7040 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7041 
7042 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7043 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7044 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7045 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7046 
7047 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
7048 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7049 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7050 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7051 
7052 
7053 /* Peripheral: PPI */
7054 /* Description: Programmable Peripheral Interconnect */
7055 
7056 /* Register: PPI_CHEN */
7057 /* Description: Channel enable register */
7058 
7059 /* Bit 31 : Enable or disable channel 31 */
7060 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
7061 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
7062 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7063 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7064 
7065 /* Bit 30 : Enable or disable channel 30 */
7066 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
7067 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
7068 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7069 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7070 
7071 /* Bit 29 : Enable or disable channel 29 */
7072 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
7073 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
7074 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7075 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7076 
7077 /* Bit 28 : Enable or disable channel 28 */
7078 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
7079 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
7080 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7081 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7082 
7083 /* Bit 27 : Enable or disable channel 27 */
7084 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
7085 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
7086 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7087 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7088 
7089 /* Bit 26 : Enable or disable channel 26 */
7090 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
7091 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
7092 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7093 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7094 
7095 /* Bit 25 : Enable or disable channel 25 */
7096 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
7097 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
7098 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7099 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7100 
7101 /* Bit 24 : Enable or disable channel 24 */
7102 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
7103 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
7104 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7105 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7106 
7107 /* Bit 23 : Enable or disable channel 23 */
7108 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
7109 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
7110 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7111 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7112 
7113 /* Bit 22 : Enable or disable channel 22 */
7114 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
7115 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
7116 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7117 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7118 
7119 /* Bit 21 : Enable or disable channel 21 */
7120 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
7121 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
7122 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7123 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7124 
7125 /* Bit 20 : Enable or disable channel 20 */
7126 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
7127 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
7128 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7129 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7130 
7131 /* Bit 19 : Enable or disable channel 19 */
7132 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
7133 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
7134 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7135 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7136 
7137 /* Bit 18 : Enable or disable channel 18 */
7138 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
7139 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
7140 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7141 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7142 
7143 /* Bit 17 : Enable or disable channel 17 */
7144 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
7145 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
7146 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7147 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7148 
7149 /* Bit 16 : Enable or disable channel 16 */
7150 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
7151 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
7152 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7153 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7154 
7155 /* Bit 15 : Enable or disable channel 15 */
7156 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
7157 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
7158 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7159 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7160 
7161 /* Bit 14 : Enable or disable channel 14 */
7162 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
7163 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
7164 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7165 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7166 
7167 /* Bit 13 : Enable or disable channel 13 */
7168 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
7169 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
7170 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7171 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7172 
7173 /* Bit 12 : Enable or disable channel 12 */
7174 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
7175 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
7176 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7177 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7178 
7179 /* Bit 11 : Enable or disable channel 11 */
7180 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
7181 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
7182 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7183 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7184 
7185 /* Bit 10 : Enable or disable channel 10 */
7186 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
7187 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
7188 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7189 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7190 
7191 /* Bit 9 : Enable or disable channel 9 */
7192 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
7193 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
7194 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7195 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7196 
7197 /* Bit 8 : Enable or disable channel 8 */
7198 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
7199 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
7200 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
7201 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7202 
7203 /* Bit 7 : Enable or disable channel 7 */
7204 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
7205 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
7206 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
7207 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7208 
7209 /* Bit 6 : Enable or disable channel 6 */
7210 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
7211 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
7212 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
7213 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7214 
7215 /* Bit 5 : Enable or disable channel 5 */
7216 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
7217 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
7218 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
7219 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7220 
7221 /* Bit 4 : Enable or disable channel 4 */
7222 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
7223 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
7224 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
7225 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7226 
7227 /* Bit 3 : Enable or disable channel 3 */
7228 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
7229 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
7230 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
7231 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7232 
7233 /* Bit 2 : Enable or disable channel 2 */
7234 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
7235 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
7236 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
7237 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
7238 
7239 /* Bit 1 : Enable or disable channel 1 */
7240 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
7241 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
7242 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
7243 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
7244 
7245 /* Bit 0 : Enable or disable channel 0 */
7246 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
7247 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
7248 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
7249 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
7250 
7251 /* Register: PPI_CHENSET */
7252 /* Description: Channel enable set register */
7253 
7254 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
7255 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
7256 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
7257 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7258 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7259 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7260 
7261 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
7262 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
7263 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
7264 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7265 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7266 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7267 
7268 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
7269 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
7270 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
7271 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7272 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7273 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7274 
7275 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
7276 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
7277 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
7278 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7279 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7280 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7281 
7282 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
7283 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
7284 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
7285 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7286 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7287 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7288 
7289 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
7290 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
7291 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
7292 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
7293 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
7294 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
7295 
7296 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
7297 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
7298 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
7299 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
7300 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
7301 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
7302 
7303 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
7304 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
7305 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
7306 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
7307 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
7308 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
7309 
7310 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
7311 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
7312 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
7313 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
7314 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
7315 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
7316 
7317 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
7318 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
7319 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
7320 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
7321 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
7322 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
7323 
7324 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
7325 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
7326 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
7327 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
7328 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
7329 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
7330 
7331 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
7332 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
7333 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
7334 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
7335 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
7336 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
7337 
7338 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
7339 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
7340 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
7341 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
7342 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
7343 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
7344 
7345 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
7346 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
7347 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
7348 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
7349 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
7350 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
7351 
7352 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
7353 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
7354 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
7355 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
7356 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
7357 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
7358 
7359 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
7360 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
7361 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
7362 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
7363 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
7364 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
7365 
7366 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
7367 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
7368 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
7369 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
7370 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
7371 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
7372 
7373 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
7374 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
7375 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
7376 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
7377 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
7378 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
7379 
7380 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
7381 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
7382 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
7383 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
7384 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
7385 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
7386 
7387 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
7388 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
7389 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
7390 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
7391 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
7392 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
7393 
7394 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
7395 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
7396 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
7397 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
7398 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
7399 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
7400 
7401 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
7402 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
7403 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
7404 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
7405 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
7406 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
7407 
7408 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
7409 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
7410 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
7411 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
7412 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
7413 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
7414 
7415 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
7416 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
7417 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
7418 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
7419 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
7420 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
7421 
7422 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
7423 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
7424 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
7425 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
7426 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
7427 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
7428 
7429 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
7430 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
7431 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
7432 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
7433 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
7434 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
7435 
7436 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
7437 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
7438 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
7439 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
7440 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
7441 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
7442 
7443 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
7444 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
7445 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
7446 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
7447 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
7448 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
7449 
7450 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
7451 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
7452 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
7453 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
7454 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
7455 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
7456 
7457 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
7458 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
7459 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
7460 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
7461 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
7462 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
7463 
7464 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
7465 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
7466 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
7467 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
7468 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
7469 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
7470 
7471 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
7472 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
7473 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
7474 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
7475 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
7476 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
7477 
7478 /* Register: PPI_CHENCLR */
7479 /* Description: Channel enable clear register */
7480 
7481 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
7482 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
7483 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
7484 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
7485 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
7486 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
7487 
7488 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
7489 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
7490 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
7491 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
7492 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
7493 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
7494 
7495 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
7496 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
7497 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
7498 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
7499 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
7500 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
7501 
7502 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
7503 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
7504 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
7505 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
7506 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
7507 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
7508 
7509 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
7510 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
7511 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
7512 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
7513 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
7514 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
7515 
7516 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
7517 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
7518 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
7519 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
7520 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
7521 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
7522 
7523 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
7524 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
7525 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
7526 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
7527 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
7528 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
7529 
7530 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
7531 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
7532 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
7533 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
7534 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
7535 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
7536 
7537 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
7538 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
7539 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
7540 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
7541 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
7542 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
7543 
7544 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
7545 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
7546 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
7547 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
7548 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
7549 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
7550 
7551 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
7552 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
7553 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
7554 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
7555 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
7556 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
7557 
7558 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
7559 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
7560 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
7561 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
7562 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
7563 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
7564 
7565 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
7566 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
7567 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
7568 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
7569 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
7570 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
7571 
7572 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
7573 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
7574 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
7575 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
7576 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
7577 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
7578 
7579 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
7580 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
7581 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
7582 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
7583 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
7584 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
7585 
7586 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
7587 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
7588 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
7589 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
7590 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
7591 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
7592 
7593 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
7594 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
7595 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
7596 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
7597 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
7598 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
7599 
7600 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
7601 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
7602 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
7603 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
7604 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
7605 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
7606 
7607 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
7608 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
7609 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
7610 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
7611 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
7612 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
7613 
7614 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
7615 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
7616 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
7617 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
7618 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
7619 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
7620 
7621 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
7622 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
7623 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
7624 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
7625 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
7626 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
7627 
7628 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
7629 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
7630 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
7631 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
7632 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
7633 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
7634 
7635 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
7636 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
7637 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
7638 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
7639 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
7640 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
7641 
7642 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
7643 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
7644 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
7645 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
7646 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
7647 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
7648 
7649 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
7650 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
7651 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
7652 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
7653 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
7654 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
7655 
7656 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
7657 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
7658 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
7659 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
7660 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
7661 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
7662 
7663 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
7664 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
7665 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
7666 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
7667 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
7668 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
7669 
7670 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
7671 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
7672 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
7673 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
7674 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
7675 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
7676 
7677 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
7678 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
7679 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
7680 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
7681 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
7682 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
7683 
7684 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
7685 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
7686 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
7687 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
7688 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
7689 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
7690 
7691 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
7692 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
7693 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
7694 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
7695 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
7696 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
7697 
7698 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
7699 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
7700 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
7701 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
7702 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
7703 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
7704 
7705 /* Register: PPI_CH_EEP */
7706 /* Description: Description cluster[0]:  Channel 0 event end-point */
7707 
7708 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
7709 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
7710 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
7711 
7712 /* Register: PPI_CH_TEP */
7713 /* Description: Description cluster[0]:  Channel 0 task end-point */
7714 
7715 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
7716 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
7717 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
7718 
7719 /* Register: PPI_CHG */
7720 /* Description: Description collection[0]:  Channel group 0 */
7721 
7722 /* Bit 31 : Include or exclude channel 31 */
7723 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
7724 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
7725 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
7726 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
7727 
7728 /* Bit 30 : Include or exclude channel 30 */
7729 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
7730 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
7731 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
7732 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
7733 
7734 /* Bit 29 : Include or exclude channel 29 */
7735 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
7736 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
7737 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
7738 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
7739 
7740 /* Bit 28 : Include or exclude channel 28 */
7741 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
7742 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
7743 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
7744 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
7745 
7746 /* Bit 27 : Include or exclude channel 27 */
7747 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
7748 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
7749 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
7750 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
7751 
7752 /* Bit 26 : Include or exclude channel 26 */
7753 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
7754 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
7755 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
7756 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
7757 
7758 /* Bit 25 : Include or exclude channel 25 */
7759 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
7760 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
7761 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
7762 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
7763 
7764 /* Bit 24 : Include or exclude channel 24 */
7765 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
7766 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
7767 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
7768 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
7769 
7770 /* Bit 23 : Include or exclude channel 23 */
7771 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
7772 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
7773 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
7774 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
7775 
7776 /* Bit 22 : Include or exclude channel 22 */
7777 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
7778 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
7779 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
7780 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
7781 
7782 /* Bit 21 : Include or exclude channel 21 */
7783 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
7784 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
7785 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
7786 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
7787 
7788 /* Bit 20 : Include or exclude channel 20 */
7789 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
7790 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
7791 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
7792 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
7793 
7794 /* Bit 19 : Include or exclude channel 19 */
7795 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
7796 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
7797 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
7798 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
7799 
7800 /* Bit 18 : Include or exclude channel 18 */
7801 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
7802 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
7803 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
7804 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
7805 
7806 /* Bit 17 : Include or exclude channel 17 */
7807 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
7808 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
7809 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
7810 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
7811 
7812 /* Bit 16 : Include or exclude channel 16 */
7813 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
7814 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
7815 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
7816 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
7817 
7818 /* Bit 15 : Include or exclude channel 15 */
7819 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
7820 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
7821 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
7822 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
7823 
7824 /* Bit 14 : Include or exclude channel 14 */
7825 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
7826 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
7827 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
7828 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
7829 
7830 /* Bit 13 : Include or exclude channel 13 */
7831 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
7832 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
7833 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
7834 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
7835 
7836 /* Bit 12 : Include or exclude channel 12 */
7837 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
7838 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
7839 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
7840 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
7841 
7842 /* Bit 11 : Include or exclude channel 11 */
7843 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
7844 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
7845 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
7846 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
7847 
7848 /* Bit 10 : Include or exclude channel 10 */
7849 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
7850 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
7851 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
7852 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
7853 
7854 /* Bit 9 : Include or exclude channel 9 */
7855 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
7856 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
7857 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
7858 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
7859 
7860 /* Bit 8 : Include or exclude channel 8 */
7861 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
7862 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
7863 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
7864 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
7865 
7866 /* Bit 7 : Include or exclude channel 7 */
7867 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
7868 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
7869 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
7870 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
7871 
7872 /* Bit 6 : Include or exclude channel 6 */
7873 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
7874 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
7875 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
7876 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
7877 
7878 /* Bit 5 : Include or exclude channel 5 */
7879 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
7880 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
7881 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
7882 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
7883 
7884 /* Bit 4 : Include or exclude channel 4 */
7885 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
7886 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
7887 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
7888 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
7889 
7890 /* Bit 3 : Include or exclude channel 3 */
7891 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
7892 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
7893 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
7894 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
7895 
7896 /* Bit 2 : Include or exclude channel 2 */
7897 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
7898 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
7899 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
7900 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
7901 
7902 /* Bit 1 : Include or exclude channel 1 */
7903 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
7904 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
7905 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
7906 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
7907 
7908 /* Bit 0 : Include or exclude channel 0 */
7909 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
7910 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
7911 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
7912 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
7913 
7914 /* Register: PPI_FORK_TEP */
7915 /* Description: Description cluster[0]:  Channel 0 task end-point */
7916 
7917 /* Bits 31..0 : Pointer to task register */
7918 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
7919 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
7920 
7921 
7922 /* Peripheral: PWM */
7923 /* Description: Pulse Width Modulation Unit 0 */
7924 
7925 /* Register: PWM_SHORTS */
7926 /* Description: Shortcut register */
7927 
7928 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
7929 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
7930 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
7931 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
7932 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
7933 
7934 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
7935 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
7936 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
7937 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
7938 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
7939 
7940 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
7941 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
7942 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
7943 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
7944 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
7945 
7946 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
7947 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
7948 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
7949 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
7950 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
7951 
7952 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
7953 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
7954 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
7955 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
7956 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
7957 
7958 /* Register: PWM_INTEN */
7959 /* Description: Enable or disable interrupt */
7960 
7961 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
7962 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
7963 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
7964 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
7965 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
7966 
7967 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
7968 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
7969 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
7970 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
7971 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
7972 
7973 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
7974 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
7975 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
7976 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
7977 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
7978 
7979 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
7980 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
7981 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
7982 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
7983 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
7984 
7985 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
7986 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
7987 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
7988 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
7989 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
7990 
7991 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
7992 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
7993 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
7994 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
7995 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
7996 
7997 /* Bit 1 : Enable or disable interrupt for STOPPED event */
7998 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7999 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8000 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8001 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8002 
8003 /* Register: PWM_INTENSET */
8004 /* Description: Enable interrupt */
8005 
8006 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
8007 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8008 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8009 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8010 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8011 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8012 
8013 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
8014 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8015 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8016 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8017 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8018 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8019 
8020 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
8021 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8022 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8023 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8024 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8025 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8026 
8027 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
8028 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8029 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8030 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8031 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8032 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8033 
8034 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
8035 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8036 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8037 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8038 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8039 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8040 
8041 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
8042 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8043 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8044 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8045 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8046 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8047 
8048 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
8049 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8050 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8051 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8052 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8053 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8054 
8055 /* Register: PWM_INTENCLR */
8056 /* Description: Disable interrupt */
8057 
8058 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
8059 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8060 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8061 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8062 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8063 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8064 
8065 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
8066 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8067 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8068 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8069 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8070 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8071 
8072 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
8073 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8074 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8075 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8076 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8077 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8078 
8079 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
8080 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8081 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8082 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8083 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8084 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8085 
8086 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
8087 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8088 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8089 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8090 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8091 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8092 
8093 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
8094 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8095 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8096 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8097 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8098 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8099 
8100 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
8101 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8102 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8103 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8104 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8105 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8106 
8107 /* Register: PWM_ENABLE */
8108 /* Description: PWM module enable register */
8109 
8110 /* Bit 0 : Enable or disable PWM module */
8111 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8112 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8113 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
8114 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8115 
8116 /* Register: PWM_MODE */
8117 /* Description: Selects operating mode of the wave counter */
8118 
8119 /* Bit 0 : Selects up or up and down as wave counter mode */
8120 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
8121 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
8122 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
8123 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
8124 
8125 /* Register: PWM_COUNTERTOP */
8126 /* Description: Value up to which the pulse generator counter counts */
8127 
8128 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
8129 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
8130 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
8131 
8132 /* Register: PWM_PRESCALER */
8133 /* Description: Configuration for PWM_CLK */
8134 
8135 /* Bits 2..0 : Pre-scaler of PWM_CLK */
8136 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8137 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8138 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
8139 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
8140 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
8141 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
8142 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
8143 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
8144 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
8145 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
8146 
8147 /* Register: PWM_DECODER */
8148 /* Description: Configuration of the decoder */
8149 
8150 /* Bit 8 : Selects source for advancing the active sequence */
8151 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
8152 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
8153 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
8154 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
8155 
8156 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
8157 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
8158 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
8159 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
8160 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
8161 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
8162 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
8163 
8164 /* Register: PWM_LOOP */
8165 /* Description: Amount of playback of a loop */
8166 
8167 /* Bits 15..0 : Amount of playback of pattern cycles */
8168 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
8169 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
8170 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
8171 
8172 /* Register: PWM_SEQ_PTR */
8173 /* Description: Description cluster[0]:  Beginning address in Data RAM of this sequence */
8174 
8175 /* Bits 31..0 : Beginning address in Data RAM of this sequence */
8176 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8177 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8178 
8179 /* Register: PWM_SEQ_CNT */
8180 /* Description: Description cluster[0]:  Amount of values (duty cycles) in this sequence */
8181 
8182 /* Bits 14..0 : Amount of values (duty cycles) in this sequence */
8183 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
8184 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
8185 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
8186 
8187 /* Register: PWM_SEQ_REFRESH */
8188 /* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register */
8189 
8190 /* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
8191 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
8192 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
8193 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
8194 
8195 /* Register: PWM_SEQ_ENDDELAY */
8196 /* Description: Description cluster[0]:  Time added after the sequence */
8197 
8198 /* Bits 23..0 : Time added after the sequence in PWM periods */
8199 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
8200 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
8201 
8202 /* Register: PWM_PSEL_OUT */
8203 /* Description: Description collection[0]:  Output pin select for PWM channel 0 */
8204 
8205 /* Bit 31 : Connection */
8206 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8207 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8208 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
8209 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
8210 
8211 /* Bits 4..0 : Pin number */
8212 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
8213 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
8214 
8215 
8216 /* Peripheral: QDEC */
8217 /* Description: Quadrature Decoder */
8218 
8219 /* Register: QDEC_SHORTS */
8220 /* Description: Shortcut register */
8221 
8222 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
8223 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
8224 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
8225 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
8226 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8227 
8228 /* Bit 5 : Shortcut between DBLRDY event and STOP task */
8229 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
8230 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
8231 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8232 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8233 
8234 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
8235 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
8236 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
8237 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
8238 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
8239 
8240 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */
8241 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
8242 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
8243 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8244 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8245 
8246 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
8247 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
8248 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
8249 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
8250 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
8251 
8252 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
8253 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
8254 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
8255 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8256 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8257 
8258 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
8259 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
8260 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
8261 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
8262 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8263 
8264 /* Register: QDEC_INTENSET */
8265 /* Description: Enable interrupt */
8266 
8267 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
8268 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
8269 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8270 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8271 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8272 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8273 
8274 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
8275 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
8276 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
8277 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8278 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8279 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
8280 
8281 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
8282 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
8283 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
8284 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8285 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8286 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
8287 
8288 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
8289 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
8290 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
8291 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8292 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8293 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
8294 
8295 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
8296 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
8297 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
8298 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8299 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8300 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
8301 
8302 /* Register: QDEC_INTENCLR */
8303 /* Description: Disable interrupt */
8304 
8305 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
8306 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
8307 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8308 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8309 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8310 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8311 
8312 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
8313 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
8314 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
8315 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8316 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8317 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
8318 
8319 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
8320 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
8321 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
8322 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8323 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8324 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
8325 
8326 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
8327 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
8328 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
8329 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8330 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8331 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
8332 
8333 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
8334 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
8335 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
8336 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8337 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8338 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
8339 
8340 /* Register: QDEC_ENABLE */
8341 /* Description: Enable the quadrature decoder */
8342 
8343 /* Bit 0 : Enable or disable the quadrature decoder */
8344 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8345 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8346 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
8347 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8348 
8349 /* Register: QDEC_LEDPOL */
8350 /* Description: LED output pin polarity */
8351 
8352 /* Bit 0 : LED output pin polarity */
8353 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
8354 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
8355 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
8356 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
8357 
8358 /* Register: QDEC_SAMPLEPER */
8359 /* Description: Sample period */
8360 
8361 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
8362 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
8363 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
8364 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
8365 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
8366 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
8367 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
8368 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
8369 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
8370 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
8371 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
8372 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
8373 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
8374 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
8375 
8376 /* Register: QDEC_SAMPLE */
8377 /* Description: Motion sample value */
8378 
8379 /* Bits 31..0 : Last motion sample */
8380 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
8381 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
8382 
8383 /* Register: QDEC_REPORTPER */
8384 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
8385 
8386 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
8387 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
8388 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
8389 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
8390 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
8391 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
8392 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
8393 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
8394 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
8395 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
8396 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
8397 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
8398 
8399 /* Register: QDEC_ACC */
8400 /* Description: Register accumulating the valid transitions */
8401 
8402 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
8403 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
8404 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
8405 
8406 /* Register: QDEC_ACCREAD */
8407 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
8408 
8409 /* Bits 31..0 : Snapshot of the ACC register. */
8410 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
8411 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
8412 
8413 /* Register: QDEC_PSEL_LED */
8414 /* Description: Pin select for LED signal */
8415 
8416 /* Bit 31 : Connection */
8417 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8418 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8419 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
8420 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
8421 
8422 /* Bits 4..0 : Pin number */
8423 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
8424 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
8425 
8426 /* Register: QDEC_PSEL_A */
8427 /* Description: Pin select for A signal */
8428 
8429 /* Bit 31 : Connection */
8430 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8431 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8432 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
8433 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
8434 
8435 /* Bits 4..0 : Pin number */
8436 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
8437 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
8438 
8439 /* Register: QDEC_PSEL_B */
8440 /* Description: Pin select for B signal */
8441 
8442 /* Bit 31 : Connection */
8443 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8444 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8445 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
8446 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
8447 
8448 /* Bits 4..0 : Pin number */
8449 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
8450 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
8451 
8452 /* Register: QDEC_DBFEN */
8453 /* Description: Enable input debounce filters */
8454 
8455 /* Bit 0 : Enable input debounce filters */
8456 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
8457 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
8458 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
8459 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
8460 
8461 /* Register: QDEC_LEDPRE */
8462 /* Description: Time period the LED is switched ON prior to sampling */
8463 
8464 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
8465 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
8466 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
8467 
8468 /* Register: QDEC_ACCDBL */
8469 /* Description: Register accumulating the number of detected double transitions */
8470 
8471 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
8472 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
8473 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
8474 
8475 /* Register: QDEC_ACCDBLREAD */
8476 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
8477 
8478 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
8479 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
8480 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
8481 
8482 
8483 /* Peripheral: RADIO */
8484 /* Description: 2.4 GHz Radio */
8485 
8486 /* Register: RADIO_SHORTS */
8487 /* Description: Shortcut register */
8488 
8489 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
8490 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
8491 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
8492 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
8493 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
8494 
8495 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
8496 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
8497 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
8498 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
8499 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
8500 
8501 /* Bit 5 : Shortcut between END event and START task */
8502 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
8503 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
8504 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
8505 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
8506 
8507 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
8508 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
8509 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
8510 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
8511 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
8512 
8513 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
8514 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
8515 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
8516 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
8517 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
8518 
8519 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
8520 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
8521 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
8522 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
8523 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
8524 
8525 /* Bit 1 : Shortcut between END event and DISABLE task */
8526 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
8527 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
8528 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
8529 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
8530 
8531 /* Bit 0 : Shortcut between READY event and START task */
8532 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
8533 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
8534 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
8535 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
8536 
8537 /* Register: RADIO_INTENSET */
8538 /* Description: Enable interrupt */
8539 
8540 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
8541 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
8542 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
8543 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8544 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8545 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
8546 
8547 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
8548 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
8549 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
8550 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8551 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8552 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
8553 
8554 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
8555 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
8556 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
8557 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8558 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8559 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
8560 
8561 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
8562 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
8563 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
8564 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8565 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8566 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
8567 
8568 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
8569 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
8570 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
8571 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8572 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8573 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
8574 
8575 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
8576 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
8577 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
8578 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8579 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8580 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
8581 
8582 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
8583 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
8584 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
8585 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8586 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8587 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
8588 
8589 /* Bit 3 : Write '1' to Enable interrupt for END event */
8590 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
8591 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
8592 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8593 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8594 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
8595 
8596 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
8597 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
8598 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
8599 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8600 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8601 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
8602 
8603 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
8604 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
8605 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
8606 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8607 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8608 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
8609 
8610 /* Bit 0 : Write '1' to Enable interrupt for READY event */
8611 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
8612 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
8613 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
8614 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
8615 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
8616 
8617 /* Register: RADIO_INTENCLR */
8618 /* Description: Disable interrupt */
8619 
8620 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
8621 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
8622 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
8623 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8624 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8625 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
8626 
8627 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
8628 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
8629 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
8630 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8631 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8632 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
8633 
8634 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
8635 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
8636 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
8637 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8638 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8639 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
8640 
8641 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
8642 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
8643 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
8644 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8645 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8646 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
8647 
8648 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
8649 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
8650 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
8651 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8652 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8653 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
8654 
8655 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
8656 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
8657 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
8658 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8659 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8660 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
8661 
8662 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
8663 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
8664 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
8665 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8666 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8667 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
8668 
8669 /* Bit 3 : Write '1' to Disable interrupt for END event */
8670 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
8671 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8672 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8673 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8674 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
8675 
8676 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
8677 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
8678 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
8679 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8680 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8681 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
8682 
8683 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
8684 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
8685 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
8686 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8687 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8688 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
8689 
8690 /* Bit 0 : Write '1' to Disable interrupt for READY event */
8691 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
8692 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
8693 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
8694 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
8695 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
8696 
8697 /* Register: RADIO_CRCSTATUS */
8698 /* Description: CRC status */
8699 
8700 /* Bit 0 : CRC status of packet received */
8701 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
8702 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
8703 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
8704 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
8705 
8706 /* Register: RADIO_RXMATCH */
8707 /* Description: Received address */
8708 
8709 /* Bits 2..0 : Received address */
8710 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
8711 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
8712 
8713 /* Register: RADIO_RXCRC */
8714 /* Description: CRC field of previously received packet */
8715 
8716 /* Bits 23..0 : CRC field of previously received packet */
8717 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
8718 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
8719 
8720 /* Register: RADIO_DAI */
8721 /* Description: Device address match index */
8722 
8723 /* Bits 2..0 : Device address match index */
8724 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
8725 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
8726 
8727 /* Register: RADIO_PACKETPTR */
8728 /* Description: Packet pointer */
8729 
8730 /* Bits 31..0 : Packet pointer */
8731 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
8732 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
8733 
8734 /* Register: RADIO_FREQUENCY */
8735 /* Description: Frequency */
8736 
8737 /* Bit 8 : Channel map selection. */
8738 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
8739 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
8740 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
8741 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
8742 
8743 /* Bits 6..0 : Radio channel frequency */
8744 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
8745 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
8746 
8747 /* Register: RADIO_TXPOWER */
8748 /* Description: Output power */
8749 
8750 /* Bits 7..0 : RADIO output power. */
8751 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
8752 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
8753 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
8754 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
8755 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
8756 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
8757 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
8758 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
8759 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
8760 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
8761 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
8762 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator -  -40 dBm */
8763 
8764 /* Register: RADIO_MODE */
8765 /* Description: Data rate and modulation */
8766 
8767 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
8768 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
8769 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
8770 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
8771 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
8772 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
8773 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
8774 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
8775 
8776 /* Register: RADIO_PCNF0 */
8777 /* Description: Packet configuration register 0 */
8778 
8779 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
8780 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
8781 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
8782 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
8783 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
8784 
8785 /* Bit 20 : Include or exclude S1 field in RAM */
8786 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
8787 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
8788 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
8789 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
8790 
8791 /* Bits 19..16 : Length on air of S1 field in number of bits. */
8792 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
8793 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
8794 
8795 /* Bit 8 : Length on air of S0 field in number of bytes. */
8796 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
8797 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
8798 
8799 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
8800 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
8801 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
8802 
8803 /* Register: RADIO_PCNF1 */
8804 /* Description: Packet configuration register 1 */
8805 
8806 /* Bit 25 : Enable or disable packet whitening */
8807 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
8808 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
8809 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
8810 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
8811 
8812 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
8813 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
8814 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
8815 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
8816 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
8817 
8818 /* Bits 18..16 : Base address length in number of bytes */
8819 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
8820 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
8821 
8822 /* Bits 15..8 : Static length in number of bytes */
8823 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
8824 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
8825 
8826 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
8827 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
8828 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
8829 
8830 /* Register: RADIO_BASE0 */
8831 /* Description: Base address 0 */
8832 
8833 /* Bits 31..0 : Base address 0 */
8834 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
8835 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
8836 
8837 /* Register: RADIO_BASE1 */
8838 /* Description: Base address 1 */
8839 
8840 /* Bits 31..0 : Base address 1 */
8841 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
8842 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
8843 
8844 /* Register: RADIO_PREFIX0 */
8845 /* Description: Prefixes bytes for logical addresses 0-3 */
8846 
8847 /* Bits 31..24 : Address prefix 3. */
8848 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
8849 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
8850 
8851 /* Bits 23..16 : Address prefix 2. */
8852 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
8853 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
8854 
8855 /* Bits 15..8 : Address prefix 1. */
8856 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
8857 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
8858 
8859 /* Bits 7..0 : Address prefix 0. */
8860 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
8861 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
8862 
8863 /* Register: RADIO_PREFIX1 */
8864 /* Description: Prefixes bytes for logical addresses 4-7 */
8865 
8866 /* Bits 31..24 : Address prefix 7. */
8867 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
8868 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
8869 
8870 /* Bits 23..16 : Address prefix 6. */
8871 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
8872 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
8873 
8874 /* Bits 15..8 : Address prefix 5. */
8875 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
8876 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
8877 
8878 /* Bits 7..0 : Address prefix 4. */
8879 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
8880 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
8881 
8882 /* Register: RADIO_TXADDRESS */
8883 /* Description: Transmit address select */
8884 
8885 /* Bits 2..0 : Transmit address select */
8886 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
8887 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
8888 
8889 /* Register: RADIO_RXADDRESSES */
8890 /* Description: Receive address select */
8891 
8892 /* Bit 7 : Enable or disable reception on logical address 7. */
8893 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
8894 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
8895 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
8896 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
8897 
8898 /* Bit 6 : Enable or disable reception on logical address 6. */
8899 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
8900 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
8901 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
8902 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
8903 
8904 /* Bit 5 : Enable or disable reception on logical address 5. */
8905 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
8906 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
8907 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
8908 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
8909 
8910 /* Bit 4 : Enable or disable reception on logical address 4. */
8911 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
8912 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
8913 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
8914 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
8915 
8916 /* Bit 3 : Enable or disable reception on logical address 3. */
8917 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
8918 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
8919 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
8920 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
8921 
8922 /* Bit 2 : Enable or disable reception on logical address 2. */
8923 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
8924 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
8925 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
8926 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
8927 
8928 /* Bit 1 : Enable or disable reception on logical address 1. */
8929 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
8930 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
8931 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
8932 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
8933 
8934 /* Bit 0 : Enable or disable reception on logical address 0. */
8935 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
8936 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
8937 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
8938 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
8939 
8940 /* Register: RADIO_CRCCNF */
8941 /* Description: CRC configuration */
8942 
8943 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
8944 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
8945 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
8946 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
8947 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
8948 
8949 /* Bits 1..0 : CRC length in number of bytes. */
8950 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
8951 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
8952 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
8953 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
8954 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
8955 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
8956 
8957 /* Register: RADIO_CRCPOLY */
8958 /* Description: CRC polynomial */
8959 
8960 /* Bits 23..0 : CRC polynomial */
8961 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
8962 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
8963 
8964 /* Register: RADIO_CRCINIT */
8965 /* Description: CRC initial value */
8966 
8967 /* Bits 23..0 : CRC initial value */
8968 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
8969 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
8970 
8971 /* Register: RADIO_TIFS */
8972 /* Description: Inter Frame Spacing in us */
8973 
8974 /* Bits 7..0 : Inter Frame Spacing in us */
8975 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
8976 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
8977 
8978 /* Register: RADIO_RSSISAMPLE */
8979 /* Description: RSSI sample */
8980 
8981 /* Bits 6..0 : RSSI sample */
8982 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
8983 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
8984 
8985 /* Register: RADIO_STATE */
8986 /* Description: Current radio state */
8987 
8988 /* Bits 3..0 : Current radio state */
8989 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
8990 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
8991 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
8992 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
8993 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
8994 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
8995 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
8996 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
8997 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
8998 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
8999 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
9000 
9001 /* Register: RADIO_DATAWHITEIV */
9002 /* Description: Data whitening initial value */
9003 
9004 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
9005 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
9006 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
9007 
9008 /* Register: RADIO_BCC */
9009 /* Description: Bit counter compare */
9010 
9011 /* Bits 31..0 : Bit counter compare */
9012 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
9013 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
9014 
9015 /* Register: RADIO_DAB */
9016 /* Description: Description collection[0]:  Device address base segment 0 */
9017 
9018 /* Bits 31..0 : Device address base segment 0 */
9019 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
9020 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
9021 
9022 /* Register: RADIO_DAP */
9023 /* Description: Description collection[0]:  Device address prefix 0 */
9024 
9025 /* Bits 15..0 : Device address prefix 0 */
9026 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
9027 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
9028 
9029 /* Register: RADIO_DACNF */
9030 /* Description: Device address match configuration */
9031 
9032 /* Bit 15 : TxAdd for device address 7 */
9033 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
9034 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
9035 
9036 /* Bit 14 : TxAdd for device address 6 */
9037 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
9038 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
9039 
9040 /* Bit 13 : TxAdd for device address 5 */
9041 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
9042 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
9043 
9044 /* Bit 12 : TxAdd for device address 4 */
9045 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
9046 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
9047 
9048 /* Bit 11 : TxAdd for device address 3 */
9049 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
9050 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
9051 
9052 /* Bit 10 : TxAdd for device address 2 */
9053 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
9054 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
9055 
9056 /* Bit 9 : TxAdd for device address 1 */
9057 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
9058 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
9059 
9060 /* Bit 8 : TxAdd for device address 0 */
9061 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
9062 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
9063 
9064 /* Bit 7 : Enable or disable device address matching using device address 7 */
9065 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
9066 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
9067 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
9068 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
9069 
9070 /* Bit 6 : Enable or disable device address matching using device address 6 */
9071 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
9072 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
9073 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
9074 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
9075 
9076 /* Bit 5 : Enable or disable device address matching using device address 5 */
9077 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
9078 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
9079 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
9080 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
9081 
9082 /* Bit 4 : Enable or disable device address matching using device address 4 */
9083 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
9084 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
9085 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
9086 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
9087 
9088 /* Bit 3 : Enable or disable device address matching using device address 3 */
9089 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
9090 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
9091 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
9092 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
9093 
9094 /* Bit 2 : Enable or disable device address matching using device address 2 */
9095 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
9096 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
9097 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
9098 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
9099 
9100 /* Bit 1 : Enable or disable device address matching using device address 1 */
9101 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
9102 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
9103 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
9104 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
9105 
9106 /* Bit 0 : Enable or disable device address matching using device address 0 */
9107 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
9108 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
9109 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
9110 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
9111 
9112 /* Register: RADIO_MODECNF0 */
9113 /* Description: Radio mode configuration register 0 */
9114 
9115 /* Bits 9..8 : Default TX value */
9116 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
9117 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
9118 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
9119 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
9120 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
9121 
9122 /* Bit 0 : Radio ramp-up time */
9123 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
9124 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
9125 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
9126 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
9127 
9128 /* Register: RADIO_POWER */
9129 /* Description: Peripheral power control */
9130 
9131 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
9132 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
9133 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
9134 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
9135 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
9136 
9137 
9138 /* Peripheral: RNG */
9139 /* Description: Random Number Generator */
9140 
9141 /* Register: RNG_SHORTS */
9142 /* Description: Shortcut register */
9143 
9144 /* Bit 0 : Shortcut between VALRDY event and STOP task */
9145 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
9146 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
9147 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9148 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9149 
9150 /* Register: RNG_INTENSET */
9151 /* Description: Enable interrupt */
9152 
9153 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
9154 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
9155 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
9156 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9157 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9158 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
9159 
9160 /* Register: RNG_INTENCLR */
9161 /* Description: Disable interrupt */
9162 
9163 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
9164 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
9165 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
9166 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9167 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9168 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
9169 
9170 /* Register: RNG_CONFIG */
9171 /* Description: Configuration register */
9172 
9173 /* Bit 0 : Bias correction */
9174 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
9175 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
9176 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
9177 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
9178 
9179 /* Register: RNG_VALUE */
9180 /* Description: Output random number */
9181 
9182 /* Bits 7..0 : Generated random number */
9183 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
9184 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
9185 
9186 
9187 /* Peripheral: RTC */
9188 /* Description: Real time counter 0 */
9189 
9190 /* Register: RTC_INTENSET */
9191 /* Description: Enable interrupt */
9192 
9193 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
9194 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9195 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9196 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9197 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9198 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
9199 
9200 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
9201 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9202 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9203 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9204 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9205 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
9206 
9207 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
9208 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9209 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9210 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9211 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9212 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
9213 
9214 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
9215 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9216 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9217 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9218 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9219 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
9220 
9221 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
9222 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9223 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9224 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9225 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9226 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
9227 
9228 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
9229 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
9230 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
9231 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9232 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9233 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
9234 
9235 /* Register: RTC_INTENCLR */
9236 /* Description: Disable interrupt */
9237 
9238 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
9239 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9240 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9241 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9242 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9243 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9244 
9245 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
9246 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9247 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9248 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9249 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9250 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9251 
9252 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
9253 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9254 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9255 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9256 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9257 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9258 
9259 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
9260 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9261 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9262 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9263 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9264 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9265 
9266 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
9267 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9268 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9269 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9270 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9271 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9272 
9273 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
9274 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
9275 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
9276 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9277 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9278 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
9279 
9280 /* Register: RTC_EVTEN */
9281 /* Description: Enable or disable event routing */
9282 
9283 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
9284 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9285 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9286 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
9287 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
9288 
9289 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
9290 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9291 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9292 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
9293 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
9294 
9295 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
9296 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9297 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9298 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
9299 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
9300 
9301 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
9302 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9303 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9304 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
9305 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
9306 
9307 /* Bit 1 : Enable or disable event routing for OVRFLW event */
9308 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9309 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9310 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
9311 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
9312 
9313 /* Bit 0 : Enable or disable event routing for TICK event */
9314 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
9315 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
9316 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
9317 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
9318 
9319 /* Register: RTC_EVTENSET */
9320 /* Description: Enable event routing */
9321 
9322 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
9323 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9324 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9325 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9326 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9327 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
9328 
9329 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
9330 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9331 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9332 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9333 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9334 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
9335 
9336 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
9337 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9338 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9339 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9340 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9341 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
9342 
9343 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
9344 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9345 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9346 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9347 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9348 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
9349 
9350 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
9351 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9352 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9353 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9354 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9355 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
9356 
9357 /* Bit 0 : Write '1' to Enable event routing for TICK event */
9358 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
9359 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
9360 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9361 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9362 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
9363 
9364 /* Register: RTC_EVTENCLR */
9365 /* Description: Disable event routing */
9366 
9367 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
9368 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9369 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9370 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9371 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9372 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9373 
9374 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
9375 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9376 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9377 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9378 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9379 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9380 
9381 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
9382 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9383 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9384 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9385 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9386 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9387 
9388 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
9389 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9390 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9391 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9392 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9393 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9394 
9395 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
9396 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9397 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9398 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9399 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9400 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9401 
9402 /* Bit 0 : Write '1' to Disable event routing for TICK event */
9403 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
9404 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
9405 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9406 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9407 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
9408 
9409 /* Register: RTC_COUNTER */
9410 /* Description: Current COUNTER value */
9411 
9412 /* Bits 23..0 : Counter value */
9413 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
9414 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
9415 
9416 /* Register: RTC_PRESCALER */
9417 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
9418 
9419 /* Bits 11..0 : Prescaler value */
9420 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9421 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9422 
9423 /* Register: RTC_CC */
9424 /* Description: Description collection[0]:  Compare register 0 */
9425 
9426 /* Bits 23..0 : Compare value */
9427 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
9428 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
9429 
9430 
9431 /* Peripheral: SAADC */
9432 /* Description: Analog to Digital Converter */
9433 
9434 /* Register: SAADC_INTEN */
9435 /* Description: Enable or disable interrupt */
9436 
9437 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
9438 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
9439 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
9440 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
9441 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
9442 
9443 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
9444 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
9445 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
9446 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
9447 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
9448 
9449 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
9450 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
9451 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
9452 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
9453 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
9454 
9455 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
9456 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
9457 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
9458 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
9459 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
9460 
9461 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
9462 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
9463 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
9464 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
9465 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
9466 
9467 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
9468 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
9469 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
9470 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
9471 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
9472 
9473 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
9474 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
9475 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
9476 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
9477 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
9478 
9479 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
9480 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
9481 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
9482 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
9483 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
9484 
9485 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
9486 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
9487 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
9488 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
9489 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
9490 
9491 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
9492 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
9493 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
9494 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
9495 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
9496 
9497 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
9498 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
9499 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
9500 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
9501 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
9502 
9503 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
9504 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
9505 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
9506 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
9507 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
9508 
9509 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
9510 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
9511 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
9512 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
9513 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
9514 
9515 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
9516 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
9517 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
9518 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
9519 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
9520 
9521 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
9522 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
9523 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
9524 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
9525 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
9526 
9527 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
9528 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
9529 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
9530 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
9531 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
9532 
9533 /* Bit 5 : Enable or disable interrupt for STOPPED event */
9534 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
9535 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9536 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9537 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9538 
9539 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
9540 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
9541 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
9542 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
9543 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
9544 
9545 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
9546 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
9547 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
9548 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
9549 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
9550 
9551 /* Bit 2 : Enable or disable interrupt for DONE event */
9552 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
9553 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
9554 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
9555 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
9556 
9557 /* Bit 1 : Enable or disable interrupt for END event */
9558 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
9559 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
9560 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
9561 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
9562 
9563 /* Bit 0 : Enable or disable interrupt for STARTED event */
9564 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
9565 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
9566 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
9567 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
9568 
9569 /* Register: SAADC_INTENSET */
9570 /* Description: Enable interrupt */
9571 
9572 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
9573 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
9574 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
9575 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9576 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9577 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
9578 
9579 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
9580 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
9581 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
9582 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9583 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9584 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
9585 
9586 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
9587 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
9588 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
9589 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9590 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9591 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
9592 
9593 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
9594 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
9595 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
9596 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9597 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9598 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
9599 
9600 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
9601 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
9602 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
9603 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9604 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9605 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
9606 
9607 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
9608 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
9609 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
9610 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9611 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9612 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
9613 
9614 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
9615 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
9616 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
9617 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9618 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9619 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
9620 
9621 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
9622 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
9623 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
9624 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9625 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9626 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
9627 
9628 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
9629 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
9630 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
9631 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9632 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9633 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
9634 
9635 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
9636 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
9637 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
9638 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9639 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9640 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
9641 
9642 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
9643 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
9644 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
9645 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9646 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9647 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
9648 
9649 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
9650 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
9651 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
9652 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9653 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9654 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
9655 
9656 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
9657 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
9658 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
9659 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9660 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9661 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
9662 
9663 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
9664 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
9665 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
9666 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9667 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9668 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
9669 
9670 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
9671 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
9672 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
9673 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9674 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9675 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
9676 
9677 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
9678 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
9679 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
9680 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9681 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9682 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
9683 
9684 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
9685 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
9686 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9687 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9688 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9689 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9690 
9691 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
9692 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
9693 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
9694 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9695 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9696 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
9697 
9698 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
9699 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
9700 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
9701 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9702 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9703 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
9704 
9705 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
9706 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
9707 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
9708 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
9709 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
9710 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
9711 
9712 /* Bit 1 : Write '1' to Enable interrupt for END event */
9713 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
9714 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
9715 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
9716 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9717 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
9718 
9719 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
9720 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
9721 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
9722 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
9723 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
9724 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
9725 
9726 /* Register: SAADC_INTENCLR */
9727 /* Description: Disable interrupt */
9728 
9729 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
9730 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
9731 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
9732 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9733 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9734 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
9735 
9736 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
9737 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
9738 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
9739 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9740 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9741 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
9742 
9743 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
9744 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
9745 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
9746 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9747 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9748 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
9749 
9750 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
9751 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
9752 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
9753 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9754 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9755 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
9756 
9757 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
9758 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
9759 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
9760 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9761 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9762 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
9763 
9764 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
9765 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
9766 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
9767 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9768 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9769 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
9770 
9771 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
9772 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
9773 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
9774 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9775 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9776 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
9777 
9778 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
9779 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
9780 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
9781 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9782 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9783 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
9784 
9785 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
9786 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
9787 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
9788 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9789 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9790 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
9791 
9792 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
9793 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
9794 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
9795 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9796 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9797 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
9798 
9799 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
9800 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
9801 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
9802 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9803 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9804 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
9805 
9806 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
9807 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
9808 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
9809 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9810 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9811 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
9812 
9813 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
9814 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
9815 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
9816 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9817 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9818 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
9819 
9820 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
9821 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
9822 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
9823 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9824 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9825 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
9826 
9827 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
9828 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
9829 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
9830 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9831 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9832 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
9833 
9834 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
9835 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
9836 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
9837 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9838 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9839 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
9840 
9841 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
9842 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
9843 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9844 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9845 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9846 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9847 
9848 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
9849 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
9850 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
9851 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9852 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9853 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
9854 
9855 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
9856 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
9857 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
9858 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9859 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9860 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
9861 
9862 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
9863 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
9864 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
9865 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
9866 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
9867 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
9868 
9869 /* Bit 1 : Write '1' to Disable interrupt for END event */
9870 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
9871 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
9872 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9873 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9874 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
9875 
9876 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
9877 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
9878 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
9879 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
9880 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
9881 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
9882 
9883 /* Register: SAADC_STATUS */
9884 /* Description: Status */
9885 
9886 /* Bit 0 : Status */
9887 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
9888 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
9889 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
9890 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
9891 
9892 /* Register: SAADC_ENABLE */
9893 /* Description: Enable or disable ADC */
9894 
9895 /* Bit 0 : Enable or disable ADC */
9896 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9897 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9898 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
9899 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
9900 
9901 /* Register: SAADC_CH_PSELP */
9902 /* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
9903 
9904 /* Bits 4..0 : Analog positive input channel */
9905 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
9906 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
9907 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
9908 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
9909 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
9910 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
9911 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
9912 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
9913 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
9914 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
9915 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
9916 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
9917 
9918 /* Register: SAADC_CH_PSELN */
9919 /* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
9920 
9921 /* Bits 4..0 : Analog negative input, enables differential channel */
9922 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
9923 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
9924 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
9925 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
9926 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
9927 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
9928 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
9929 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
9930 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
9931 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
9932 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
9933 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
9934 
9935 /* Register: SAADC_CH_CONFIG */
9936 /* Description: Description cluster[0]:  Input configuration for CH[0] */
9937 
9938 /* Bit 24 : Enable burst mode */
9939 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
9940 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
9941 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
9942 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
9943 
9944 /* Bit 20 : Enable differential mode */
9945 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
9946 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
9947 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
9948 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
9949 
9950 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
9951 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
9952 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
9953 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
9954 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
9955 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
9956 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
9957 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
9958 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
9959 
9960 /* Bit 12 : Reference control */
9961 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
9962 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
9963 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
9964 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
9965 
9966 /* Bits 10..8 : Gain control */
9967 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
9968 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
9969 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
9970 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
9971 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
9972 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
9973 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
9974 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
9975 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
9976 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
9977 
9978 /* Bits 5..4 : Negative channel resistor control */
9979 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
9980 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
9981 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
9982 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
9983 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
9984 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
9985 
9986 /* Bits 1..0 : Positive channel resistor control */
9987 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
9988 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
9989 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
9990 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
9991 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
9992 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
9993 
9994 /* Register: SAADC_CH_LIMIT */
9995 /* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
9996 
9997 /* Bits 31..16 : High level limit */
9998 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
9999 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
10000 
10001 /* Bits 15..0 : Low level limit */
10002 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
10003 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
10004 
10005 /* Register: SAADC_RESOLUTION */
10006 /* Description: Resolution configuration */
10007 
10008 /* Bits 2..0 : Set the resolution */
10009 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
10010 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
10011 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
10012 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
10013 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
10014 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
10015 
10016 /* Register: SAADC_OVERSAMPLE */
10017 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
10018 
10019 /* Bits 3..0 : Oversample control */
10020 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
10021 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
10022 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
10023 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
10024 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
10025 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
10026 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
10027 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
10028 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
10029 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
10030 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
10031 
10032 /* Register: SAADC_SAMPLERATE */
10033 /* Description: Controls normal or continuous sample rate */
10034 
10035 /* Bit 12 : Select mode for sample rate control */
10036 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
10037 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
10038 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
10039 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
10040 
10041 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
10042 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
10043 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
10044 
10045 /* Register: SAADC_RESULT_PTR */
10046 /* Description: Data pointer */
10047 
10048 /* Bits 31..0 : Data pointer */
10049 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10050 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10051 
10052 /* Register: SAADC_RESULT_MAXCNT */
10053 /* Description: Maximum number of buffer words to transfer */
10054 
10055 /* Bits 14..0 : Maximum number of buffer words to transfer */
10056 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10057 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10058 
10059 /* Register: SAADC_RESULT_AMOUNT */
10060 /* Description: Number of buffer words transferred since last START */
10061 
10062 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
10063 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10064 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10065 
10066 
10067 /* Peripheral: SPI */
10068 /* Description: Serial Peripheral Interface 0 */
10069 
10070 /* Register: SPI_INTENSET */
10071 /* Description: Enable interrupt */
10072 
10073 /* Bit 2 : Write '1' to Enable interrupt for READY event */
10074 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
10075 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
10076 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10077 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10078 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
10079 
10080 /* Register: SPI_INTENCLR */
10081 /* Description: Disable interrupt */
10082 
10083 /* Bit 2 : Write '1' to Disable interrupt for READY event */
10084 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
10085 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
10086 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10087 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10088 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
10089 
10090 /* Register: SPI_ENABLE */
10091 /* Description: Enable SPI */
10092 
10093 /* Bits 3..0 : Enable or disable SPI */
10094 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10095 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10096 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
10097 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
10098 
10099 /* Register: SPI_PSEL_SCK */
10100 /* Description: Pin select for SCK */
10101 
10102 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
10103 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
10104 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
10105 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
10106 
10107 /* Register: SPI_PSEL_MOSI */
10108 /* Description: Pin select for MOSI */
10109 
10110 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
10111 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
10112 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
10113 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
10114 
10115 /* Register: SPI_PSEL_MISO */
10116 /* Description: Pin select for MISO */
10117 
10118 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
10119 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
10120 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
10121 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
10122 
10123 /* Register: SPI_RXD */
10124 /* Description: RXD register */
10125 
10126 /* Bits 7..0 : RX data received. Double buffered */
10127 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
10128 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
10129 
10130 /* Register: SPI_TXD */
10131 /* Description: TXD register */
10132 
10133 /* Bits 7..0 : TX data to send. Double buffered */
10134 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
10135 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
10136 
10137 /* Register: SPI_FREQUENCY */
10138 /* Description: SPI frequency */
10139 
10140 /* Bits 31..0 : SPI master data rate */
10141 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10142 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10143 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
10144 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
10145 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
10146 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10147 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
10148 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
10149 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
10150 
10151 /* Register: SPI_CONFIG */
10152 /* Description: Configuration register */
10153 
10154 /* Bit 2 : Serial clock (SCK) polarity */
10155 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10156 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
10157 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
10158 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10159 
10160 /* Bit 1 : Serial clock (SCK) phase */
10161 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10162 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
10163 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
10164 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
10165 
10166 /* Bit 0 : Bit order */
10167 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
10168 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
10169 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
10170 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10171 
10172 
10173 /* Peripheral: SPIM */
10174 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
10175 
10176 /* Register: SPIM_SHORTS */
10177 /* Description: Shortcut register */
10178 
10179 /* Bit 17 : Shortcut between END event and START task */
10180 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
10181 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
10182 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
10183 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
10184 
10185 /* Register: SPIM_INTENSET */
10186 /* Description: Enable interrupt */
10187 
10188 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
10189 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
10190 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
10191 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
10192 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
10193 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
10194 
10195 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
10196 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10197 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10198 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10199 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10200 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10201 
10202 /* Bit 6 : Write '1' to Enable interrupt for END event */
10203 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
10204 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
10205 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10206 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10207 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
10208 
10209 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10210 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10211 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10212 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10213 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10214 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10215 
10216 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
10217 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10218 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10219 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10220 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10221 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
10222 
10223 /* Register: SPIM_INTENCLR */
10224 /* Description: Disable interrupt */
10225 
10226 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
10227 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
10228 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
10229 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
10230 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
10231 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
10232 
10233 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
10234 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10235 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10236 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10237 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10238 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10239 
10240 /* Bit 6 : Write '1' to Disable interrupt for END event */
10241 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
10242 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10243 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10244 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10245 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
10246 
10247 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10248 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10249 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10250 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10251 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10252 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10253 
10254 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
10255 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10256 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10257 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10258 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10259 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
10260 
10261 /* Register: SPIM_ENABLE */
10262 /* Description: Enable SPIM */
10263 
10264 /* Bits 3..0 : Enable or disable SPIM */
10265 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10266 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10267 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
10268 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
10269 
10270 /* Register: SPIM_PSEL_SCK */
10271 /* Description: Pin select for SCK */
10272 
10273 /* Bit 31 : Connection */
10274 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10275 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10276 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
10277 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10278 
10279 /* Bits 4..0 : Pin number */
10280 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
10281 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
10282 
10283 /* Register: SPIM_PSEL_MOSI */
10284 /* Description: Pin select for MOSI signal */
10285 
10286 /* Bit 31 : Connection */
10287 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10288 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10289 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
10290 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
10291 
10292 /* Bits 4..0 : Pin number */
10293 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
10294 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
10295 
10296 /* Register: SPIM_PSEL_MISO */
10297 /* Description: Pin select for MISO signal */
10298 
10299 /* Bit 31 : Connection */
10300 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10301 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10302 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
10303 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10304 
10305 /* Bits 4..0 : Pin number */
10306 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
10307 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
10308 
10309 /* Register: SPIM_FREQUENCY */
10310 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
10311 
10312 /* Bits 31..0 : SPI master data rate */
10313 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10314 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10315 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
10316 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
10317 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
10318 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10319 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
10320 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
10321 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
10322 
10323 /* Register: SPIM_RXD_PTR */
10324 /* Description: Data pointer */
10325 
10326 /* Bits 31..0 : Data pointer */
10327 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10328 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10329 
10330 /* Register: SPIM_RXD_MAXCNT */
10331 /* Description: Maximum number of bytes in receive buffer */
10332 
10333 /* Bits 7..0 : Maximum number of bytes in receive buffer */
10334 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10335 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10336 
10337 /* Register: SPIM_RXD_AMOUNT */
10338 /* Description: Number of bytes transferred in the last transaction */
10339 
10340 /* Bits 7..0 : Number of bytes transferred in the last transaction */
10341 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10342 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10343 
10344 /* Register: SPIM_RXD_LIST */
10345 /* Description: EasyDMA list type */
10346 
10347 /* Bits 2..0 : List type */
10348 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10349 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10350 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10351 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10352 
10353 /* Register: SPIM_TXD_PTR */
10354 /* Description: Data pointer */
10355 
10356 /* Bits 31..0 : Data pointer */
10357 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10358 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10359 
10360 /* Register: SPIM_TXD_MAXCNT */
10361 /* Description: Maximum number of bytes in transmit buffer */
10362 
10363 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
10364 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10365 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10366 
10367 /* Register: SPIM_TXD_AMOUNT */
10368 /* Description: Number of bytes transferred in the last transaction */
10369 
10370 /* Bits 7..0 : Number of bytes transferred in the last transaction */
10371 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10372 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10373 
10374 /* Register: SPIM_TXD_LIST */
10375 /* Description: EasyDMA list type */
10376 
10377 /* Bits 2..0 : List type */
10378 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10379 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10380 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10381 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10382 
10383 /* Register: SPIM_CONFIG */
10384 /* Description: Configuration register */
10385 
10386 /* Bit 2 : Serial clock (SCK) polarity */
10387 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10388 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
10389 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
10390 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10391 
10392 /* Bit 1 : Serial clock (SCK) phase */
10393 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10394 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
10395 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
10396 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
10397 
10398 /* Bit 0 : Bit order */
10399 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
10400 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
10401 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
10402 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10403 
10404 /* Register: SPIM_ORC */
10405 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
10406 
10407 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
10408 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
10409 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
10410 
10411 
10412 /* Peripheral: SPIS */
10413 /* Description: SPI Slave 0 */
10414 
10415 /* Register: SPIS_SHORTS */
10416 /* Description: Shortcut register */
10417 
10418 /* Bit 2 : Shortcut between END event and ACQUIRE task */
10419 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
10420 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
10421 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
10422 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
10423 
10424 /* Register: SPIS_INTENSET */
10425 /* Description: Enable interrupt */
10426 
10427 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
10428 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
10429 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
10430 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10431 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10432 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
10433 
10434 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10435 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10436 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10437 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10438 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10439 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10440 
10441 /* Bit 1 : Write '1' to Enable interrupt for END event */
10442 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
10443 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
10444 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10445 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10446 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
10447 
10448 /* Register: SPIS_INTENCLR */
10449 /* Description: Disable interrupt */
10450 
10451 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
10452 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
10453 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
10454 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10455 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10456 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
10457 
10458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10459 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10460 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10461 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10462 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10463 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10464 
10465 /* Bit 1 : Write '1' to Disable interrupt for END event */
10466 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
10467 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10468 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10469 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10470 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
10471 
10472 /* Register: SPIS_SEMSTAT */
10473 /* Description: Semaphore status register */
10474 
10475 /* Bits 1..0 : Semaphore status */
10476 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
10477 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
10478 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
10479 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
10480 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
10481 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
10482 
10483 /* Register: SPIS_STATUS */
10484 /* Description: Status from last transaction */
10485 
10486 /* Bit 1 : RX buffer overflow detected, and prevented */
10487 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
10488 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
10489 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
10490 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
10491 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
10492 
10493 /* Bit 0 : TX buffer over-read detected, and prevented */
10494 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
10495 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
10496 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
10497 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
10498 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
10499 
10500 /* Register: SPIS_ENABLE */
10501 /* Description: Enable SPI slave */
10502 
10503 /* Bits 3..0 : Enable or disable SPI slave */
10504 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10505 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10506 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
10507 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
10508 
10509 /* Register: SPIS_PSEL_SCK */
10510 /* Description: Pin select for SCK */
10511 
10512 /* Bit 31 : Connection */
10513 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10514 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10515 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
10516 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10517 
10518 /* Bits 4..0 : Pin number */
10519 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
10520 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
10521 
10522 /* Register: SPIS_PSEL_MISO */
10523 /* Description: Pin select for MISO signal */
10524 
10525 /* Bit 31 : Connection */
10526 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10527 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10528 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
10529 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10530 
10531 /* Bits 4..0 : Pin number */
10532 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
10533 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
10534 
10535 /* Register: SPIS_PSEL_MOSI */
10536 /* Description: Pin select for MOSI signal */
10537 
10538 /* Bit 31 : Connection */
10539 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10540 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10541 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
10542 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
10543 
10544 /* Bits 4..0 : Pin number */
10545 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
10546 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
10547 
10548 /* Register: SPIS_PSEL_CSN */
10549 /* Description: Pin select for CSN signal */
10550 
10551 /* Bit 31 : Connection */
10552 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10553 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10554 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
10555 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
10556 
10557 /* Bits 4..0 : Pin number */
10558 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
10559 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
10560 
10561 /* Register: SPIS_RXD_PTR */
10562 /* Description: RXD data pointer */
10563 
10564 /* Bits 31..0 : RXD data pointer */
10565 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10566 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10567 
10568 /* Register: SPIS_RXD_MAXCNT */
10569 /* Description: Maximum number of bytes in receive buffer */
10570 
10571 /* Bits 7..0 : Maximum number of bytes in receive buffer */
10572 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10573 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10574 
10575 /* Register: SPIS_RXD_AMOUNT */
10576 /* Description: Number of bytes received in last granted transaction */
10577 
10578 /* Bits 7..0 : Number of bytes received in the last granted transaction */
10579 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10580 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10581 
10582 /* Register: SPIS_TXD_PTR */
10583 /* Description: TXD data pointer */
10584 
10585 /* Bits 31..0 : TXD data pointer */
10586 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10587 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10588 
10589 /* Register: SPIS_TXD_MAXCNT */
10590 /* Description: Maximum number of bytes in transmit buffer */
10591 
10592 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
10593 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10594 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10595 
10596 /* Register: SPIS_TXD_AMOUNT */
10597 /* Description: Number of bytes transmitted in last granted transaction */
10598 
10599 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
10600 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10601 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10602 
10603 /* Register: SPIS_CONFIG */
10604 /* Description: Configuration register */
10605 
10606 /* Bit 2 : Serial clock (SCK) polarity */
10607 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10608 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
10609 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
10610 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10611 
10612 /* Bit 1 : Serial clock (SCK) phase */
10613 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10614 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
10615 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
10616 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
10617 
10618 /* Bit 0 : Bit order */
10619 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
10620 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
10621 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
10622 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10623 
10624 /* Register: SPIS_DEF */
10625 /* Description: Default character. Character clocked out in case of an ignored transaction. */
10626 
10627 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
10628 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
10629 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
10630 
10631 /* Register: SPIS_ORC */
10632 /* Description: Over-read character */
10633 
10634 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
10635 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
10636 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
10637 
10638 
10639 /* Peripheral: TEMP */
10640 /* Description: Temperature Sensor */
10641 
10642 /* Register: TEMP_INTENSET */
10643 /* Description: Enable interrupt */
10644 
10645 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
10646 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
10647 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
10648 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10649 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10650 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
10651 
10652 /* Register: TEMP_INTENCLR */
10653 /* Description: Disable interrupt */
10654 
10655 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
10656 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
10657 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
10658 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10659 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10660 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
10661 
10662 /* Register: TEMP_TEMP */
10663 /* Description: Temperature in degC (0.25deg steps) */
10664 
10665 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
10666 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
10667 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
10668 
10669 /* Register: TEMP_A0 */
10670 /* Description: Slope of 1st piece wise linear function */
10671 
10672 /* Bits 11..0 : Slope of 1st piece wise linear function */
10673 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
10674 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
10675 
10676 /* Register: TEMP_A1 */
10677 /* Description: Slope of 2nd piece wise linear function */
10678 
10679 /* Bits 11..0 : Slope of 2nd piece wise linear function */
10680 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
10681 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
10682 
10683 /* Register: TEMP_A2 */
10684 /* Description: Slope of 3rd piece wise linear function */
10685 
10686 /* Bits 11..0 : Slope of 3rd piece wise linear function */
10687 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
10688 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
10689 
10690 /* Register: TEMP_A3 */
10691 /* Description: Slope of 4th piece wise linear function */
10692 
10693 /* Bits 11..0 : Slope of 4th piece wise linear function */
10694 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
10695 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
10696 
10697 /* Register: TEMP_A4 */
10698 /* Description: Slope of 5th piece wise linear function */
10699 
10700 /* Bits 11..0 : Slope of 5th piece wise linear function */
10701 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
10702 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
10703 
10704 /* Register: TEMP_A5 */
10705 /* Description: Slope of 6th piece wise linear function */
10706 
10707 /* Bits 11..0 : Slope of 6th piece wise linear function */
10708 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
10709 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
10710 
10711 /* Register: TEMP_B0 */
10712 /* Description: y-intercept of 1st piece wise linear function */
10713 
10714 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
10715 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
10716 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
10717 
10718 /* Register: TEMP_B1 */
10719 /* Description: y-intercept of 2nd piece wise linear function */
10720 
10721 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
10722 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
10723 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
10724 
10725 /* Register: TEMP_B2 */
10726 /* Description: y-intercept of 3rd piece wise linear function */
10727 
10728 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
10729 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
10730 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
10731 
10732 /* Register: TEMP_B3 */
10733 /* Description: y-intercept of 4th piece wise linear function */
10734 
10735 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
10736 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
10737 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
10738 
10739 /* Register: TEMP_B4 */
10740 /* Description: y-intercept of 5th piece wise linear function */
10741 
10742 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
10743 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
10744 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
10745 
10746 /* Register: TEMP_B5 */
10747 /* Description: y-intercept of 6th piece wise linear function */
10748 
10749 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
10750 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
10751 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
10752 
10753 /* Register: TEMP_T0 */
10754 /* Description: End point of 1st piece wise linear function */
10755 
10756 /* Bits 7..0 : End point of 1st piece wise linear function */
10757 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
10758 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
10759 
10760 /* Register: TEMP_T1 */
10761 /* Description: End point of 2nd piece wise linear function */
10762 
10763 /* Bits 7..0 : End point of 2nd piece wise linear function */
10764 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
10765 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
10766 
10767 /* Register: TEMP_T2 */
10768 /* Description: End point of 3rd piece wise linear function */
10769 
10770 /* Bits 7..0 : End point of 3rd piece wise linear function */
10771 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
10772 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
10773 
10774 /* Register: TEMP_T3 */
10775 /* Description: End point of 4th piece wise linear function */
10776 
10777 /* Bits 7..0 : End point of 4th piece wise linear function */
10778 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
10779 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
10780 
10781 /* Register: TEMP_T4 */
10782 /* Description: End point of 5th piece wise linear function */
10783 
10784 /* Bits 7..0 : End point of 5th piece wise linear function */
10785 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
10786 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
10787 
10788 
10789 /* Peripheral: TIMER */
10790 /* Description: Timer/Counter 0 */
10791 
10792 /* Register: TIMER_SHORTS */
10793 /* Description: Shortcut register */
10794 
10795 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
10796 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
10797 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
10798 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
10799 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
10800 
10801 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
10802 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
10803 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
10804 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
10805 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
10806 
10807 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
10808 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
10809 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
10810 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
10811 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
10812 
10813 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
10814 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
10815 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
10816 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
10817 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
10818 
10819 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
10820 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
10821 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
10822 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
10823 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
10824 
10825 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
10826 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
10827 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
10828 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
10829 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
10830 
10831 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
10832 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
10833 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
10834 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10835 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10836 
10837 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
10838 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
10839 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
10840 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10841 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10842 
10843 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
10844 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
10845 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
10846 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10847 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10848 
10849 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
10850 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
10851 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
10852 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10853 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10854 
10855 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
10856 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
10857 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
10858 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10859 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10860 
10861 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
10862 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
10863 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
10864 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10865 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10866 
10867 /* Register: TIMER_INTENSET */
10868 /* Description: Enable interrupt */
10869 
10870 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
10871 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10872 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10873 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10874 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10875 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
10876 
10877 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
10878 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10879 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10880 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10881 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10882 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
10883 
10884 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
10885 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10886 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10887 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10888 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10889 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
10890 
10891 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
10892 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10893 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10894 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10895 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10896 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
10897 
10898 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
10899 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10900 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10901 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10902 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10903 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
10904 
10905 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
10906 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10907 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10908 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10909 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10910 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
10911 
10912 /* Register: TIMER_INTENCLR */
10913 /* Description: Disable interrupt */
10914 
10915 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
10916 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10917 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10918 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10919 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10920 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
10921 
10922 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
10923 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10924 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10925 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10926 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10927 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
10928 
10929 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
10930 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10931 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10932 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10933 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10934 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10935 
10936 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
10937 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10938 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10939 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10940 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10941 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10942 
10943 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
10944 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10945 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10946 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10947 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10948 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10949 
10950 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
10951 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10952 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10953 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10954 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10955 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
10956 
10957 /* Register: TIMER_MODE */
10958 /* Description: Timer mode selection */
10959 
10960 /* Bits 1..0 : Timer mode */
10961 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
10962 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
10963 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
10964 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
10965 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
10966 
10967 /* Register: TIMER_BITMODE */
10968 /* Description: Configure the number of bits used by the TIMER */
10969 
10970 /* Bits 1..0 : Timer bit width */
10971 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
10972 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
10973 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
10974 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
10975 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
10976 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
10977 
10978 /* Register: TIMER_PRESCALER */
10979 /* Description: Timer prescaler register */
10980 
10981 /* Bits 3..0 : Prescaler value */
10982 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
10983 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
10984 
10985 /* Register: TIMER_CC */
10986 /* Description: Description collection[0]:  Capture/Compare register 0 */
10987 
10988 /* Bits 31..0 : Capture/Compare value */
10989 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
10990 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
10991 
10992 
10993 /* Peripheral: TWI */
10994 /* Description: I2C compatible Two-Wire Interface 0 */
10995 
10996 /* Register: TWI_SHORTS */
10997 /* Description: Shortcut register */
10998 
10999 /* Bit 1 : Shortcut between BB event and STOP task */
11000 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
11001 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
11002 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
11003 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
11004 
11005 /* Bit 0 : Shortcut between BB event and SUSPEND task */
11006 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
11007 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
11008 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11009 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11010 
11011 /* Register: TWI_INTENSET */
11012 /* Description: Enable interrupt */
11013 
11014 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11015 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11016 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11017 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11018 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11019 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11020 
11021 /* Bit 14 : Write '1' to Enable interrupt for BB event */
11022 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
11023 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
11024 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
11025 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
11026 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
11027 
11028 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11029 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11030 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11031 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11032 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11033 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
11034 
11035 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
11036 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
11037 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
11038 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11039 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11040 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
11041 
11042 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
11043 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
11044 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
11045 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11046 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11047 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
11048 
11049 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11050 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11051 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11052 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11053 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11054 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11055 
11056 /* Register: TWI_INTENCLR */
11057 /* Description: Disable interrupt */
11058 
11059 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11060 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11061 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11062 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11063 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11064 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11065 
11066 /* Bit 14 : Write '1' to Disable interrupt for BB event */
11067 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
11068 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
11069 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
11070 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
11071 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
11072 
11073 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11074 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11075 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11076 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11077 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11078 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11079 
11080 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
11081 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
11082 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
11083 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11084 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11085 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
11086 
11087 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
11088 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
11089 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
11090 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11091 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11092 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
11093 
11094 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11095 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11096 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11097 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11098 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11099 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11100 
11101 /* Register: TWI_ERRORSRC */
11102 /* Description: Error source */
11103 
11104 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11105 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11106 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11107 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
11108 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
11109 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11110 
11111 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11112 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
11113 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
11114 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
11115 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
11116 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11117 
11118 /* Bit 0 : Overrun error */
11119 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
11120 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
11121 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
11122 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
11123 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
11124 
11125 /* Register: TWI_ENABLE */
11126 /* Description: Enable TWI */
11127 
11128 /* Bits 3..0 : Enable or disable TWI */
11129 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11130 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11131 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
11132 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
11133 
11134 /* Register: TWI_PSELSCL */
11135 /* Description: Pin select for SCL */
11136 
11137 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
11138 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
11139 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
11140 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11141 
11142 /* Register: TWI_PSELSDA */
11143 /* Description: Pin select for SDA */
11144 
11145 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
11146 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
11147 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
11148 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11149 
11150 /* Register: TWI_RXD */
11151 /* Description: RXD register */
11152 
11153 /* Bits 7..0 : RXD register */
11154 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
11155 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
11156 
11157 /* Register: TWI_TXD */
11158 /* Description: TXD register */
11159 
11160 /* Bits 7..0 : TXD register */
11161 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
11162 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
11163 
11164 /* Register: TWI_FREQUENCY */
11165 /* Description: TWI frequency */
11166 
11167 /* Bits 31..0 : TWI master clock frequency */
11168 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11169 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11170 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
11171 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11172 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
11173 
11174 /* Register: TWI_ADDRESS */
11175 /* Description: Address used in the TWI transfer */
11176 
11177 /* Bits 6..0 : Address used in the TWI transfer */
11178 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11179 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11180 
11181 
11182 /* Peripheral: TWIM */
11183 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
11184 
11185 /* Register: TWIM_SHORTS */
11186 /* Description: Shortcut register */
11187 
11188 /* Bit 12 : Shortcut between LASTRX event and STOP task */
11189 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
11190 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
11191 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
11192 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
11193 
11194 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */
11195 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
11196 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
11197 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
11198 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
11199 
11200 /* Bit 9 : Shortcut between LASTTX event and STOP task */
11201 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
11202 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
11203 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
11204 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
11205 
11206 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
11207 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
11208 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
11209 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11210 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11211 
11212 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */
11213 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
11214 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
11215 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11216 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11217 
11218 /* Register: TWIM_INTEN */
11219 /* Description: Enable or disable interrupt */
11220 
11221 /* Bit 24 : Enable or disable interrupt for LASTTX event */
11222 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
11223 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
11224 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
11225 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
11226 
11227 /* Bit 23 : Enable or disable interrupt for LASTRX event */
11228 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
11229 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
11230 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
11231 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
11232 
11233 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11234 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11235 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11236 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11237 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11238 
11239 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11240 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11241 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11242 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11243 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11244 
11245 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
11246 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11247 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11248 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
11249 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
11250 
11251 /* Bit 9 : Enable or disable interrupt for ERROR event */
11252 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11253 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
11254 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11255 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11256 
11257 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11258 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11259 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11260 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11261 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11262 
11263 /* Register: TWIM_INTENSET */
11264 /* Description: Enable interrupt */
11265 
11266 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
11267 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
11268 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
11269 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11270 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11271 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
11272 
11273 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
11274 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
11275 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
11276 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11277 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11278 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
11279 
11280 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11281 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11282 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11283 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11284 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11285 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11286 
11287 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11288 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11289 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11290 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11291 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11292 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11293 
11294 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11295 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11296 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11297 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11298 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11299 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11300 
11301 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11302 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11303 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11304 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11305 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11306 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
11307 
11308 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11309 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11310 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11311 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11312 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11313 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11314 
11315 /* Register: TWIM_INTENCLR */
11316 /* Description: Disable interrupt */
11317 
11318 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
11319 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
11320 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
11321 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11322 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11323 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
11324 
11325 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
11326 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
11327 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
11328 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11329 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11330 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
11331 
11332 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11333 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11334 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11335 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11336 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11337 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11338 
11339 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11340 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11341 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11342 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11343 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11344 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11345 
11346 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11347 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11348 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11349 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11350 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11351 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11352 
11353 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11354 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11355 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11356 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11357 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11358 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11359 
11360 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11361 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11362 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11363 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11364 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11365 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11366 
11367 /* Register: TWIM_ERRORSRC */
11368 /* Description: Error source */
11369 
11370 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11371 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11372 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11373 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
11374 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11375 
11376 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11377 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
11378 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
11379 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
11380 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
11381 
11382 /* Bit 0 : Overrun error */
11383 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
11384 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
11385 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
11386 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
11387 
11388 /* Register: TWIM_ENABLE */
11389 /* Description: Enable TWIM */
11390 
11391 /* Bits 3..0 : Enable or disable TWIM */
11392 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11393 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11394 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
11395 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
11396 
11397 /* Register: TWIM_PSEL_SCL */
11398 /* Description: Pin select for SCL signal */
11399 
11400 /* Bit 31 : Connection */
11401 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11402 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11403 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
11404 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11405 
11406 /* Bits 4..0 : Pin number */
11407 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
11408 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
11409 
11410 /* Register: TWIM_PSEL_SDA */
11411 /* Description: Pin select for SDA signal */
11412 
11413 /* Bit 31 : Connection */
11414 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11415 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11416 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
11417 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11418 
11419 /* Bits 4..0 : Pin number */
11420 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
11421 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
11422 
11423 /* Register: TWIM_FREQUENCY */
11424 /* Description: TWI frequency */
11425 
11426 /* Bits 31..0 : TWI master clock frequency */
11427 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11428 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11429 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
11430 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11431 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
11432 
11433 /* Register: TWIM_RXD_PTR */
11434 /* Description: Data pointer */
11435 
11436 /* Bits 31..0 : Data pointer */
11437 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11438 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11439 
11440 /* Register: TWIM_RXD_MAXCNT */
11441 /* Description: Maximum number of bytes in receive buffer */
11442 
11443 /* Bits 7..0 : Maximum number of bytes in receive buffer */
11444 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11445 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11446 
11447 /* Register: TWIM_RXD_AMOUNT */
11448 /* Description: Number of bytes transferred in the last transaction */
11449 
11450 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
11451 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11452 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11453 
11454 /* Register: TWIM_RXD_LIST */
11455 /* Description: EasyDMA list type */
11456 
11457 /* Bits 2..0 : List type */
11458 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11459 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11460 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11461 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11462 
11463 /* Register: TWIM_TXD_PTR */
11464 /* Description: Data pointer */
11465 
11466 /* Bits 31..0 : Data pointer */
11467 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11468 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11469 
11470 /* Register: TWIM_TXD_MAXCNT */
11471 /* Description: Maximum number of bytes in transmit buffer */
11472 
11473 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
11474 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11475 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11476 
11477 /* Register: TWIM_TXD_AMOUNT */
11478 /* Description: Number of bytes transferred in the last transaction */
11479 
11480 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
11481 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11482 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11483 
11484 /* Register: TWIM_TXD_LIST */
11485 /* Description: EasyDMA list type */
11486 
11487 /* Bits 2..0 : List type */
11488 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11489 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11490 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11491 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11492 
11493 /* Register: TWIM_ADDRESS */
11494 /* Description: Address used in the TWI transfer */
11495 
11496 /* Bits 6..0 : Address used in the TWI transfer */
11497 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11498 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11499 
11500 
11501 /* Peripheral: TWIS */
11502 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
11503 
11504 /* Register: TWIS_SHORTS */
11505 /* Description: Shortcut register */
11506 
11507 /* Bit 14 : Shortcut between READ event and SUSPEND task */
11508 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
11509 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
11510 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11511 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11512 
11513 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
11514 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
11515 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
11516 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11517 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11518 
11519 /* Register: TWIS_INTEN */
11520 /* Description: Enable or disable interrupt */
11521 
11522 /* Bit 26 : Enable or disable interrupt for READ event */
11523 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
11524 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
11525 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
11526 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
11527 
11528 /* Bit 25 : Enable or disable interrupt for WRITE event */
11529 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11530 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
11531 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
11532 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
11533 
11534 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11535 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11536 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11537 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11538 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11539 
11540 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11541 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11542 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11543 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11544 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11545 
11546 /* Bit 9 : Enable or disable interrupt for ERROR event */
11547 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11548 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
11549 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11550 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11551 
11552 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11553 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11554 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11555 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11556 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11557 
11558 /* Register: TWIS_INTENSET */
11559 /* Description: Enable interrupt */
11560 
11561 /* Bit 26 : Write '1' to Enable interrupt for READ event */
11562 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
11563 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
11564 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
11565 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
11566 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
11567 
11568 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
11569 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11570 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
11571 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
11572 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
11573 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
11574 
11575 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11576 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11577 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11578 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11579 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11580 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11581 
11582 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11583 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11584 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11585 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11586 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11587 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11588 
11589 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11590 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11591 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11592 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11593 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11594 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
11595 
11596 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11597 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11598 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11599 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11600 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11601 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11602 
11603 /* Register: TWIS_INTENCLR */
11604 /* Description: Disable interrupt */
11605 
11606 /* Bit 26 : Write '1' to Disable interrupt for READ event */
11607 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
11608 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
11609 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
11610 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
11611 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
11612 
11613 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
11614 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11615 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
11616 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
11617 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
11618 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
11619 
11620 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11621 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11622 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11623 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11624 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11625 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11626 
11627 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11628 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11629 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11630 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11631 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11632 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11633 
11634 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11635 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11636 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11637 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11638 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11639 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11640 
11641 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11642 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11643 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11644 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11645 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11646 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11647 
11648 /* Register: TWIS_ERRORSRC */
11649 /* Description: Error source */
11650 
11651 /* Bit 3 : TX buffer over-read detected, and prevented */
11652 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
11653 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
11654 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
11655 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
11656 
11657 /* Bit 2 : NACK sent after receiving a data byte */
11658 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11659 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11660 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
11661 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11662 
11663 /* Bit 0 : RX buffer overflow detected, and prevented */
11664 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
11665 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
11666 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
11667 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
11668 
11669 /* Register: TWIS_MATCH */
11670 /* Description: Status register indicating which address had a match */
11671 
11672 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
11673 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
11674 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
11675 
11676 /* Register: TWIS_ENABLE */
11677 /* Description: Enable TWIS */
11678 
11679 /* Bits 3..0 : Enable or disable TWIS */
11680 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11681 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11682 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
11683 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
11684 
11685 /* Register: TWIS_PSEL_SCL */
11686 /* Description: Pin select for SCL signal */
11687 
11688 /* Bit 31 : Connection */
11689 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11690 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11691 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
11692 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11693 
11694 /* Bits 4..0 : Pin number */
11695 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
11696 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
11697 
11698 /* Register: TWIS_PSEL_SDA */
11699 /* Description: Pin select for SDA signal */
11700 
11701 /* Bit 31 : Connection */
11702 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11703 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11704 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
11705 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11706 
11707 /* Bits 4..0 : Pin number */
11708 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
11709 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
11710 
11711 /* Register: TWIS_RXD_PTR */
11712 /* Description: RXD Data pointer */
11713 
11714 /* Bits 31..0 : RXD Data pointer */
11715 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11716 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11717 
11718 /* Register: TWIS_RXD_MAXCNT */
11719 /* Description: Maximum number of bytes in RXD buffer */
11720 
11721 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
11722 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11723 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11724 
11725 /* Register: TWIS_RXD_AMOUNT */
11726 /* Description: Number of bytes transferred in the last RXD transaction */
11727 
11728 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
11729 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11730 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11731 
11732 /* Register: TWIS_TXD_PTR */
11733 /* Description: TXD Data pointer */
11734 
11735 /* Bits 31..0 : TXD Data pointer */
11736 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11737 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11738 
11739 /* Register: TWIS_TXD_MAXCNT */
11740 /* Description: Maximum number of bytes in TXD buffer */
11741 
11742 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
11743 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11744 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11745 
11746 /* Register: TWIS_TXD_AMOUNT */
11747 /* Description: Number of bytes transferred in the last TXD transaction */
11748 
11749 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
11750 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11751 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11752 
11753 /* Register: TWIS_ADDRESS */
11754 /* Description: Description collection[0]:  TWI slave address 0 */
11755 
11756 /* Bits 6..0 : TWI slave address */
11757 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11758 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11759 
11760 /* Register: TWIS_CONFIG */
11761 /* Description: Configuration register for the address match mechanism */
11762 
11763 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
11764 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
11765 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
11766 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
11767 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
11768 
11769 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
11770 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
11771 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
11772 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
11773 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
11774 
11775 /* Register: TWIS_ORC */
11776 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
11777 
11778 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
11779 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
11780 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
11781 
11782 
11783 /* Peripheral: UART */
11784 /* Description: Universal Asynchronous Receiver/Transmitter */
11785 
11786 /* Register: UART_SHORTS */
11787 /* Description: Shortcut register */
11788 
11789 /* Bit 4 : Shortcut between NCTS event and STOPRX task */
11790 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
11791 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
11792 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
11793 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
11794 
11795 /* Bit 3 : Shortcut between CTS event and STARTRX task */
11796 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
11797 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
11798 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11799 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11800 
11801 /* Register: UART_INTENSET */
11802 /* Description: Enable interrupt */
11803 
11804 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
11805 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
11806 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
11807 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
11808 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
11809 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
11810 
11811 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11812 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11813 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11814 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11815 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11816 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
11817 
11818 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
11819 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
11820 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
11821 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11822 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11823 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
11824 
11825 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
11826 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11827 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
11828 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11829 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11830 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
11831 
11832 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
11833 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11834 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
11835 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
11836 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
11837 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
11838 
11839 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
11840 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
11841 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
11842 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
11843 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
11844 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
11845 
11846 /* Register: UART_INTENCLR */
11847 /* Description: Disable interrupt */
11848 
11849 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
11850 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
11851 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
11852 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
11853 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
11854 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
11855 
11856 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11857 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11858 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11859 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11860 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11861 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11862 
11863 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
11864 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
11865 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
11866 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11867 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11868 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
11869 
11870 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
11871 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11872 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
11873 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11874 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11875 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
11876 
11877 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
11878 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11879 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
11880 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
11881 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
11882 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
11883 
11884 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
11885 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
11886 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
11887 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
11888 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
11889 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
11890 
11891 /* Register: UART_ERRORSRC */
11892 /* Description: Error source */
11893 
11894 /* Bit 3 : Break condition */
11895 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
11896 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
11897 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
11898 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
11899 
11900 /* Bit 2 : Framing error occurred */
11901 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
11902 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
11903 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
11904 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
11905 
11906 /* Bit 1 : Parity error */
11907 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
11908 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
11909 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
11910 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
11911 
11912 /* Bit 0 : Overrun error */
11913 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
11914 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
11915 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
11916 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
11917 
11918 /* Register: UART_ENABLE */
11919 /* Description: Enable UART */
11920 
11921 /* Bits 3..0 : Enable or disable UART */
11922 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11923 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11924 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
11925 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
11926 
11927 /* Register: UART_PSELRTS */
11928 /* Description: Pin select for RTS */
11929 
11930 /* Bits 31..0 : Pin number configuration for UART RTS signal */
11931 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
11932 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
11933 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11934 
11935 /* Register: UART_PSELTXD */
11936 /* Description: Pin select for TXD */
11937 
11938 /* Bits 31..0 : Pin number configuration for UART TXD signal */
11939 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
11940 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
11941 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11942 
11943 /* Register: UART_PSELCTS */
11944 /* Description: Pin select for CTS */
11945 
11946 /* Bits 31..0 : Pin number configuration for UART CTS signal */
11947 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
11948 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
11949 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11950 
11951 /* Register: UART_PSELRXD */
11952 /* Description: Pin select for RXD */
11953 
11954 /* Bits 31..0 : Pin number configuration for UART RXD signal */
11955 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
11956 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
11957 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11958 
11959 /* Register: UART_RXD */
11960 /* Description: RXD register */
11961 
11962 /* Bits 7..0 : RX data received in previous transfers, double buffered */
11963 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
11964 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
11965 
11966 /* Register: UART_TXD */
11967 /* Description: TXD register */
11968 
11969 /* Bits 7..0 : TX data to be transferred */
11970 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
11971 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
11972 
11973 /* Register: UART_BAUDRATE */
11974 /* Description: Baud rate */
11975 
11976 /* Bits 31..0 : Baud rate */
11977 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
11978 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
11979 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
11980 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
11981 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
11982 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
11983 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
11984 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
11985 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
11986 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
11987 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
11988 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
11989 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
11990 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
11991 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
11992 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
11993 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
11994 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
11995 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
11996 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
11997 
11998 /* Register: UART_CONFIG */
11999 /* Description: Configuration of parity and hardware flow control */
12000 
12001 /* Bits 3..1 : Parity */
12002 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12003 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
12004 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
12005 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
12006 
12007 /* Bit 0 : Hardware flow control */
12008 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
12009 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
12010 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12011 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12012 
12013 
12014 /* Peripheral: UARTE */
12015 /* Description: UART with EasyDMA */
12016 
12017 /* Register: UARTE_SHORTS */
12018 /* Description: Shortcut register */
12019 
12020 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */
12021 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
12022 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
12023 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
12024 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
12025 
12026 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */
12027 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
12028 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
12029 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
12030 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
12031 
12032 /* Register: UARTE_INTEN */
12033 /* Description: Enable or disable interrupt */
12034 
12035 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
12036 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
12037 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
12038 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
12039 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
12040 
12041 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
12042 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12043 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12044 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
12045 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
12046 
12047 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
12048 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12049 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12050 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
12051 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
12052 
12053 /* Bit 17 : Enable or disable interrupt for RXTO event */
12054 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12055 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
12056 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
12057 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
12058 
12059 /* Bit 9 : Enable or disable interrupt for ERROR event */
12060 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12061 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
12062 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
12063 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
12064 
12065 /* Bit 8 : Enable or disable interrupt for ENDTX event */
12066 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12067 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12068 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
12069 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
12070 
12071 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
12072 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12073 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12074 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
12075 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
12076 
12077 /* Bit 4 : Enable or disable interrupt for ENDRX event */
12078 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12079 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12080 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
12081 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
12082 
12083 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
12084 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12085 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12086 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
12087 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
12088 
12089 /* Bit 1 : Enable or disable interrupt for NCTS event */
12090 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12091 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
12092 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
12093 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
12094 
12095 /* Bit 0 : Enable or disable interrupt for CTS event */
12096 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
12097 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
12098 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
12099 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
12100 
12101 /* Register: UARTE_INTENSET */
12102 /* Description: Enable interrupt */
12103 
12104 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
12105 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
12106 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
12107 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12108 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12109 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
12110 
12111 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
12112 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12113 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12114 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12115 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12116 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
12117 
12118 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
12119 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12120 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12121 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12122 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12123 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
12124 
12125 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
12126 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12127 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
12128 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
12129 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
12130 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
12131 
12132 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
12133 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12134 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
12135 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
12136 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
12137 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
12138 
12139 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
12140 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12141 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12142 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12143 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12144 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12145 
12146 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
12147 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12148 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12149 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12150 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12151 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
12152 
12153 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
12154 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12155 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12156 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12157 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12158 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12159 
12160 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
12161 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12162 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12163 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12164 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12165 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
12166 
12167 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
12168 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12169 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
12170 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
12171 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
12172 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
12173 
12174 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
12175 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
12176 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
12177 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
12178 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
12179 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
12180 
12181 /* Register: UARTE_INTENCLR */
12182 /* Description: Disable interrupt */
12183 
12184 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
12185 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
12186 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
12187 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12188 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12189 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
12190 
12191 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
12192 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12193 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12194 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12195 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12196 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
12197 
12198 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
12199 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12200 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12201 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12202 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12203 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
12204 
12205 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
12206 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12207 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
12208 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
12209 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
12210 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
12211 
12212 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
12213 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12214 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
12215 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
12216 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12217 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
12218 
12219 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
12220 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12221 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12222 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12223 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12224 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12225 
12226 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
12227 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12228 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12229 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12230 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12231 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
12232 
12233 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
12234 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12235 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12236 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12237 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12238 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12239 
12240 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
12241 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12242 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12243 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12244 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12245 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
12246 
12247 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
12248 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12249 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
12250 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
12251 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
12252 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
12253 
12254 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
12255 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
12256 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
12257 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
12258 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12259 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
12260 
12261 /* Register: UARTE_ERRORSRC */
12262 /* Description: Error source */
12263 
12264 /* Bit 3 : Break condition */
12265 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
12266 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
12267 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
12268 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
12269 
12270 /* Bit 2 : Framing error occurred */
12271 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
12272 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
12273 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
12274 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
12275 
12276 /* Bit 1 : Parity error */
12277 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12278 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
12279 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
12280 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
12281 
12282 /* Bit 0 : Overrun error */
12283 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
12284 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
12285 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
12286 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
12287 
12288 /* Register: UARTE_ENABLE */
12289 /* Description: Enable UART */
12290 
12291 /* Bits 3..0 : Enable or disable UARTE */
12292 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12293 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12294 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
12295 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
12296 
12297 /* Register: UARTE_PSEL_RTS */
12298 /* Description: Pin select for RTS signal */
12299 
12300 /* Bit 31 : Connection */
12301 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12302 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12303 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
12304 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12305 
12306 /* Bits 4..0 : Pin number */
12307 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
12308 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
12309 
12310 /* Register: UARTE_PSEL_TXD */
12311 /* Description: Pin select for TXD signal */
12312 
12313 /* Bit 31 : Connection */
12314 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12315 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12316 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
12317 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12318 
12319 /* Bits 4..0 : Pin number */
12320 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
12321 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
12322 
12323 /* Register: UARTE_PSEL_CTS */
12324 /* Description: Pin select for CTS signal */
12325 
12326 /* Bit 31 : Connection */
12327 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12328 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12329 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
12330 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12331 
12332 /* Bits 4..0 : Pin number */
12333 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
12334 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
12335 
12336 /* Register: UARTE_PSEL_RXD */
12337 /* Description: Pin select for RXD signal */
12338 
12339 /* Bit 31 : Connection */
12340 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12341 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12342 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
12343 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12344 
12345 /* Bits 4..0 : Pin number */
12346 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
12347 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
12348 
12349 /* Register: UARTE_BAUDRATE */
12350 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
12351 
12352 /* Bits 31..0 : Baud rate */
12353 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
12354 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
12355 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
12356 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
12357 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
12358 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
12359 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
12360 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
12361 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
12362 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
12363 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
12364 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
12365 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
12366 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
12367 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
12368 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
12369 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
12370 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
12371 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
12372 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
12373 
12374 /* Register: UARTE_RXD_PTR */
12375 /* Description: Data pointer */
12376 
12377 /* Bits 31..0 : Data pointer */
12378 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12379 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12380 
12381 /* Register: UARTE_RXD_MAXCNT */
12382 /* Description: Maximum number of bytes in receive buffer */
12383 
12384 /* Bits 7..0 : Maximum number of bytes in receive buffer */
12385 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12386 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12387 
12388 /* Register: UARTE_RXD_AMOUNT */
12389 /* Description: Number of bytes transferred in the last transaction */
12390 
12391 /* Bits 7..0 : Number of bytes transferred in the last transaction */
12392 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12393 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12394 
12395 /* Register: UARTE_TXD_PTR */
12396 /* Description: Data pointer */
12397 
12398 /* Bits 31..0 : Data pointer */
12399 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12400 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12401 
12402 /* Register: UARTE_TXD_MAXCNT */
12403 /* Description: Maximum number of bytes in transmit buffer */
12404 
12405 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
12406 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12407 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12408 
12409 /* Register: UARTE_TXD_AMOUNT */
12410 /* Description: Number of bytes transferred in the last transaction */
12411 
12412 /* Bits 7..0 : Number of bytes transferred in the last transaction */
12413 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12414 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12415 
12416 /* Register: UARTE_CONFIG */
12417 /* Description: Configuration of parity and hardware flow control */
12418 
12419 /* Bits 3..1 : Parity */
12420 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12421 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
12422 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
12423 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
12424 
12425 /* Bit 0 : Hardware flow control */
12426 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
12427 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
12428 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12429 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12430 
12431 
12432 /* Peripheral: UICR */
12433 /* Description: User Information Configuration Registers */
12434 
12435 /* Register: UICR_NRFFW */
12436 /* Description: Description collection[0]:  Reserved for Nordic firmware design */
12437 
12438 /* Bits 31..0 : Reserved for Nordic firmware design */
12439 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
12440 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
12441 
12442 /* Register: UICR_NRFHW */
12443 /* Description: Description collection[0]:  Reserved for Nordic hardware design */
12444 
12445 /* Bits 31..0 : Reserved for Nordic hardware design */
12446 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
12447 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
12448 
12449 /* Register: UICR_CUSTOMER */
12450 /* Description: Description collection[0]:  Reserved for customer */
12451 
12452 /* Bits 31..0 : Reserved for customer */
12453 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
12454 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
12455 
12456 /* Register: UICR_PSELRESET */
12457 /* Description: Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details) */
12458 
12459 /* Bit 31 : Connection */
12460 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12461 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12462 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
12463 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
12464 
12465 /* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */
12466 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
12467 #define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
12468 
12469 /* Register: UICR_APPROTECT */
12470 /* Description: Access Port protection */
12471 
12472 /* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */
12473 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
12474 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
12475 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
12476 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
12477 
12478 /* Register: UICR_NFCPINS */
12479 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
12480 
12481 /* Bit 0 : Setting of pins dedicated to NFC functionality */
12482 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
12483 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
12484 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
12485 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
12486 
12487 
12488 /* Peripheral: WDT */
12489 /* Description: Watchdog Timer */
12490 
12491 /* Register: WDT_INTENSET */
12492 /* Description: Enable interrupt */
12493 
12494 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
12495 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12496 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12497 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12498 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12499 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
12500 
12501 /* Register: WDT_INTENCLR */
12502 /* Description: Disable interrupt */
12503 
12504 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
12505 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12506 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12507 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12508 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12509 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
12510 
12511 /* Register: WDT_RUNSTATUS */
12512 /* Description: Run status */
12513 
12514 /* Bit 0 : Indicates whether or not the watchdog is running */
12515 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
12516 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
12517 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
12518 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
12519 
12520 /* Register: WDT_REQSTATUS */
12521 /* Description: Request status */
12522 
12523 /* Bit 7 : Request status for RR[7] register */
12524 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
12525 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
12526 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
12527 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
12528 
12529 /* Bit 6 : Request status for RR[6] register */
12530 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
12531 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
12532 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
12533 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
12534 
12535 /* Bit 5 : Request status for RR[5] register */
12536 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
12537 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
12538 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
12539 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
12540 
12541 /* Bit 4 : Request status for RR[4] register */
12542 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
12543 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
12544 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
12545 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
12546 
12547 /* Bit 3 : Request status for RR[3] register */
12548 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
12549 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
12550 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
12551 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
12552 
12553 /* Bit 2 : Request status for RR[2] register */
12554 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
12555 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
12556 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
12557 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
12558 
12559 /* Bit 1 : Request status for RR[1] register */
12560 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
12561 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
12562 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
12563 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
12564 
12565 /* Bit 0 : Request status for RR[0] register */
12566 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
12567 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
12568 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
12569 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
12570 
12571 /* Register: WDT_CRV */
12572 /* Description: Counter reload value */
12573 
12574 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
12575 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
12576 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
12577 
12578 /* Register: WDT_RREN */
12579 /* Description: Enable register for reload request registers */
12580 
12581 /* Bit 7 : Enable or disable RR[7] register */
12582 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
12583 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
12584 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
12585 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
12586 
12587 /* Bit 6 : Enable or disable RR[6] register */
12588 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
12589 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
12590 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
12591 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
12592 
12593 /* Bit 5 : Enable or disable RR[5] register */
12594 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
12595 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
12596 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
12597 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
12598 
12599 /* Bit 4 : Enable or disable RR[4] register */
12600 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
12601 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
12602 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
12603 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
12604 
12605 /* Bit 3 : Enable or disable RR[3] register */
12606 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
12607 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
12608 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
12609 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
12610 
12611 /* Bit 2 : Enable or disable RR[2] register */
12612 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
12613 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
12614 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
12615 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
12616 
12617 /* Bit 1 : Enable or disable RR[1] register */
12618 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
12619 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
12620 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
12621 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
12622 
12623 /* Bit 0 : Enable or disable RR[0] register */
12624 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
12625 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
12626 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
12627 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
12628 
12629 /* Register: WDT_CONFIG */
12630 /* Description: Configuration register */
12631 
12632 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
12633 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
12634 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
12635 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
12636 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
12637 
12638 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
12639 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
12640 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
12641 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
12642 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
12643 
12644 /* Register: WDT_RR */
12645 /* Description: Description collection[0]:  Reload request 0 */
12646 
12647 /* Bits 31..0 : Reload request register */
12648 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
12649 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
12650 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
12651 
12652 
12653 /*lint --flb "Leave library region" */
12654 #endif
12655