1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf52840.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 03. December 2018 34 * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35 * from File 'nrf52840.svd', 36 * last modified on Monday, 03.12.2018 10:18:21 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf52840 47 * @{ 48 */ 49 50 51 #ifndef NRF52840_H 52 #define NRF52840_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83 /* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ 84 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85 RADIO_IRQn = 1, /*!< 1 RADIO */ 86 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 88 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 89 NFCT_IRQn = 5, /*!< 5 NFCT */ 90 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 91 SAADC_IRQn = 7, /*!< 7 SAADC */ 92 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95 RTC0_IRQn = 11, /*!< 11 RTC0 */ 96 TEMP_IRQn = 12, /*!< 12 TEMP */ 97 RNG_IRQn = 13, /*!< 13 RNG */ 98 ECB_IRQn = 14, /*!< 14 ECB */ 99 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100 WDT_IRQn = 16, /*!< 16 WDT */ 101 RTC1_IRQn = 17, /*!< 17 RTC1 */ 102 QDEC_IRQn = 18, /*!< 18 QDEC */ 103 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 104 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 112 PWM0_IRQn = 28, /*!< 28 PWM0 */ 113 PDM_IRQn = 29, /*!< 29 PDM */ 114 MWU_IRQn = 32, /*!< 32 MWU */ 115 PWM1_IRQn = 33, /*!< 33 PWM1 */ 116 PWM2_IRQn = 34, /*!< 34 PWM2 */ 117 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 118 RTC2_IRQn = 36, /*!< 36 RTC2 */ 119 I2S_IRQn = 37, /*!< 37 I2S */ 120 FPU_IRQn = 38, /*!< 38 FPU */ 121 USBD_IRQn = 39, /*!< 39 USBD */ 122 UARTE1_IRQn = 40, /*!< 40 UARTE1 */ 123 QSPI_IRQn = 41, /*!< 41 QSPI */ 124 CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ 125 PWM3_IRQn = 45, /*!< 45 PWM3 */ 126 SPIM3_IRQn = 47 /*!< 47 SPIM3 */ 127 } IRQn_Type; 128 129 130 131 /* =========================================================================================================================== */ 132 /* ================ Processor and Core Peripheral Section ================ */ 133 /* =========================================================================================================================== */ 134 135 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 136 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 137 #define __DSP_PRESENT 0 /*!< DSP present or not */ 138 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 139 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 140 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 141 #define __MPU_PRESENT 1 /*!< MPU present or not */ 142 #define __FPU_PRESENT 1 /*!< FPU present or not */ 143 144 145 /** @} */ /* End of group Configuration_of_CMSIS */ 146 147 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 148 #include "system_nrf52840.h" /*!< nrf52840 System */ 149 150 #ifndef __IM /*!< Fallback for older CMSIS versions */ 151 #define __IM __I 152 #endif 153 #ifndef __OM /*!< Fallback for older CMSIS versions */ 154 #define __OM __O 155 #endif 156 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 157 #define __IOM __IO 158 #endif 159 160 161 /* ======================================== Start of section using anonymous unions ======================================== */ 162 #if defined (__CC_ARM) 163 #pragma push 164 #pragma anon_unions 165 #elif defined (__ICCARM__) 166 #pragma language=extended 167 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 168 #pragma clang diagnostic push 169 #pragma clang diagnostic ignored "-Wc11-extensions" 170 #pragma clang diagnostic ignored "-Wreserved-id-macro" 171 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 172 #pragma clang diagnostic ignored "-Wnested-anon-types" 173 #elif defined (__GNUC__) 174 /* anonymous unions are enabled by default */ 175 #elif defined (__TMS470__) 176 /* anonymous unions are enabled by default */ 177 #elif defined (__TASKING__) 178 #pragma warning 586 179 #elif defined (__CSMC__) 180 /* anonymous unions are enabled by default */ 181 #else 182 #warning Not supported compiler type 183 #endif 184 185 186 /* =========================================================================================================================== */ 187 /* ================ Device Specific Cluster Section ================ */ 188 /* =========================================================================================================================== */ 189 190 191 /** @addtogroup Device_Peripheral_clusters 192 * @{ 193 */ 194 195 196 /** 197 * @brief FICR_INFO [INFO] (Device info) 198 */ 199 typedef struct { 200 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 201 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ 202 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 203 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 204 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 205 __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ 206 } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 207 208 209 /** 210 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 211 */ 212 typedef struct { 213 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 214 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 215 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 216 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 217 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 218 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 219 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 220 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 221 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 222 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 223 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 224 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 225 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 226 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 227 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 228 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 229 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 230 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 231 232 233 /** 234 * @brief FICR_NFC [NFC] (Unspecified) 235 */ 236 typedef struct { 237 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read 238 these values to populate NFCID1_3RD_LAST, 239 NFCID1_2ND_LAST and NFCID1_LAST. */ 240 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read 241 these values to populate NFCID1_3RD_LAST, 242 NFCID1_2ND_LAST and NFCID1_LAST. */ 243 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read 244 these values to populate NFCID1_3RD_LAST, 245 NFCID1_2ND_LAST and NFCID1_LAST. */ 246 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read 247 these values to populate NFCID1_3RD_LAST, 248 NFCID1_2ND_LAST and NFCID1_LAST. */ 249 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 250 251 252 /** 253 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 254 */ 255 typedef struct { 256 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 257 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 258 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 259 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 260 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 261 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 262 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 263 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 264 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 265 266 267 /** 268 * @brief POWER_RAM [RAM] (Unspecified) 269 */ 270 typedef struct { 271 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ 272 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set 273 register */ 274 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear 275 register */ 276 __IM uint32_t RESERVED; 277 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 278 279 280 /** 281 * @brief UART_PSEL [PSEL] (Unspecified) 282 */ 283 typedef struct { 284 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 285 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 286 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 287 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 288 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 289 290 291 /** 292 * @brief UARTE_PSEL [PSEL] (Unspecified) 293 */ 294 typedef struct { 295 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 296 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 297 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 298 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 299 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 300 301 302 /** 303 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 304 */ 305 typedef struct { 306 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 307 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 308 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 309 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 310 311 312 /** 313 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 314 */ 315 typedef struct { 316 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 317 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 318 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 319 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 320 321 322 /** 323 * @brief SPI_PSEL [PSEL] (Unspecified) 324 */ 325 typedef struct { 326 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 327 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 328 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 329 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 330 331 332 /** 333 * @brief SPIM_PSEL [PSEL] (Unspecified) 334 */ 335 typedef struct { 336 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 337 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 338 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 339 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 340 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 341 342 343 /** 344 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 345 */ 346 typedef struct { 347 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 348 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 349 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 350 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 351 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 352 353 354 /** 355 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 356 */ 357 typedef struct { 358 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 359 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 360 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 361 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 362 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 363 364 365 /** 366 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 367 */ 368 typedef struct { 369 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 370 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 371 of SCK and minimum duration CSN must stay 372 high between transactions */ 373 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 374 375 376 /** 377 * @brief SPIS_PSEL [PSEL] (Unspecified) 378 */ 379 typedef struct { 380 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 381 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 382 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 383 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 384 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 385 386 387 /** 388 * @brief SPIS_RXD [RXD] (Unspecified) 389 */ 390 typedef struct { 391 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 392 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 393 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 394 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 395 396 397 /** 398 * @brief SPIS_TXD [TXD] (Unspecified) 399 */ 400 typedef struct { 401 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 402 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 403 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 404 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 405 406 407 /** 408 * @brief TWI_PSEL [PSEL] (Unspecified) 409 */ 410 typedef struct { 411 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 412 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 413 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 414 415 416 /** 417 * @brief TWIM_PSEL [PSEL] (Unspecified) 418 */ 419 typedef struct { 420 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 421 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 422 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 423 424 425 /** 426 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 427 */ 428 typedef struct { 429 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 430 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 431 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 432 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 433 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 434 435 436 /** 437 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 438 */ 439 typedef struct { 440 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 441 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 442 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 443 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 444 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 445 446 447 /** 448 * @brief TWIS_PSEL [PSEL] (Unspecified) 449 */ 450 typedef struct { 451 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 452 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 453 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 454 455 456 /** 457 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 458 */ 459 typedef struct { 460 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 461 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 462 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 463 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 464 465 466 /** 467 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 468 */ 469 typedef struct { 470 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 471 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 472 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 473 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 474 475 476 /** 477 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 478 */ 479 typedef struct { 480 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 481 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 482 483 484 /** 485 * @brief NFCT_TXD [TXD] (Unspecified) 486 */ 487 typedef struct { 488 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 489 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 490 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 491 492 493 /** 494 * @brief NFCT_RXD [RXD] (Unspecified) 495 */ 496 typedef struct { 497 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 498 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 499 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 500 501 502 /** 503 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 504 */ 505 typedef struct { 506 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal 507 or above CH[n].LIMIT.HIGH */ 508 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal 509 or below CH[n].LIMIT.LOW */ 510 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 511 512 513 /** 514 * @brief SAADC_CH [CH] (Unspecified) 515 */ 516 typedef struct { 517 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection 518 for CH[n] */ 519 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection 520 for CH[n] */ 521 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for 522 CH[n] */ 523 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event 524 monitoring of a channel */ 525 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 526 527 528 /** 529 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 530 */ 531 typedef struct { 532 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 533 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written 534 to output RAM buffer */ 535 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM 536 buffer since the previous START task */ 537 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 538 539 540 /** 541 * @brief QDEC_PSEL [PSEL] (Unspecified) 542 */ 543 typedef struct { 544 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 545 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 546 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 547 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 548 549 550 /** 551 * @brief PWM_SEQ [SEQ] (Unspecified) 552 */ 553 typedef struct { 554 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in 555 RAM of this sequence */ 556 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty 557 cycles) in this sequence */ 558 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional 559 PWM periods between samples loaded into 560 compare register */ 561 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the 562 sequence */ 563 __IM uint32_t RESERVED[4]; 564 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 565 566 567 /** 568 * @brief PWM_PSEL [PSEL] (Unspecified) 569 */ 570 typedef struct { 571 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select 572 for PWM channel n */ 573 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 574 575 576 /** 577 * @brief PDM_PSEL [PSEL] (Unspecified) 578 */ 579 typedef struct { 580 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 581 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 582 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 583 584 585 /** 586 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 587 */ 588 typedef struct { 589 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 590 EasyDMA */ 591 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 592 mode */ 593 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 594 595 596 /** 597 * @brief ACL_ACL [ACL] (Unspecified) 598 */ 599 typedef struct { 600 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned 601 start address of region n to protect */ 602 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect 603 counting from address ACL[n].ADDR. Write 604 '0' as no effect. */ 605 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for 606 region n as defined by start address ACL[n].ADDR 607 and size ACL[n].SIZE */ 608 __IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ 609 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 610 611 612 /** 613 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 614 */ 615 typedef struct { 616 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group 617 n */ 618 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group 619 n */ 620 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 621 622 623 /** 624 * @brief PPI_CH [CH] (PPI Channel) 625 */ 626 typedef struct { 627 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ 628 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ 629 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 630 631 632 /** 633 * @brief PPI_FORK [FORK] (Fork) 634 */ 635 typedef struct { 636 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ 637 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 638 639 640 /** 641 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) 642 */ 643 typedef struct { 644 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region 645 n detected */ 646 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region 647 n detected */ 648 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 649 650 651 /** 652 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) 653 */ 654 typedef struct { 655 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral 656 region n detected */ 657 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral 658 region n detected */ 659 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 660 661 662 /** 663 * @brief MWU_PERREGION [PERREGION] (Unspecified) 664 */ 665 typedef struct { 666 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt 667 in region n, write access detected while 668 corresponding subregion was enabled for 669 watching */ 670 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt 671 in region n, read access detected while 672 corresponding subregion was enabled for 673 watching */ 674 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 675 676 677 /** 678 * @brief MWU_REGION [REGION] (Unspecified) 679 */ 680 typedef struct { 681 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region 682 n */ 683 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region 684 n */ 685 __IM uint32_t RESERVED[2]; 686 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 687 688 689 /** 690 * @brief MWU_PREGION [PREGION] (Unspecified) 691 */ 692 typedef struct { 693 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ 694 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ 695 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region 696 n */ 697 __IM uint32_t RESERVED; 698 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 699 700 701 /** 702 * @brief I2S_CONFIG [CONFIG] (Unspecified) 703 */ 704 typedef struct { 705 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 706 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 707 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 708 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 709 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 710 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 711 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 712 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 713 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 714 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 715 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 716 717 718 /** 719 * @brief I2S_RXD [RXD] (Unspecified) 720 */ 721 typedef struct { 722 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 723 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 724 725 726 /** 727 * @brief I2S_TXD [TXD] (Unspecified) 728 */ 729 typedef struct { 730 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 731 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 732 733 734 /** 735 * @brief I2S_RXTXD [RXTXD] (Unspecified) 736 */ 737 typedef struct { 738 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 739 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 740 741 742 /** 743 * @brief I2S_PSEL [PSEL] (Unspecified) 744 */ 745 typedef struct { 746 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 747 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 748 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 749 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 750 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 751 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 752 753 754 /** 755 * @brief USBD_HALTED [HALTED] (Unspecified) 756 */ 757 typedef struct { 758 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted 759 status. Can be used as is as response to 760 a GetStatus() request to endpoint. */ 761 __IM uint32_t RESERVED; 762 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted 763 status. Can be used as is as response to 764 a GetStatus() request to endpoint. */ 765 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 766 767 768 /** 769 * @brief USBD_SIZE [SIZE] (Unspecified) 770 */ 771 typedef struct { 772 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received 773 last in the data stage of this OUT endpoint */ 774 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 775 data endpoint */ 776 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 777 778 779 /** 780 * @brief USBD_EPIN [EPIN] (Unspecified) 781 */ 782 typedef struct { 783 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ 784 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes 785 to transfer */ 786 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred 787 in the last transaction */ 788 __IM uint32_t RESERVED[2]; 789 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 790 791 792 /** 793 * @brief USBD_ISOIN [ISOIN] (Unspecified) 794 */ 795 typedef struct { 796 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 797 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 798 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 799 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 800 801 802 /** 803 * @brief USBD_EPOUT [EPOUT] (Unspecified) 804 */ 805 typedef struct { 806 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ 807 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes 808 to transfer */ 809 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred 810 in the last transaction */ 811 __IM uint32_t RESERVED[2]; 812 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 813 814 815 /** 816 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 817 */ 818 typedef struct { 819 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 820 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 821 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 822 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 823 824 825 /** 826 * @brief QSPI_READ [READ] (Unspecified) 827 */ 828 typedef struct { 829 __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 830 __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 831 __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 832 } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 833 834 835 /** 836 * @brief QSPI_WRITE [WRITE] (Unspecified) 837 */ 838 typedef struct { 839 __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 840 __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 841 __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 842 } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 843 844 845 /** 846 * @brief QSPI_ERASE [ERASE] (Unspecified) 847 */ 848 typedef struct { 849 __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 850 __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 851 } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 852 853 854 /** 855 * @brief QSPI_PSEL [PSEL] (Unspecified) 856 */ 857 typedef struct { 858 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 859 __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 860 __IM uint32_t RESERVED; 861 __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 862 __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 863 __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ 864 __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ 865 } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 866 867 868 /** @} */ /* End of group Device_Peripheral_clusters */ 869 870 871 /* =========================================================================================================================== */ 872 /* ================ Device Specific Peripheral Section ================ */ 873 /* =========================================================================================================================== */ 874 875 876 /** @addtogroup Device_Peripheral_peripherals 877 * @{ 878 */ 879 880 881 882 /* =========================================================================================================================== */ 883 /* ================ FICR ================ */ 884 /* =========================================================================================================================== */ 885 886 887 /** 888 * @brief Factory information configuration registers (FICR) 889 */ 890 891 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 892 __IM uint32_t RESERVED[4]; 893 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 894 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 895 __IM uint32_t RESERVED1[18]; 896 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ 897 __IM uint32_t RESERVED2[6]; 898 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word 899 n */ 900 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word 901 n */ 902 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 903 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ 904 __IM uint32_t RESERVED3[21]; 905 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 906 __IM uint32_t RESERVED4[140]; 907 __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature 908 n */ 909 __IM uint32_t RESERVED5[42]; 910 __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 911 coefficients */ 912 __IM uint32_t RESERVED6[2]; 913 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 914 __IM uint32_t RESERVED7[488]; 915 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 916 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 917 918 919 920 /* =========================================================================================================================== */ 921 /* ================ UICR ================ */ 922 /* =========================================================================================================================== */ 923 924 925 /** 926 * @brief User information configuration registers (UICR) 927 */ 928 929 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 930 __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 931 __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 932 __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 933 __IM uint32_t RESERVED; 934 __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 935 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic 936 firmware design */ 937 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic 938 hardware design */ 939 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ 940 __IM uint32_t RESERVED1[64]; 941 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET 942 function */ 943 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 944 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 945 NFC antenna or GPIO */ 946 __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 947 __IM uint32_t RESERVED2[60]; 948 __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply 949 voltage in high voltage mode */ 950 } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 951 952 953 954 /* =========================================================================================================================== */ 955 /* ================ CLOCK ================ */ 956 /* =========================================================================================================================== */ 957 958 959 /** 960 * @brief Clock control (CLOCK) 961 */ 962 963 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 964 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 965 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 966 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 967 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 968 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 969 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 970 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 971 __IM uint32_t RESERVED[57]; 972 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 973 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 974 __IM uint32_t RESERVED1; 975 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 976 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 977 __IM uint32_t RESERVED2[5]; 978 __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 979 to process new tasks */ 980 __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 981 to process new tasks */ 982 __IM uint32_t RESERVED3[117]; 983 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 984 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 985 __IM uint32_t RESERVED4[63]; 986 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 987 triggered */ 988 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 989 __IM uint32_t RESERVED5; 990 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 991 triggered */ 992 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 993 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 994 task was triggered */ 995 __IM uint32_t RESERVED6[62]; 996 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 997 __IM uint32_t RESERVED7[3]; 998 __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 999 the TASKS_HFCLKSTART task. */ 1000 __IM uint32_t RESERVED8[3]; 1001 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 1002 __IM uint32_t RESERVED9[8]; 1003 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ 1004 __IM uint32_t RESERVED10[21]; 1005 __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ 1006 } NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ 1007 1008 1009 1010 /* =========================================================================================================================== */ 1011 /* ================ POWER ================ */ 1012 /* =========================================================================================================================== */ 1013 1014 1015 /** 1016 * @brief Power control (POWER) 1017 */ 1018 1019 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 1020 __IM uint32_t RESERVED[30]; 1021 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 1022 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 1023 __IM uint32_t RESERVED1[34]; 1024 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1025 __IM uint32_t RESERVED2[2]; 1026 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1027 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1028 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 1029 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 1030 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 1031 __IM uint32_t RESERVED3[119]; 1032 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1033 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1034 __IM uint32_t RESERVED4[61]; 1035 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1036 __IM uint32_t RESERVED5[9]; 1037 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 1038 __IM uint32_t RESERVED6[3]; 1039 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 1040 __IM uint32_t RESERVED7[49]; 1041 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1042 __IM uint32_t RESERVED8[3]; 1043 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1044 __IM uint32_t RESERVED9[2]; 1045 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 1046 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 1047 __IM uint32_t RESERVED10[21]; 1048 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ 1049 __IM uint32_t RESERVED11; 1050 __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ 1051 __IM uint32_t RESERVED12[47]; 1052 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 1053 __IM uint32_t RESERVED13[175]; 1054 __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ 1055 } NRF_POWER_Type; /*!< Size = 2448 (0x990) */ 1056 1057 1058 1059 /* =========================================================================================================================== */ 1060 /* ================ RADIO ================ */ 1061 /* =========================================================================================================================== */ 1062 1063 1064 /** 1065 * @brief 2.4 GHz radio (RADIO) 1066 */ 1067 1068 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 1069 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 1070 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 1071 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 1072 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 1073 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 1074 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 1075 the receive signal strength */ 1076 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 1077 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 1078 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 1079 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 1080 802.15.4 mode */ 1081 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 1082 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 1083 802.15.4 mode */ 1084 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 1085 __IM uint32_t RESERVED[51]; 1086 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 1087 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 1088 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 1089 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 1090 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 1091 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 1092 packet */ 1093 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 1094 received packet */ 1095 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 1096 __IM uint32_t RESERVED1[2]; 1097 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 1098 __IM uint32_t RESERVED2; 1099 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 1100 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 1101 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 1102 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 1103 ED sample is ready for readout from the 1104 RADIO.EDSAMPLE register. */ 1105 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 1106 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 1107 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 1108 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 1109 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 1110 from Ble_LR125Kbit to Ble_LR500Kbit. */ 1111 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 1112 TX path */ 1113 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 1114 RX path */ 1115 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 1116 __IM uint32_t RESERVED3[3]; 1117 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and 1118 BleIeee802154_250Kbit modes when last bit 1119 is sent on air. */ 1120 __IM uint32_t RESERVED4[36]; 1121 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1122 __IM uint32_t RESERVED5[64]; 1123 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1124 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1125 __IM uint32_t RESERVED6[61]; 1126 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 1127 __IM uint32_t RESERVED7; 1128 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 1129 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 1130 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 1131 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 1132 __IM uint32_t RESERVED8[59]; 1133 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 1134 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 1135 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 1136 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 1137 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 1138 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 1139 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 1140 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 1141 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 1142 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 1143 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 1144 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 1145 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 1146 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 1147 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 1148 __IM uint32_t RESERVED9; 1149 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 1150 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 1151 __IM uint32_t RESERVED10; 1152 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 1153 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 1154 __IM uint32_t RESERVED11[2]; 1155 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 1156 __IM uint32_t RESERVED12[39]; 1157 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base 1158 segment n */ 1159 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix 1160 n */ 1161 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 1162 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 1163 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 1164 __IM uint32_t RESERVED13; 1165 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 1166 __IM uint32_t RESERVED14[3]; 1167 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 1168 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 1169 __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 1170 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 1171 __IM uint32_t RESERVED15[611]; 1172 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 1173 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 1174 1175 1176 1177 /* =========================================================================================================================== */ 1178 /* ================ UART0 ================ */ 1179 /* =========================================================================================================================== */ 1180 1181 1182 /** 1183 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1184 */ 1185 1186 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1187 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1188 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1189 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1190 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1191 __IM uint32_t RESERVED[3]; 1192 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1193 __IM uint32_t RESERVED1[56]; 1194 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1195 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1196 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1197 __IM uint32_t RESERVED2[4]; 1198 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1199 __IM uint32_t RESERVED3; 1200 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1201 __IM uint32_t RESERVED4[7]; 1202 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1203 __IM uint32_t RESERVED5[46]; 1204 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1205 __IM uint32_t RESERVED6[64]; 1206 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1207 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1208 __IM uint32_t RESERVED7[93]; 1209 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1210 __IM uint32_t RESERVED8[31]; 1211 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1212 __IM uint32_t RESERVED9; 1213 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1214 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1215 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1216 __IM uint32_t RESERVED10; 1217 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1218 selected. */ 1219 __IM uint32_t RESERVED11[17]; 1220 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1221 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1222 1223 1224 1225 /* =========================================================================================================================== */ 1226 /* ================ UARTE0 ================ */ 1227 /* =========================================================================================================================== */ 1228 1229 1230 /** 1231 * @brief UART with EasyDMA 0 (UARTE0) 1232 */ 1233 1234 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1235 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1236 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1237 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1238 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1239 __IM uint32_t RESERVED[7]; 1240 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1241 __IM uint32_t RESERVED1[52]; 1242 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1243 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1244 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1245 transferred to Data RAM) */ 1246 __IM uint32_t RESERVED2; 1247 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1248 __IM uint32_t RESERVED3[2]; 1249 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1250 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1251 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1252 __IM uint32_t RESERVED4[7]; 1253 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1254 __IM uint32_t RESERVED5; 1255 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1256 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1257 __IM uint32_t RESERVED6; 1258 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1259 __IM uint32_t RESERVED7[41]; 1260 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1261 __IM uint32_t RESERVED8[63]; 1262 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1263 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1264 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1265 __IM uint32_t RESERVED9[93]; 1266 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1267 one to clear. */ 1268 __IM uint32_t RESERVED10[31]; 1269 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1270 __IM uint32_t RESERVED11; 1271 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1272 __IM uint32_t RESERVED12[3]; 1273 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1274 selected. */ 1275 __IM uint32_t RESERVED13[3]; 1276 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1277 __IM uint32_t RESERVED14; 1278 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1279 __IM uint32_t RESERVED15[7]; 1280 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1281 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1282 1283 1284 1285 /* =========================================================================================================================== */ 1286 /* ================ SPI0 ================ */ 1287 /* =========================================================================================================================== */ 1288 1289 1290 /** 1291 * @brief Serial Peripheral Interface 0 (SPI0) 1292 */ 1293 1294 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1295 __IM uint32_t RESERVED[66]; 1296 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1297 __IM uint32_t RESERVED1[126]; 1298 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1299 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1300 __IM uint32_t RESERVED2[125]; 1301 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1302 __IM uint32_t RESERVED3; 1303 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1304 __IM uint32_t RESERVED4; 1305 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1306 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1307 __IM uint32_t RESERVED5; 1308 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1309 source selected. */ 1310 __IM uint32_t RESERVED6[11]; 1311 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1312 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1313 1314 1315 1316 /* =========================================================================================================================== */ 1317 /* ================ SPIM0 ================ */ 1318 /* =========================================================================================================================== */ 1319 1320 1321 /** 1322 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1323 */ 1324 1325 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1326 __IM uint32_t RESERVED[4]; 1327 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1328 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1329 __IM uint32_t RESERVED1; 1330 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1331 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1332 __IM uint32_t RESERVED2[56]; 1333 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1334 __IM uint32_t RESERVED3[2]; 1335 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1336 __IM uint32_t RESERVED4; 1337 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1338 __IM uint32_t RESERVED5; 1339 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1340 __IM uint32_t RESERVED6[10]; 1341 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1342 __IM uint32_t RESERVED7[44]; 1343 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1344 __IM uint32_t RESERVED8[64]; 1345 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1346 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1347 __IM uint32_t RESERVED9[61]; 1348 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1349 in this register is set to STALL by hardware 1350 whenever a stall occurres and can be cleared 1351 (set to NOSTALL) by the CPU. */ 1352 __IM uint32_t RESERVED10[63]; 1353 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1354 __IM uint32_t RESERVED11; 1355 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1356 __IM uint32_t RESERVED12[3]; 1357 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1358 source selected. */ 1359 __IM uint32_t RESERVED13[3]; 1360 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1361 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1362 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1363 __IM uint32_t RESERVED14[2]; 1364 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1365 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1366 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1367 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1368 __IM uint32_t RESERVED15[19]; 1369 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1370 been transmitted in the case when RXD.MAXCNT 1371 is greater than TXD.MAXCNT */ 1372 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1373 1374 1375 1376 /* =========================================================================================================================== */ 1377 /* ================ SPIS0 ================ */ 1378 /* =========================================================================================================================== */ 1379 1380 1381 /** 1382 * @brief SPI Slave 0 (SPIS0) 1383 */ 1384 1385 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1386 __IM uint32_t RESERVED[9]; 1387 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1388 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1389 to acquire it */ 1390 __IM uint32_t RESERVED1[54]; 1391 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1392 __IM uint32_t RESERVED2[2]; 1393 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1394 __IM uint32_t RESERVED3[5]; 1395 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1396 __IM uint32_t RESERVED4[53]; 1397 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1398 __IM uint32_t RESERVED5[64]; 1399 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1400 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1401 __IM uint32_t RESERVED6[61]; 1402 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1403 __IM uint32_t RESERVED7[15]; 1404 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1405 __IM uint32_t RESERVED8[47]; 1406 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1407 __IM uint32_t RESERVED9; 1408 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1409 __IM uint32_t RESERVED10[7]; 1410 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1411 __IM uint32_t RESERVED11; 1412 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1413 __IM uint32_t RESERVED12; 1414 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1415 __IM uint32_t RESERVED13; 1416 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1417 of an ignored transaction. */ 1418 __IM uint32_t RESERVED14[24]; 1419 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1420 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1421 1422 1423 1424 /* =========================================================================================================================== */ 1425 /* ================ TWI0 ================ */ 1426 /* =========================================================================================================================== */ 1427 1428 1429 /** 1430 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1431 */ 1432 1433 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1434 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1435 __IM uint32_t RESERVED; 1436 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1437 __IM uint32_t RESERVED1[2]; 1438 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1439 __IM uint32_t RESERVED2; 1440 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1441 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1442 __IM uint32_t RESERVED3[56]; 1443 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1444 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1445 __IM uint32_t RESERVED4[4]; 1446 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1447 __IM uint32_t RESERVED5; 1448 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1449 __IM uint32_t RESERVED6[4]; 1450 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1451 that is sent or received */ 1452 __IM uint32_t RESERVED7[3]; 1453 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1454 __IM uint32_t RESERVED8[45]; 1455 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1456 __IM uint32_t RESERVED9[64]; 1457 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1458 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1459 __IM uint32_t RESERVED10[110]; 1460 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1461 __IM uint32_t RESERVED11[14]; 1462 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1463 __IM uint32_t RESERVED12; 1464 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1465 __IM uint32_t RESERVED13[2]; 1466 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1467 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1468 __IM uint32_t RESERVED14; 1469 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1470 source selected. */ 1471 __IM uint32_t RESERVED15[24]; 1472 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1473 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1474 1475 1476 1477 /* =========================================================================================================================== */ 1478 /* ================ TWIM0 ================ */ 1479 /* =========================================================================================================================== */ 1480 1481 1482 /** 1483 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1484 */ 1485 1486 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1487 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1488 __IM uint32_t RESERVED; 1489 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1490 __IM uint32_t RESERVED1[2]; 1491 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1492 TWI master is not suspended. */ 1493 __IM uint32_t RESERVED2; 1494 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1495 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1496 __IM uint32_t RESERVED3[56]; 1497 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1498 __IM uint32_t RESERVED4[7]; 1499 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1500 __IM uint32_t RESERVED5[8]; 1501 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1502 task has been issued, TWI traffic is now 1503 suspended. */ 1504 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1505 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1506 __IM uint32_t RESERVED6[2]; 1507 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1508 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1509 byte */ 1510 __IM uint32_t RESERVED7[39]; 1511 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1512 __IM uint32_t RESERVED8[63]; 1513 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1514 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1515 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1516 __IM uint32_t RESERVED9[110]; 1517 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1518 __IM uint32_t RESERVED10[14]; 1519 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1520 __IM uint32_t RESERVED11; 1521 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1522 __IM uint32_t RESERVED12[5]; 1523 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1524 source selected. */ 1525 __IM uint32_t RESERVED13[3]; 1526 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1527 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1528 __IM uint32_t RESERVED14[13]; 1529 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1530 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1531 1532 1533 1534 /* =========================================================================================================================== */ 1535 /* ================ TWIS0 ================ */ 1536 /* =========================================================================================================================== */ 1537 1538 1539 /** 1540 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1541 */ 1542 1543 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1544 __IM uint32_t RESERVED[5]; 1545 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1546 __IM uint32_t RESERVED1; 1547 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1548 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1549 __IM uint32_t RESERVED2[3]; 1550 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1551 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1552 __IM uint32_t RESERVED3[51]; 1553 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1554 __IM uint32_t RESERVED4[7]; 1555 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1556 __IM uint32_t RESERVED5[9]; 1557 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1558 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1559 __IM uint32_t RESERVED6[4]; 1560 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1561 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1562 __IM uint32_t RESERVED7[37]; 1563 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1564 __IM uint32_t RESERVED8[63]; 1565 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1566 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1567 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1568 __IM uint32_t RESERVED9[113]; 1569 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1570 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1571 a match */ 1572 __IM uint32_t RESERVED10[10]; 1573 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1574 __IM uint32_t RESERVED11; 1575 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1576 __IM uint32_t RESERVED12[9]; 1577 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1578 __IM uint32_t RESERVED13; 1579 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1580 __IM uint32_t RESERVED14[14]; 1581 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address 1582 n */ 1583 __IM uint32_t RESERVED15; 1584 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1585 mechanism */ 1586 __IM uint32_t RESERVED16[10]; 1587 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1588 of an over-read of the transmit buffer. */ 1589 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1590 1591 1592 1593 /* =========================================================================================================================== */ 1594 /* ================ NFCT ================ */ 1595 /* =========================================================================================================================== */ 1596 1597 1598 /** 1599 * @brief NFC-A compatible radio (NFCT) 1600 */ 1601 1602 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1603 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 1604 frames, change state to activated */ 1605 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 1606 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1607 sense mode */ 1608 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 1609 state to transmit */ 1610 __IM uint32_t RESERVED[3]; 1611 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1612 __IM uint32_t RESERVED1; 1613 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1614 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1615 __IM uint32_t RESERVED2[53]; 1616 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 1617 frames */ 1618 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1619 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1620 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1621 frame */ 1622 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1623 symbol of a frame */ 1624 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1625 frame */ 1626 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 1627 and transferred to RAM, and EasyDMA has 1628 ended accessing the RX buffer */ 1629 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1630 contains details on the source of the error. */ 1631 __IM uint32_t RESERVED3[2]; 1632 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1633 register contains details on the source 1634 of the error. */ 1635 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1636 in Data RAM full. */ 1637 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1638 has ended accessing the TX buffer */ 1639 __IM uint32_t RESERVED4; 1640 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1641 __IM uint32_t RESERVED5[3]; 1642 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 1643 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 1644 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1645 __IM uint32_t RESERVED6[43]; 1646 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1647 __IM uint32_t RESERVED7[63]; 1648 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1649 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1650 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1651 __IM uint32_t RESERVED8[62]; 1652 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1653 __IM uint32_t RESERVED9; 1654 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1655 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ 1656 __IM uint32_t RESERVED10[3]; 1657 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 1658 __IM uint32_t RESERVED11[6]; 1659 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1660 __IM uint32_t RESERVED12[49]; 1661 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1662 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1663 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1664 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1665 Data RAM */ 1666 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 1667 data storage each */ 1668 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1669 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1670 __IM uint32_t RESERVED13[26]; 1671 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1672 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1673 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1674 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 1675 This setting must be done before the NFCT 1676 peripheral is enabled. */ 1677 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1678 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1679 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1680 1681 1682 1683 /* =========================================================================================================================== */ 1684 /* ================ GPIOTE ================ */ 1685 /* =========================================================================================================================== */ 1686 1687 1688 /** 1689 * @brief GPIO Tasks and Events (GPIOTE) 1690 */ 1691 1692 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1693 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to 1694 pin specified in CONFIG[n].PSEL. Action 1695 on pin is configured in CONFIG[n].POLARITY. */ 1696 __IM uint32_t RESERVED[4]; 1697 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to 1698 pin specified in CONFIG[n].PSEL. Action 1699 on pin is to set it high. */ 1700 __IM uint32_t RESERVED1[4]; 1701 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to 1702 pin specified in CONFIG[n].PSEL. Action 1703 on pin is to set it low. */ 1704 __IM uint32_t RESERVED2[32]; 1705 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from 1706 pin specified in CONFIG[n].PSEL */ 1707 __IM uint32_t RESERVED3[23]; 1708 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1709 with SENSE mechanism enabled */ 1710 __IM uint32_t RESERVED4[97]; 1711 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1712 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1713 __IM uint32_t RESERVED5[129]; 1714 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for 1715 OUT[n], SET[n] and CLR[n] tasks and IN[n] 1716 event */ 1717 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1718 1719 1720 1721 /* =========================================================================================================================== */ 1722 /* ================ SAADC ================ */ 1723 /* =========================================================================================================================== */ 1724 1725 1726 /** 1727 * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) 1728 */ 1729 1730 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1731 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer 1732 in RAM */ 1733 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ 1734 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ 1735 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1736 __IM uint32_t RESERVED[60]; 1737 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ 1738 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ 1739 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1740 on the configuration, multiple conversions 1741 might be needed for a result to be transferred 1742 to RAM. */ 1743 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ 1744 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1745 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ 1746 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1747 __IM uint32_t RESERVED1[106]; 1748 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1749 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1750 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1751 __IM uint32_t RESERVED2[61]; 1752 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1753 __IM uint32_t RESERVED3[63]; 1754 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ 1755 __IM uint32_t RESERVED4[3]; 1756 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1757 __IM uint32_t RESERVED5[24]; 1758 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1759 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is 1760 applied before averaging, thus for high 1761 OVERSAMPLE a higher RESOLUTION should be 1762 used. */ 1763 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1764 __IM uint32_t RESERVED6[12]; 1765 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1766 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1767 1768 1769 1770 /* =========================================================================================================================== */ 1771 /* ================ TIMER0 ================ */ 1772 /* =========================================================================================================================== */ 1773 1774 1775 /** 1776 * @brief Timer/Counter 0 (TIMER0) 1777 */ 1778 1779 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1780 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1781 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1782 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1783 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1784 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1785 __IM uint32_t RESERVED[11]; 1786 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value 1787 to CC[n] register */ 1788 __IM uint32_t RESERVED1[58]; 1789 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1790 match */ 1791 __IM uint32_t RESERVED2[42]; 1792 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1793 __IM uint32_t RESERVED3[64]; 1794 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1795 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1796 __IM uint32_t RESERVED4[126]; 1797 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1798 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1799 __IM uint32_t RESERVED5; 1800 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1801 __IM uint32_t RESERVED6[11]; 1802 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register 1803 n */ 1804 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1805 1806 1807 1808 /* =========================================================================================================================== */ 1809 /* ================ RTC0 ================ */ 1810 /* =========================================================================================================================== */ 1811 1812 1813 /** 1814 * @brief Real time counter 0 (RTC0) 1815 */ 1816 1817 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1818 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1819 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1820 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1821 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1822 __IM uint32_t RESERVED[60]; 1823 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1824 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1825 __IM uint32_t RESERVED1[14]; 1826 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1827 match */ 1828 __IM uint32_t RESERVED2[109]; 1829 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1830 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1831 __IM uint32_t RESERVED3[13]; 1832 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1833 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1834 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1835 __IM uint32_t RESERVED4[110]; 1836 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1837 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1838 t be written when RTC is stopped */ 1839 __IM uint32_t RESERVED5[13]; 1840 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ 1841 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1842 1843 1844 1845 /* =========================================================================================================================== */ 1846 /* ================ TEMP ================ */ 1847 /* =========================================================================================================================== */ 1848 1849 1850 /** 1851 * @brief Temperature Sensor (TEMP) 1852 */ 1853 1854 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1855 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1856 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1857 __IM uint32_t RESERVED[62]; 1858 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1859 __IM uint32_t RESERVED1[128]; 1860 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1861 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1862 __IM uint32_t RESERVED2[127]; 1863 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1864 __IM uint32_t RESERVED3[5]; 1865 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1866 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1867 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1868 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1869 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1870 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1871 __IM uint32_t RESERVED4[2]; 1872 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1873 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1874 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1875 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1876 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1877 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1878 __IM uint32_t RESERVED5[2]; 1879 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1880 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1881 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1882 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1883 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1884 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1885 1886 1887 1888 /* =========================================================================================================================== */ 1889 /* ================ RNG ================ */ 1890 /* =========================================================================================================================== */ 1891 1892 1893 /** 1894 * @brief Random Number Generator (RNG) 1895 */ 1896 1897 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1898 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1899 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1900 __IM uint32_t RESERVED[62]; 1901 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1902 written to the VALUE register */ 1903 __IM uint32_t RESERVED1[63]; 1904 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1905 __IM uint32_t RESERVED2[64]; 1906 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1907 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1908 __IM uint32_t RESERVED3[126]; 1909 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1910 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1911 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1912 1913 1914 1915 /* =========================================================================================================================== */ 1916 /* ================ ECB ================ */ 1917 /* =========================================================================================================================== */ 1918 1919 1920 /** 1921 * @brief AES ECB Mode Encryption (ECB) 1922 */ 1923 1924 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1925 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1926 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1927 __IM uint32_t RESERVED[62]; 1928 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1929 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1930 task or due to an error */ 1931 __IM uint32_t RESERVED1[127]; 1932 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1933 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1934 __IM uint32_t RESERVED2[126]; 1935 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1936 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1937 1938 1939 1940 /* =========================================================================================================================== */ 1941 /* ================ AAR ================ */ 1942 /* =========================================================================================================================== */ 1943 1944 1945 /** 1946 * @brief Accelerated Address Resolver (AAR) 1947 */ 1948 1949 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1950 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1951 in the IRK data structure */ 1952 __IM uint32_t RESERVED; 1953 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1954 __IM uint32_t RESERVED1[61]; 1955 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1956 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1957 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1958 __IM uint32_t RESERVED2[126]; 1959 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1960 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1961 __IM uint32_t RESERVED3[61]; 1962 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1963 __IM uint32_t RESERVED4[63]; 1964 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1965 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1966 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1967 __IM uint32_t RESERVED5; 1968 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1969 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1970 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1971 1972 1973 1974 /* =========================================================================================================================== */ 1975 /* ================ CCM ================ */ 1976 /* =========================================================================================================================== */ 1977 1978 1979 /** 1980 * @brief AES CCM Mode Encryption (CCM) 1981 */ 1982 1983 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1984 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1985 will stop by itself when completed. */ 1986 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1987 stop by itself when completed. */ 1988 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1989 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1990 the contents of the RATEOVERRIDE register 1991 for any ongoing encryption/decryption */ 1992 __IM uint32_t RESERVED[60]; 1993 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1994 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1995 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1996 __IM uint32_t RESERVED1[61]; 1997 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1998 __IM uint32_t RESERVED2[64]; 1999 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2000 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2001 __IM uint32_t RESERVED3[61]; 2002 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 2003 __IM uint32_t RESERVED4[63]; 2004 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 2005 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 2006 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 2007 NONCE vector */ 2008 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 2009 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 2010 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2011 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH 2012 = Extended. */ 2013 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 2014 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 2015 2016 2017 2018 /* =========================================================================================================================== */ 2019 /* ================ WDT ================ */ 2020 /* =========================================================================================================================== */ 2021 2022 2023 /** 2024 * @brief Watchdog Timer (WDT) 2025 */ 2026 2027 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 2028 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2029 __IM uint32_t RESERVED[63]; 2030 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2031 __IM uint32_t RESERVED1[128]; 2032 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2033 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2034 __IM uint32_t RESERVED2[61]; 2035 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2036 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2037 __IM uint32_t RESERVED3[63]; 2038 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2039 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2040 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2041 __IM uint32_t RESERVED4[60]; 2042 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ 2043 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2044 2045 2046 2047 /* =========================================================================================================================== */ 2048 /* ================ QDEC ================ */ 2049 /* =========================================================================================================================== */ 2050 2051 2052 /** 2053 * @brief Quadrature Decoder (QDEC) 2054 */ 2055 2056 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 2057 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2058 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2059 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2060 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2061 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2062 __IM uint32_t RESERVED[59]; 2063 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2064 written to the SAMPLE register */ 2065 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2066 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2067 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2068 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2069 __IM uint32_t RESERVED1[59]; 2070 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2071 __IM uint32_t RESERVED2[64]; 2072 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2073 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2074 __IM uint32_t RESERVED3[125]; 2075 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2076 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2077 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2078 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2079 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2080 and DBLRDY events can be generated */ 2081 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2082 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2083 READCLRACC or RDCLRACC task */ 2084 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2085 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2086 __IM uint32_t RESERVED4[5]; 2087 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2088 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2089 double transitions */ 2090 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2091 or RDCLRDBL task */ 2092 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2093 2094 2095 2096 /* =========================================================================================================================== */ 2097 /* ================ COMP ================ */ 2098 /* =========================================================================================================================== */ 2099 2100 2101 /** 2102 * @brief Comparator (COMP) 2103 */ 2104 2105 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 2106 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2107 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2108 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2109 __IM uint32_t RESERVED[61]; 2110 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2111 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2112 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2113 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2114 __IM uint32_t RESERVED1[60]; 2115 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2116 __IM uint32_t RESERVED2[63]; 2117 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2118 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2119 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2120 __IM uint32_t RESERVED3[61]; 2121 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2122 __IM uint32_t RESERVED4[63]; 2123 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2124 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2125 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2126 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2127 __IM uint32_t RESERVED5[8]; 2128 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2129 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2130 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2131 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 2132 2133 2134 2135 /* =========================================================================================================================== */ 2136 /* ================ LPCOMP ================ */ 2137 /* =========================================================================================================================== */ 2138 2139 2140 /** 2141 * @brief Low Power Comparator (LPCOMP) 2142 */ 2143 2144 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 2145 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2146 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2147 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2148 __IM uint32_t RESERVED[61]; 2149 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2150 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2151 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2152 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2153 __IM uint32_t RESERVED1[60]; 2154 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2155 __IM uint32_t RESERVED2[64]; 2156 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2157 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2158 __IM uint32_t RESERVED3[61]; 2159 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2160 __IM uint32_t RESERVED4[63]; 2161 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2162 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2163 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2164 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2165 __IM uint32_t RESERVED5[4]; 2166 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2167 __IM uint32_t RESERVED6[5]; 2168 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2169 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2170 2171 2172 2173 /* =========================================================================================================================== */ 2174 /* ================ EGU0 ================ */ 2175 /* =========================================================================================================================== */ 2176 2177 2178 /** 2179 * @brief Event Generator Unit 0 (EGU0) 2180 */ 2181 2182 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 2183 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering 2184 the corresponding TRIGGERED[n] event */ 2185 __IM uint32_t RESERVED[48]; 2186 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated 2187 by triggering the corresponding TRIGGER[n] 2188 task */ 2189 __IM uint32_t RESERVED1[112]; 2190 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2191 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2192 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2193 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2194 2195 2196 2197 /* =========================================================================================================================== */ 2198 /* ================ SWI0 ================ */ 2199 /* =========================================================================================================================== */ 2200 2201 2202 /** 2203 * @brief Software interrupt 0 (SWI0) 2204 */ 2205 2206 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2207 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2208 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2209 2210 2211 2212 /* =========================================================================================================================== */ 2213 /* ================ PWM0 ================ */ 2214 /* =========================================================================================================================== */ 2215 2216 2217 /** 2218 * @brief Pulse width modulation unit 0 (PWM0) 2219 */ 2220 2221 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2222 __IM uint32_t RESERVED; 2223 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2224 the end of current PWM period, and stops 2225 sequence playback */ 2226 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM 2227 value on all enabled channels from sequence 2228 n, and starts playing that sequence at the 2229 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2230 Causes PWM generation to start if not running. */ 2231 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2232 all enabled channels if DECODER.MODE=NextStep. 2233 Does not cause PWM generation to start if 2234 not running. */ 2235 __IM uint32_t RESERVED1[60]; 2236 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2237 are no longer generated */ 2238 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started 2239 on sequence n */ 2240 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of 2241 every sequence n, when last value from RAM 2242 has been applied to wave counter */ 2243 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2244 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2245 of times defined in LOOP.CNT */ 2246 __IM uint32_t RESERVED2[56]; 2247 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2248 __IM uint32_t RESERVED3[63]; 2249 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2250 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2251 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2252 __IM uint32_t RESERVED4[125]; 2253 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2254 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2255 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2256 counts */ 2257 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2258 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2259 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2260 __IM uint32_t RESERVED5[2]; 2261 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2262 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2263 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2264 2265 2266 2267 /* =========================================================================================================================== */ 2268 /* ================ PDM ================ */ 2269 /* =========================================================================================================================== */ 2270 2271 2272 /** 2273 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2274 */ 2275 2276 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2277 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2278 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2279 __IM uint32_t RESERVED[62]; 2280 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2281 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2282 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2283 by SAMPLE.MAXCNT (or the last sample after 2284 a STOP task has been received) to Data RAM */ 2285 __IM uint32_t RESERVED1[125]; 2286 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2287 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2288 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2289 __IM uint32_t RESERVED2[125]; 2290 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2291 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2292 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2293 signals */ 2294 __IM uint32_t RESERVED3[3]; 2295 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2296 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2297 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2298 sample rate. Change PDMCLKCTRL accordingly. */ 2299 __IM uint32_t RESERVED4[7]; 2300 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2301 __IM uint32_t RESERVED5[6]; 2302 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2303 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2304 2305 2306 2307 /* =========================================================================================================================== */ 2308 /* ================ ACL ================ */ 2309 /* =========================================================================================================================== */ 2310 2311 2312 /** 2313 * @brief Access control lists (ACL) 2314 */ 2315 2316 typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 2317 __IM uint32_t RESERVED[512]; 2318 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 2319 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 2320 2321 2322 2323 /* =========================================================================================================================== */ 2324 /* ================ NVMC ================ */ 2325 /* =========================================================================================================================== */ 2326 2327 2328 /** 2329 * @brief Non Volatile Memory Controller (NVMC) 2330 */ 2331 2332 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2333 __IM uint32_t RESERVED[256]; 2334 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2335 __IM uint32_t RESERVED1; 2336 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2337 __IM uint32_t RESERVED2[62]; 2338 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2339 2340 union { 2341 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 2342 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2343 page in code area. Equivalent to ERASEPAGE. */ 2344 }; 2345 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2346 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2347 page in code area. Equivalent to ERASEPAGE. */ 2348 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 2349 registers */ 2350 __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 2351 area */ 2352 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2353 __IM uint32_t RESERVED3[8]; 2354 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ 2355 __IM uint32_t RESERVED4; 2356 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ 2357 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ 2358 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2359 2360 2361 2362 /* =========================================================================================================================== */ 2363 /* ================ PPI ================ */ 2364 /* =========================================================================================================================== */ 2365 2366 2367 /** 2368 * @brief Programmable Peripheral Interconnect (PPI) 2369 */ 2370 2371 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2372 __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2373 __IM uint32_t RESERVED[308]; 2374 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2375 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2376 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2377 __IM uint32_t RESERVED1; 2378 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2379 __IM uint32_t RESERVED2[148]; 2380 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ 2381 __IM uint32_t RESERVED3[62]; 2382 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2383 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2384 2385 2386 2387 /* =========================================================================================================================== */ 2388 /* ================ MWU ================ */ 2389 /* =========================================================================================================================== */ 2390 2391 2392 /** 2393 * @brief Memory Watch Unit (MWU) 2394 */ 2395 2396 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2397 __IM uint32_t RESERVED[64]; 2398 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ 2399 __IM uint32_t RESERVED1[16]; 2400 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ 2401 __IM uint32_t RESERVED2[100]; 2402 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2403 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2404 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2405 __IM uint32_t RESERVED3[5]; 2406 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ 2407 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ 2408 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ 2409 __IM uint32_t RESERVED4[53]; 2410 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2411 __IM uint32_t RESERVED5[64]; 2412 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2413 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2414 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2415 __IM uint32_t RESERVED6[57]; 2416 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2417 __IM uint32_t RESERVED7[32]; 2418 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2419 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2420 2421 2422 2423 /* =========================================================================================================================== */ 2424 /* ================ I2S ================ */ 2425 /* =========================================================================================================================== */ 2426 2427 2428 /** 2429 * @brief Inter-IC Sound (I2S) 2430 */ 2431 2432 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2433 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2434 generator when this is enabled. */ 2435 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2436 Triggering this task will cause the {event:STOPPED} 2437 event to be generated. */ 2438 __IM uint32_t RESERVED[63]; 2439 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2440 double-buffers. When the I2S module is started 2441 and RX is enabled, this event will be generated 2442 for every RXTXD.MAXCNT words that are received 2443 on the SDIN pin. */ 2444 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2445 __IM uint32_t RESERVED1[2]; 2446 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2447 double-buffers. When the I2S module is started 2448 and TX is enabled, this event will be generated 2449 for every RXTXD.MAXCNT words that are sent 2450 on the SDOUT pin. */ 2451 __IM uint32_t RESERVED2[122]; 2452 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2453 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2454 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2455 __IM uint32_t RESERVED3[125]; 2456 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2457 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2458 __IM uint32_t RESERVED4[3]; 2459 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2460 __IM uint32_t RESERVED5; 2461 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2462 __IM uint32_t RESERVED6[3]; 2463 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2464 __IM uint32_t RESERVED7[3]; 2465 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2466 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2467 2468 2469 2470 /* =========================================================================================================================== */ 2471 /* ================ FPU ================ */ 2472 /* =========================================================================================================================== */ 2473 2474 2475 /** 2476 * @brief FPU (FPU) 2477 */ 2478 2479 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2480 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2481 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2482 2483 2484 2485 /* =========================================================================================================================== */ 2486 /* ================ USBD ================ */ 2487 /* =========================================================================================================================== */ 2488 2489 2490 /** 2491 * @brief Universal serial bus device (USBD) 2492 */ 2493 2494 typedef struct { /*!< (@ 0x40027000) USBD Structure */ 2495 __IM uint32_t RESERVED; 2496 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR 2497 and EPIN[n].MAXCNT registers values, and 2498 enables endpoint IN n to respond to traffic 2499 from host */ 2500 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2501 values, and enables sending data on ISO 2502 endpoint */ 2503 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR 2504 and EPOUT[n].MAXCNT registers values, and 2505 enables endpoint n to respond to traffic 2506 from host */ 2507 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2508 values, and enables receiving of data on 2509 ISO endpoint */ 2510 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2511 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2512 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2513 0 */ 2514 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2515 in the DPDMVALUE register */ 2516 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2517 (USB engine takes control) */ 2518 __IM uint32_t RESERVED1[40]; 2519 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2520 on USB lines */ 2521 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2522 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2523 have been captured on all endpoints reported 2524 in the EPSTATUS register */ 2525 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] 2526 buffer has been consumed. The RAM buffer 2527 can be accessed safely by software. */ 2528 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2529 on the control endpoint */ 2530 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2531 RAM buffer can be accessed safely by software. */ 2532 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] 2533 buffer has been consumed. The RAM buffer 2534 can be accessed safely by software. */ 2535 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2536 RAM buffer can be accessed safely by software. */ 2537 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2538 has been detected on USB lines */ 2539 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2540 events has occurred. Check EVENTCAUSE register 2541 to find the cause. */ 2542 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2543 on the control endpoint */ 2544 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2545 indicated by the EPDATASTATUS register */ 2546 __IM uint32_t RESERVED2[39]; 2547 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2548 __IM uint32_t RESERVED3[63]; 2549 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2550 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2551 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2552 __IM uint32_t RESERVED4[61]; 2553 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2554 __IM uint32_t RESERVED5[7]; 2555 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2556 __IM uint32_t RESERVED6; 2557 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2558 registers have been captured */ 2559 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2560 acknowledged data transfer has occurred 2561 (EPDATA event) */ 2562 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2563 __IM uint32_t RESERVED7[3]; 2564 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2565 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2566 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2567 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2568 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2569 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2570 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2571 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2572 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2573 __IM uint32_t RESERVED8[15]; 2574 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2575 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2576 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2577 the DPDMDRIVE task. The DPDMNODRIVE task 2578 reverts the control of the lines to MAC 2579 IP (no forcing). */ 2580 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2581 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2582 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2583 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2584 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2585 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2586 counter */ 2587 __IM uint32_t RESERVED9[2]; 2588 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2589 USB suspend */ 2590 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2591 to an IN token when no data is ready to 2592 be sent */ 2593 __IM uint32_t RESERVED10[51]; 2594 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 2595 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 2596 __IM uint32_t RESERVED11[21]; 2597 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 2598 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 2599 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 2600 2601 2602 2603 /* =========================================================================================================================== */ 2604 /* ================ QSPI ================ */ 2605 /* =========================================================================================================================== */ 2606 2607 2608 /** 2609 * @brief External flash interface (QSPI) 2610 */ 2611 2612 typedef struct { /*!< (@ 0x40029000) QSPI Structure */ 2613 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2614 __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2615 internal RAM */ 2616 __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2617 flash memory */ 2618 __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2619 __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2620 __IM uint32_t RESERVED[59]; 2621 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2622 generated as a response to any QSPI task. */ 2623 __IM uint32_t RESERVED1[127]; 2624 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2625 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2626 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2627 __IM uint32_t RESERVED2[125]; 2628 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2629 in PSELn registers */ 2630 __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2631 __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2632 __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2633 __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2634 __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2635 in Place operation. */ 2636 __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2637 __IM uint32_t RESERVED3[46]; 2638 __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2639 __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2640 __IM uint32_t RESERVED4[3]; 2641 __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2642 power-down mode (DPM). */ 2643 __IM uint32_t RESERVED5[3]; 2644 __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2645 __IM uint32_t RESERVED6[3]; 2646 __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2647 __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2648 __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2649 __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2650 } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2651 2652 2653 2654 /* =========================================================================================================================== */ 2655 /* ================ P0 ================ */ 2656 /* =========================================================================================================================== */ 2657 2658 2659 /** 2660 * @brief GPIO Port 1 (P0) 2661 */ 2662 2663 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 2664 __IM uint32_t RESERVED[321]; 2665 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 2666 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 2667 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 2668 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 2669 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 2670 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 2671 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 2672 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 2673 have met the criteria set in the PIN_CNF[n].SENSE 2674 registers */ 2675 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 2676 and LDETECT mode */ 2677 __IM uint32_t RESERVED1[118]; 2678 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO 2679 pins */ 2680 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 2681 2682 2683 2684 /* =========================================================================================================================== */ 2685 /* ================ CC_HOST_RGF ================ */ 2686 /* =========================================================================================================================== */ 2687 2688 2689 /** 2690 * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) 2691 */ 2692 2693 typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ 2694 __IM uint32_t RESERVED[1678]; 2695 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 2696 __IM uint32_t RESERVED1[4]; 2697 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 2698 When this register is set, K_PRTL can not 2699 be used and a zeroed key will be used instead. 2700 The value of this register is saved in the 2701 CRYPTOCELL AO power domain. */ 2702 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 2703 of this register is saved in the CRYPTOCELL 2704 AO power domain. Reading from this address 2705 returns the K_DR valid status indicating 2706 if K_DR is successfully retained. */ 2707 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 2708 of this register is saved in the CRYPTOCELL 2709 AO power domain. */ 2710 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 2711 of this register is saved in the CRYPTOCELL 2712 AO power domain. */ 2713 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 2714 value of this register is saved in the CRYPTOCELL 2715 AO power domain. */ 2716 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 2717 subsystem */ 2718 } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 2719 2720 2721 2722 /* =========================================================================================================================== */ 2723 /* ================ CRYPTOCELL ================ */ 2724 /* =========================================================================================================================== */ 2725 2726 2727 /** 2728 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) 2729 */ 2730 2731 typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ 2732 __IM uint32_t RESERVED[320]; 2733 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 2734 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2735 2736 2737 /** @} */ /* End of group Device_Peripheral_peripherals */ 2738 2739 2740 /* =========================================================================================================================== */ 2741 /* ================ Device Specific Peripheral Address Map ================ */ 2742 /* =========================================================================================================================== */ 2743 2744 2745 /** @addtogroup Device_Peripheral_peripheralAddr 2746 * @{ 2747 */ 2748 2749 #define NRF_FICR_BASE 0x10000000UL 2750 #define NRF_UICR_BASE 0x10001000UL 2751 #define NRF_CLOCK_BASE 0x40000000UL 2752 #define NRF_POWER_BASE 0x40000000UL 2753 #define NRF_RADIO_BASE 0x40001000UL 2754 #define NRF_UART0_BASE 0x40002000UL 2755 #define NRF_UARTE0_BASE 0x40002000UL 2756 #define NRF_SPI0_BASE 0x40003000UL 2757 #define NRF_SPIM0_BASE 0x40003000UL 2758 #define NRF_SPIS0_BASE 0x40003000UL 2759 #define NRF_TWI0_BASE 0x40003000UL 2760 #define NRF_TWIM0_BASE 0x40003000UL 2761 #define NRF_TWIS0_BASE 0x40003000UL 2762 #define NRF_SPI1_BASE 0x40004000UL 2763 #define NRF_SPIM1_BASE 0x40004000UL 2764 #define NRF_SPIS1_BASE 0x40004000UL 2765 #define NRF_TWI1_BASE 0x40004000UL 2766 #define NRF_TWIM1_BASE 0x40004000UL 2767 #define NRF_TWIS1_BASE 0x40004000UL 2768 #define NRF_NFCT_BASE 0x40005000UL 2769 #define NRF_GPIOTE_BASE 0x40006000UL 2770 #define NRF_SAADC_BASE 0x40007000UL 2771 #define NRF_TIMER0_BASE 0x40008000UL 2772 #define NRF_TIMER1_BASE 0x40009000UL 2773 #define NRF_TIMER2_BASE 0x4000A000UL 2774 #define NRF_RTC0_BASE 0x4000B000UL 2775 #define NRF_TEMP_BASE 0x4000C000UL 2776 #define NRF_RNG_BASE 0x4000D000UL 2777 #define NRF_ECB_BASE 0x4000E000UL 2778 #define NRF_AAR_BASE 0x4000F000UL 2779 #define NRF_CCM_BASE 0x4000F000UL 2780 #define NRF_WDT_BASE 0x40010000UL 2781 #define NRF_RTC1_BASE 0x40011000UL 2782 #define NRF_QDEC_BASE 0x40012000UL 2783 #define NRF_COMP_BASE 0x40013000UL 2784 #define NRF_LPCOMP_BASE 0x40013000UL 2785 #define NRF_EGU0_BASE 0x40014000UL 2786 #define NRF_SWI0_BASE 0x40014000UL 2787 #define NRF_EGU1_BASE 0x40015000UL 2788 #define NRF_SWI1_BASE 0x40015000UL 2789 #define NRF_EGU2_BASE 0x40016000UL 2790 #define NRF_SWI2_BASE 0x40016000UL 2791 #define NRF_EGU3_BASE 0x40017000UL 2792 #define NRF_SWI3_BASE 0x40017000UL 2793 #define NRF_EGU4_BASE 0x40018000UL 2794 #define NRF_SWI4_BASE 0x40018000UL 2795 #define NRF_EGU5_BASE 0x40019000UL 2796 #define NRF_SWI5_BASE 0x40019000UL 2797 #define NRF_TIMER3_BASE 0x4001A000UL 2798 #define NRF_TIMER4_BASE 0x4001B000UL 2799 #define NRF_PWM0_BASE 0x4001C000UL 2800 #define NRF_PDM_BASE 0x4001D000UL 2801 #define NRF_ACL_BASE 0x4001E000UL 2802 #define NRF_NVMC_BASE 0x4001E000UL 2803 #define NRF_PPI_BASE 0x4001F000UL 2804 #define NRF_MWU_BASE 0x40020000UL 2805 #define NRF_PWM1_BASE 0x40021000UL 2806 #define NRF_PWM2_BASE 0x40022000UL 2807 #define NRF_SPI2_BASE 0x40023000UL 2808 #define NRF_SPIM2_BASE 0x40023000UL 2809 #define NRF_SPIS2_BASE 0x40023000UL 2810 #define NRF_RTC2_BASE 0x40024000UL 2811 #define NRF_I2S_BASE 0x40025000UL 2812 #define NRF_FPU_BASE 0x40026000UL 2813 #define NRF_USBD_BASE 0x40027000UL 2814 #define NRF_UARTE1_BASE 0x40028000UL 2815 #define NRF_QSPI_BASE 0x40029000UL 2816 #define NRF_PWM3_BASE 0x4002D000UL 2817 #define NRF_SPIM3_BASE 0x4002F000UL 2818 #define NRF_P0_BASE 0x50000000UL 2819 #define NRF_P1_BASE 0x50000300UL 2820 #define NRF_CC_HOST_RGF_BASE 0x5002A000UL 2821 #define NRF_CRYPTOCELL_BASE 0x5002A000UL 2822 2823 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2824 2825 2826 /* =========================================================================================================================== */ 2827 /* ================ Peripheral declaration ================ */ 2828 /* =========================================================================================================================== */ 2829 2830 2831 /** @addtogroup Device_Peripheral_declaration 2832 * @{ 2833 */ 2834 2835 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2836 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2837 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2838 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2839 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2840 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2841 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2842 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2843 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2844 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2845 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2846 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2847 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2848 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2849 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2850 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2851 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2852 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2853 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2854 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2855 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2856 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2857 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2858 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2859 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2860 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2861 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2862 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2863 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2864 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2865 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2866 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2867 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2868 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2869 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2870 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2871 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2872 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2873 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2874 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2875 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2876 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2877 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2878 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2879 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2880 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2881 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2882 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2883 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2884 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2885 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2886 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2887 #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 2888 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2889 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2890 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2891 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2892 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2893 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2894 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2895 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2896 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2897 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2898 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2899 #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 2900 #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) 2901 #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) 2902 #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) 2903 #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) 2904 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2905 #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) 2906 #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) 2907 #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) 2908 2909 /** @} */ /* End of group Device_Peripheral_declaration */ 2910 2911 2912 /* ========================================= End of section using anonymous unions ========================================= */ 2913 #if defined (__CC_ARM) 2914 #pragma pop 2915 #elif defined (__ICCARM__) 2916 /* leave anonymous unions enabled */ 2917 #elif (__ARMCC_VERSION >= 6010050) 2918 #pragma clang diagnostic pop 2919 #elif defined (__GNUC__) 2920 /* anonymous unions are enabled by default */ 2921 #elif defined (__TMS470__) 2922 /* anonymous unions are enabled by default */ 2923 #elif defined (__TASKING__) 2924 #pragma warning restore 2925 #elif defined (__CSMC__) 2926 /* anonymous unions are enabled by default */ 2927 #endif 2928 2929 2930 #ifdef __cplusplus 2931 } 2932 #endif 2933 2934 #endif /* NRF52840_H */ 2935 2936 2937 /** @} */ /* End of group nrf52840 */ 2938 2939 /** @} */ /* End of group Nordic Semiconductor */ 2940