1*150812a8SEvalZero /* 2*150812a8SEvalZero 3*150812a8SEvalZero Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 4*150812a8SEvalZero 5*150812a8SEvalZero Redistribution and use in source and binary forms, with or without 6*150812a8SEvalZero modification, are permitted provided that the following conditions are met: 7*150812a8SEvalZero 8*150812a8SEvalZero 1. Redistributions of source code must retain the above copyright notice, this 9*150812a8SEvalZero list of conditions and the following disclaimer. 10*150812a8SEvalZero 11*150812a8SEvalZero 2. Redistributions in binary form must reproduce the above copyright 12*150812a8SEvalZero notice, this list of conditions and the following disclaimer in the 13*150812a8SEvalZero documentation and/or other materials provided with the distribution. 14*150812a8SEvalZero 15*150812a8SEvalZero 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16*150812a8SEvalZero contributors may be used to endorse or promote products derived from this 17*150812a8SEvalZero software without specific prior written permission. 18*150812a8SEvalZero 19*150812a8SEvalZero THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20*150812a8SEvalZero AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*150812a8SEvalZero IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22*150812a8SEvalZero ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23*150812a8SEvalZero LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24*150812a8SEvalZero CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25*150812a8SEvalZero SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26*150812a8SEvalZero INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27*150812a8SEvalZero CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28*150812a8SEvalZero ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29*150812a8SEvalZero POSSIBILITY OF SUCH DAMAGE. 30*150812a8SEvalZero 31*150812a8SEvalZero */ 32*150812a8SEvalZero 33*150812a8SEvalZero #ifndef _NRF52810_PERIPHERALS_H 34*150812a8SEvalZero #define _NRF52810_PERIPHERALS_H 35*150812a8SEvalZero 36*150812a8SEvalZero 37*150812a8SEvalZero /* Clock Peripheral */ 38*150812a8SEvalZero #define CLOCK_PRESENT 39*150812a8SEvalZero #define CLOCK_COUNT 1 40*150812a8SEvalZero 41*150812a8SEvalZero /* Power Peripheral */ 42*150812a8SEvalZero #define POWER_PRESENT 43*150812a8SEvalZero #define POWER_COUNT 1 44*150812a8SEvalZero 45*150812a8SEvalZero #define POWER_FEATURE_RAM_REGISTERS_PRESENT 46*150812a8SEvalZero #define POWER_FEATURE_RAM_REGISTERS_COUNT 3 47*150812a8SEvalZero 48*150812a8SEvalZero /* Systick timer */ 49*150812a8SEvalZero #define SYSTICK_PRESENT 50*150812a8SEvalZero #define SYSTICK_COUNT 1 51*150812a8SEvalZero 52*150812a8SEvalZero /* Software Interrupts */ 53*150812a8SEvalZero #define SWI_PRESENT 54*150812a8SEvalZero #define SWI_COUNT 6 55*150812a8SEvalZero 56*150812a8SEvalZero /* GPIO */ 57*150812a8SEvalZero #define GPIO_PRESENT 58*150812a8SEvalZero #define GPIO_COUNT 1 59*150812a8SEvalZero 60*150812a8SEvalZero #define P0_PIN_NUM 32 61*150812a8SEvalZero 62*150812a8SEvalZero /* MPU and BPROT */ 63*150812a8SEvalZero #define BPROT_PRESENT 64*150812a8SEvalZero 65*150812a8SEvalZero #define BPROT_REGIONS_SIZE 4096 66*150812a8SEvalZero #define BPROT_REGIONS_NUM 48 67*150812a8SEvalZero 68*150812a8SEvalZero /* Radio */ 69*150812a8SEvalZero #define RADIO_PRESENT 70*150812a8SEvalZero #define RADIO_COUNT 1 71*150812a8SEvalZero 72*150812a8SEvalZero #define RADIO_EASYDMA_MAXCNT_SIZE 8 73*150812a8SEvalZero 74*150812a8SEvalZero /* Accelerated Address Resolver */ 75*150812a8SEvalZero #define AAR_PRESENT 76*150812a8SEvalZero #define AAR_COUNT 1 77*150812a8SEvalZero 78*150812a8SEvalZero #define AAR_MAX_IRK_NUM 16 79*150812a8SEvalZero 80*150812a8SEvalZero /* AES Electronic CodeBook mode encryption */ 81*150812a8SEvalZero #define ECB_PRESENT 82*150812a8SEvalZero #define ECB_COUNT 1 83*150812a8SEvalZero 84*150812a8SEvalZero /* AES CCM mode encryption */ 85*150812a8SEvalZero #define CCM_PRESENT 86*150812a8SEvalZero #define CCM_COUNT 1 87*150812a8SEvalZero 88*150812a8SEvalZero /* Peripheral to Peripheral Interconnect */ 89*150812a8SEvalZero #define PPI_PRESENT 90*150812a8SEvalZero #define PPI_COUNT 1 91*150812a8SEvalZero 92*150812a8SEvalZero #define PPI_CH_NUM 20 93*150812a8SEvalZero #define PPI_FIXED_CH_NUM 12 94*150812a8SEvalZero #define PPI_GROUP_NUM 6 95*150812a8SEvalZero #define PPI_FEATURE_FORKS_PRESENT 96*150812a8SEvalZero 97*150812a8SEvalZero /* Event Generator Unit */ 98*150812a8SEvalZero #define EGU_PRESENT 99*150812a8SEvalZero #define EGU_COUNT 2 100*150812a8SEvalZero 101*150812a8SEvalZero #define EGU0_CH_NUM 16 102*150812a8SEvalZero #define EGU1_CH_NUM 16 103*150812a8SEvalZero 104*150812a8SEvalZero /* Timer/Counter */ 105*150812a8SEvalZero #define TIMER_PRESENT 106*150812a8SEvalZero #define TIMER_COUNT 3 107*150812a8SEvalZero 108*150812a8SEvalZero #define TIMER0_MAX_SIZE 32 109*150812a8SEvalZero #define TIMER1_MAX_SIZE 32 110*150812a8SEvalZero #define TIMER2_MAX_SIZE 32 111*150812a8SEvalZero 112*150812a8SEvalZero #define TIMER0_CC_NUM 4 113*150812a8SEvalZero #define TIMER1_CC_NUM 4 114*150812a8SEvalZero #define TIMER2_CC_NUM 4 115*150812a8SEvalZero 116*150812a8SEvalZero /* Real Time Counter */ 117*150812a8SEvalZero #define RTC_PRESENT 118*150812a8SEvalZero #define RTC_COUNT 2 119*150812a8SEvalZero 120*150812a8SEvalZero #define RTC0_CC_NUM 3 121*150812a8SEvalZero #define RTC1_CC_NUM 4 122*150812a8SEvalZero 123*150812a8SEvalZero /* RNG */ 124*150812a8SEvalZero #define RNG_PRESENT 125*150812a8SEvalZero #define RNG_COUNT 1 126*150812a8SEvalZero 127*150812a8SEvalZero /* Watchdog Timer */ 128*150812a8SEvalZero #define WDT_PRESENT 129*150812a8SEvalZero #define WDT_COUNT 1 130*150812a8SEvalZero 131*150812a8SEvalZero /* Temperature Sensor */ 132*150812a8SEvalZero #define TEMP_PRESENT 133*150812a8SEvalZero #define TEMP_COUNT 1 134*150812a8SEvalZero 135*150812a8SEvalZero /* Serial Peripheral Interface Master with DMA */ 136*150812a8SEvalZero #define SPIM_PRESENT 137*150812a8SEvalZero #define SPIM_COUNT 1 138*150812a8SEvalZero 139*150812a8SEvalZero #define SPIM0_MAX_DATARATE 8 140*150812a8SEvalZero 141*150812a8SEvalZero #define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 142*150812a8SEvalZero 143*150812a8SEvalZero #define SPIM0_FEATURE_DCX_PRESENT 0 144*150812a8SEvalZero 145*150812a8SEvalZero #define SPIM0_FEATURE_RXDELAY_PRESENT 0 146*150812a8SEvalZero 147*150812a8SEvalZero #define SPIM0_EASYDMA_MAXCNT_SIZE 10 148*150812a8SEvalZero 149*150812a8SEvalZero /* Serial Peripheral Interface Slave with DMA*/ 150*150812a8SEvalZero #define SPIS_PRESENT 151*150812a8SEvalZero #define SPIS_COUNT 1 152*150812a8SEvalZero 153*150812a8SEvalZero #define SPIS0_EASYDMA_MAXCNT_SIZE 10 154*150812a8SEvalZero 155*150812a8SEvalZero /* Two Wire Interface Master with DMA */ 156*150812a8SEvalZero #define TWIM_PRESENT 157*150812a8SEvalZero #define TWIM_COUNT 1 158*150812a8SEvalZero 159*150812a8SEvalZero #define TWIM0_EASYDMA_MAXCNT_SIZE 10 160*150812a8SEvalZero 161*150812a8SEvalZero /* Two Wire Interface Slave with DMA */ 162*150812a8SEvalZero #define TWIS_PRESENT 163*150812a8SEvalZero #define TWIS_COUNT 1 164*150812a8SEvalZero 165*150812a8SEvalZero #define TWIS0_EASYDMA_MAXCNT_SIZE 10 166*150812a8SEvalZero 167*150812a8SEvalZero /* Universal Asynchronous Receiver-Transmitter with DMA */ 168*150812a8SEvalZero #define UARTE_PRESENT 169*150812a8SEvalZero #define UARTE_COUNT 1 170*150812a8SEvalZero 171*150812a8SEvalZero #define UARTE0_EASYDMA_MAXCNT_SIZE 10 172*150812a8SEvalZero 173*150812a8SEvalZero /* Quadrature Decoder */ 174*150812a8SEvalZero #define QDEC_PRESENT 175*150812a8SEvalZero #define QDEC_COUNT 1 176*150812a8SEvalZero 177*150812a8SEvalZero /* Successive Approximation Analog to Digital Converter */ 178*150812a8SEvalZero #define SAADC_PRESENT 179*150812a8SEvalZero #define SAADC_COUNT 1 180*150812a8SEvalZero 181*150812a8SEvalZero #define SAADC_EASYDMA_MAXCNT_SIZE 15 182*150812a8SEvalZero 183*150812a8SEvalZero #define SAADC_CH_NUM 8 184*150812a8SEvalZero 185*150812a8SEvalZero /* GPIO Tasks and Events */ 186*150812a8SEvalZero #define GPIOTE_PRESENT 187*150812a8SEvalZero #define GPIOTE_COUNT 1 188*150812a8SEvalZero 189*150812a8SEvalZero #define GPIOTE_CH_NUM 8 190*150812a8SEvalZero 191*150812a8SEvalZero #define GPIOTE_FEATURE_SET_PRESENT 192*150812a8SEvalZero #define GPIOTE_FEATURE_CLR_PRESENT 193*150812a8SEvalZero 194*150812a8SEvalZero /* Comparator */ 195*150812a8SEvalZero #define COMP_PRESENT 196*150812a8SEvalZero #define COMP_COUNT 1 197*150812a8SEvalZero 198*150812a8SEvalZero /* Pulse Width Modulator */ 199*150812a8SEvalZero #define PWM_PRESENT 200*150812a8SEvalZero #define PWM_COUNT 1 201*150812a8SEvalZero 202*150812a8SEvalZero #define PWM0_CH_NUM 4 203*150812a8SEvalZero 204*150812a8SEvalZero #define PWM0_EASYDMA_MAXCNT_SIZE 15 205*150812a8SEvalZero 206*150812a8SEvalZero /* Pulse Density Modulator */ 207*150812a8SEvalZero #define PDM_PRESENT 208*150812a8SEvalZero #define PDM_COUNT 1 209*150812a8SEvalZero 210*150812a8SEvalZero #define PDM_EASYDMA_MAXCNT_SIZE 15 211*150812a8SEvalZero 212*150812a8SEvalZero 213*150812a8SEvalZero #endif // _NRF52810_PERIPHERALS_H 214