1 /* 2 3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef __NRF52810_BITS_H 34 #define __NRF52810_BITS_H 35 36 /*lint ++flb "Enter library region" */ 37 38 /* Peripheral: AAR */ 39 /* Description: Accelerated Address Resolver */ 40 41 /* Register: AAR_TASKS_START */ 42 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ 43 44 /* Bit 0 : */ 45 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 46 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 47 48 /* Register: AAR_TASKS_STOP */ 49 /* Description: Stop resolving addresses */ 50 51 /* Bit 0 : */ 52 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 53 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 54 55 /* Register: AAR_EVENTS_END */ 56 /* Description: Address resolution procedure complete */ 57 58 /* Bit 0 : */ 59 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 60 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 61 62 /* Register: AAR_EVENTS_RESOLVED */ 63 /* Description: Address resolved */ 64 65 /* Bit 0 : */ 66 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ 67 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ 68 69 /* Register: AAR_EVENTS_NOTRESOLVED */ 70 /* Description: Address not resolved */ 71 72 /* Bit 0 : */ 73 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ 74 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ 75 76 /* Register: AAR_INTENSET */ 77 /* Description: Enable interrupt */ 78 79 /* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ 80 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 81 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 83 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 84 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ 85 86 /* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ 87 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 88 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 90 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 91 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ 92 93 /* Bit 0 : Write '1' to enable interrupt for END event */ 94 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 95 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 97 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 98 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */ 99 100 /* Register: AAR_INTENCLR */ 101 /* Description: Disable interrupt */ 102 103 /* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ 104 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 105 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 107 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 108 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ 109 110 /* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ 111 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 112 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 114 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 115 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ 116 117 /* Bit 0 : Write '1' to disable interrupt for END event */ 118 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 119 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 121 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 122 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ 123 124 /* Register: AAR_STATUS */ 125 /* Description: Resolution status */ 126 127 /* Bits 3..0 : The IRK that was used last time an address was resolved */ 128 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 129 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 130 131 /* Register: AAR_ENABLE */ 132 /* Description: Enable AAR */ 133 134 /* Bits 1..0 : Enable or disable AAR */ 135 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 136 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 137 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 138 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ 139 140 /* Register: AAR_NIRK */ 141 /* Description: Number of IRKs */ 142 143 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ 144 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 145 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 146 147 /* Register: AAR_IRKPTR */ 148 /* Description: Pointer to IRK data structure */ 149 150 /* Bits 31..0 : Pointer to the IRK data structure */ 151 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ 152 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ 153 154 /* Register: AAR_ADDRPTR */ 155 /* Description: Pointer to the resolvable address */ 156 157 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ 158 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ 159 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ 160 161 /* Register: AAR_SCRATCHPTR */ 162 /* Description: Pointer to data area used for temporary storage */ 163 164 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ 165 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 166 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 167 168 169 /* Peripheral: BPROT */ 170 /* Description: Block Protect */ 171 172 /* Register: BPROT_CONFIG0 */ 173 /* Description: Block protect configuration register 0 */ 174 175 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ 176 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ 177 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ 178 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ 179 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */ 180 181 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ 182 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ 183 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ 184 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ 185 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */ 186 187 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ 188 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ 189 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ 190 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ 191 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */ 192 193 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ 194 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ 195 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ 196 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ 197 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */ 198 199 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ 200 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ 201 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ 202 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ 203 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */ 204 205 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ 206 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ 207 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ 208 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ 209 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */ 210 211 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ 212 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ 213 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ 214 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ 215 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */ 216 217 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ 218 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ 219 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ 220 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ 221 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */ 222 223 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ 224 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ 225 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ 226 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ 227 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */ 228 229 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ 230 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ 231 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ 232 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ 233 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */ 234 235 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ 236 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ 237 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ 238 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ 239 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */ 240 241 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ 242 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ 243 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ 244 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ 245 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */ 246 247 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ 248 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ 249 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ 250 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ 251 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */ 252 253 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ 254 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ 255 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ 256 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ 257 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */ 258 259 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ 260 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ 261 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ 262 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ 263 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */ 264 265 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ 266 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ 267 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ 268 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ 269 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */ 270 271 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ 272 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ 273 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ 274 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ 275 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */ 276 277 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ 278 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ 279 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ 280 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ 281 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */ 282 283 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ 284 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ 285 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ 286 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ 287 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */ 288 289 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ 290 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ 291 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ 292 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ 293 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */ 294 295 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ 296 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ 297 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ 298 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ 299 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */ 300 301 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ 302 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ 303 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ 304 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ 305 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */ 306 307 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ 308 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ 309 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ 310 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ 311 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */ 312 313 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ 314 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ 315 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ 316 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ 317 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */ 318 319 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ 320 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ 321 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ 322 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ 323 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */ 324 325 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ 326 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ 327 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ 328 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ 329 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */ 330 331 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ 332 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ 333 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ 334 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ 335 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */ 336 337 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ 338 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ 339 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ 340 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ 341 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */ 342 343 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ 344 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ 345 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ 346 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ 347 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */ 348 349 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ 350 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ 351 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ 352 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ 353 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */ 354 355 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ 356 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ 357 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ 358 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ 359 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */ 360 361 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ 362 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ 363 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ 364 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ 365 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */ 366 367 /* Register: BPROT_CONFIG1 */ 368 /* Description: Block protect configuration register 1 */ 369 370 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ 371 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ 372 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ 373 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ 374 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ 375 376 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ 377 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ 378 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ 379 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ 380 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ 381 382 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ 383 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ 384 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ 385 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ 386 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ 387 388 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ 389 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ 390 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ 391 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ 392 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ 393 394 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ 395 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ 396 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ 397 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ 398 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ 399 400 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ 401 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ 402 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ 403 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ 404 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ 405 406 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ 407 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ 408 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ 409 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ 410 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ 411 412 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ 413 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ 414 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ 415 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ 416 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ 417 418 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ 419 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ 420 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ 421 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ 422 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ 423 424 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ 425 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ 426 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ 427 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ 428 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ 429 430 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ 431 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ 432 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ 433 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ 434 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ 435 436 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ 437 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ 438 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ 439 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ 440 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ 441 442 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ 443 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ 444 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ 445 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ 446 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ 447 448 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ 449 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ 450 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ 451 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ 452 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ 453 454 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ 455 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ 456 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ 457 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ 458 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ 459 460 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ 461 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ 462 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ 463 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ 464 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ 465 466 /* Register: BPROT_DISABLEINDEBUG */ 467 /* Description: Disable protection mechanism in debug mode */ 468 469 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */ 470 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ 471 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ 472 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */ 473 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */ 474 475 476 /* Peripheral: CCM */ 477 /* Description: AES CCM Mode Encryption */ 478 479 /* Register: CCM_TASKS_KSGEN */ 480 /* Description: Start generation of key-stream. This operation will stop by itself when completed. */ 481 482 /* Bit 0 : */ 483 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ 484 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ 485 486 /* Register: CCM_TASKS_CRYPT */ 487 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ 488 489 /* Bit 0 : */ 490 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ 491 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ 492 493 /* Register: CCM_TASKS_STOP */ 494 /* Description: Stop encryption/decryption */ 495 496 /* Bit 0 : */ 497 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 498 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 499 500 /* Register: CCM_TASKS_RATEOVERRIDE */ 501 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 502 503 /* Bit 0 : */ 504 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ 505 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ 506 507 /* Register: CCM_EVENTS_ENDKSGEN */ 508 /* Description: Key-stream generation complete */ 509 510 /* Bit 0 : */ 511 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ 512 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ 513 514 /* Register: CCM_EVENTS_ENDCRYPT */ 515 /* Description: Encrypt/decrypt complete */ 516 517 /* Bit 0 : */ 518 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ 519 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ 520 521 /* Register: CCM_EVENTS_ERROR */ 522 /* Description: Deprecated register - CCM error event */ 523 524 /* Bit 0 : */ 525 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 526 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 527 528 /* Register: CCM_SHORTS */ 529 /* Description: Shortcut register */ 530 531 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ 532 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 533 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 534 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ 535 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ 536 537 /* Register: CCM_INTENSET */ 538 /* Description: Enable interrupt */ 539 540 /* Bit 2 : Write '1' to enable interrupt for ERROR event */ 541 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 542 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 543 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 544 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 545 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 546 547 /* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ 548 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 549 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 550 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 551 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 552 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ 553 554 /* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ 555 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 556 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 557 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 558 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 559 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ 560 561 /* Register: CCM_INTENCLR */ 562 /* Description: Disable interrupt */ 563 564 /* Bit 2 : Write '1' to disable interrupt for ERROR event */ 565 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 566 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 567 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 568 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 569 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 570 571 /* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ 572 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 573 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 574 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 575 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 576 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ 577 578 /* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ 579 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 580 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 581 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 582 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 583 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ 584 585 /* Register: CCM_MICSTATUS */ 586 /* Description: MIC check result */ 587 588 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */ 589 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 590 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 591 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ 592 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ 593 594 /* Register: CCM_ENABLE */ 595 /* Description: Enable */ 596 597 /* Bits 1..0 : Enable or disable CCM */ 598 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 599 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 600 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 601 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 602 603 /* Register: CCM_MODE */ 604 /* Description: Operation mode */ 605 606 /* Bit 24 : Packet length configuration */ 607 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ 608 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ 609 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ 610 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ 611 612 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ 613 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ 614 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ 615 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ 616 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ 617 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ 618 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ 619 620 /* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ 621 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 622 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 623 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ 624 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ 625 626 /* Register: CCM_CNFPTR */ 627 /* Description: Pointer to data structure holding AES key and NONCE vector */ 628 629 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ 630 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ 631 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ 632 633 /* Register: CCM_INPTR */ 634 /* Description: Input pointer */ 635 636 /* Bits 31..0 : Input pointer */ 637 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ 638 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ 639 640 /* Register: CCM_OUTPTR */ 641 /* Description: Output pointer */ 642 643 /* Bits 31..0 : Output pointer */ 644 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ 645 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ 646 647 /* Register: CCM_SCRATCHPTR */ 648 /* Description: Pointer to data area used for temporary storage */ 649 650 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, 651 MIC generation and encryption/decryption. */ 652 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 653 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 654 655 /* Register: CCM_MAXPACKETSIZE */ 656 /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ 657 658 /* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ 659 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ 660 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ 661 662 /* Register: CCM_RATEOVERRIDE */ 663 /* Description: Data rate override setting. */ 664 665 /* Bits 1..0 : Data rate override setting. */ 666 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ 667 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ 668 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ 669 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ 670 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ 671 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ 672 673 674 /* Peripheral: CLOCK */ 675 /* Description: Clock control */ 676 677 /* Register: CLOCK_TASKS_HFCLKSTART */ 678 /* Description: Start HFCLK crystal oscillator */ 679 680 /* Bit 0 : */ 681 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ 682 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ 683 684 /* Register: CLOCK_TASKS_HFCLKSTOP */ 685 /* Description: Stop HFCLK crystal oscillator */ 686 687 /* Bit 0 : */ 688 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ 689 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ 690 691 /* Register: CLOCK_TASKS_LFCLKSTART */ 692 /* Description: Start LFCLK source */ 693 694 /* Bit 0 : */ 695 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ 696 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ 697 698 /* Register: CLOCK_TASKS_LFCLKSTOP */ 699 /* Description: Stop LFCLK source */ 700 701 /* Bit 0 : */ 702 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ 703 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ 704 705 /* Register: CLOCK_TASKS_CAL */ 706 /* Description: Start calibration of LFRC oscillator */ 707 708 /* Bit 0 : */ 709 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ 710 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ 711 712 /* Register: CLOCK_TASKS_CTSTART */ 713 /* Description: Start calibration timer */ 714 715 /* Bit 0 : */ 716 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ 717 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ 718 719 /* Register: CLOCK_TASKS_CTSTOP */ 720 /* Description: Stop calibration timer */ 721 722 /* Bit 0 : */ 723 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ 724 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ 725 726 /* Register: CLOCK_EVENTS_HFCLKSTARTED */ 727 /* Description: HFCLK oscillator started */ 728 729 /* Bit 0 : */ 730 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ 731 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ 732 733 /* Register: CLOCK_EVENTS_LFCLKSTARTED */ 734 /* Description: LFCLK started */ 735 736 /* Bit 0 : */ 737 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ 738 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ 739 740 /* Register: CLOCK_EVENTS_DONE */ 741 /* Description: Calibration of LFCLK RC oscillator complete event */ 742 743 /* Bit 0 : */ 744 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 745 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 746 747 /* Register: CLOCK_EVENTS_CTTO */ 748 /* Description: Calibration timer timeout */ 749 750 /* Bit 0 : */ 751 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ 752 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ 753 754 /* Register: CLOCK_INTENSET */ 755 /* Description: Enable interrupt */ 756 757 /* Bit 4 : Write '1' to enable interrupt for CTTO event */ 758 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 759 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ 760 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ 761 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ 762 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ 763 764 /* Bit 3 : Write '1' to enable interrupt for DONE event */ 765 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ 766 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 767 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 768 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 769 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ 770 771 /* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ 772 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 773 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 774 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 775 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 776 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ 777 778 /* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ 779 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 780 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 781 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 782 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 783 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ 784 785 /* Register: CLOCK_INTENCLR */ 786 /* Description: Disable interrupt */ 787 788 /* Bit 4 : Write '1' to disable interrupt for CTTO event */ 789 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 790 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ 791 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ 792 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ 793 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ 794 795 /* Bit 3 : Write '1' to disable interrupt for DONE event */ 796 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ 797 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 798 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 799 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 800 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 801 802 /* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ 803 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 804 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 805 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 806 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 807 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ 808 809 /* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ 810 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 811 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 812 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 813 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 814 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ 815 816 /* Register: CLOCK_HFCLKRUN */ 817 /* Description: Status indicating that HFCLKSTART task has been triggered */ 818 819 /* Bit 0 : HFCLKSTART task triggered or not */ 820 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 821 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 822 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 823 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 824 825 /* Register: CLOCK_HFCLKSTAT */ 826 /* Description: HFCLK status */ 827 828 /* Bit 16 : HFCLK state */ 829 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 830 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 831 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ 832 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ 833 834 /* Bit 0 : Source of HFCLK */ 835 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 836 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 837 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ 838 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ 839 840 /* Register: CLOCK_LFCLKRUN */ 841 /* Description: Status indicating that LFCLKSTART task has been triggered */ 842 843 /* Bit 0 : LFCLKSTART task triggered or not */ 844 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 845 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 846 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 847 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 848 849 /* Register: CLOCK_LFCLKSTAT */ 850 /* Description: LFCLK status */ 851 852 /* Bit 16 : LFCLK state */ 853 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 854 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 855 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ 856 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ 857 858 /* Bits 1..0 : Source of LFCLK */ 859 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 860 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 861 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 862 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 863 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 864 865 /* Register: CLOCK_LFCLKSRCCOPY */ 866 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ 867 868 /* Bits 1..0 : Clock source */ 869 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 870 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 871 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 872 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 873 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 874 875 /* Register: CLOCK_LFCLKSRC */ 876 /* Description: Clock source for the LFCLK */ 877 878 /* Bit 17 : Enable or disable external source for LFCLK */ 879 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ 880 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ 881 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ 882 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ 883 884 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ 885 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ 886 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ 887 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ 888 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ 889 890 /* Bits 1..0 : Clock source */ 891 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 892 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 893 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 894 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 895 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 896 897 /* Register: CLOCK_CTIV */ 898 /* Description: Calibration timer interval */ 899 900 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ 901 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ 902 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ 903 904 905 /* Peripheral: COMP */ 906 /* Description: Comparator */ 907 908 /* Register: COMP_TASKS_START */ 909 /* Description: Start comparator */ 910 911 /* Bit 0 : */ 912 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 913 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 914 915 /* Register: COMP_TASKS_STOP */ 916 /* Description: Stop comparator */ 917 918 /* Bit 0 : */ 919 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 920 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 921 922 /* Register: COMP_TASKS_SAMPLE */ 923 /* Description: Sample comparator value */ 924 925 /* Bit 0 : */ 926 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ 927 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ 928 929 /* Register: COMP_EVENTS_READY */ 930 /* Description: COMP is ready and output is valid */ 931 932 /* Bit 0 : */ 933 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ 934 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ 935 936 /* Register: COMP_EVENTS_DOWN */ 937 /* Description: Downward crossing */ 938 939 /* Bit 0 : */ 940 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ 941 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ 942 943 /* Register: COMP_EVENTS_UP */ 944 /* Description: Upward crossing */ 945 946 /* Bit 0 : */ 947 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ 948 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ 949 950 /* Register: COMP_EVENTS_CROSS */ 951 /* Description: Downward or upward crossing */ 952 953 /* Bit 0 : */ 954 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ 955 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ 956 957 /* Register: COMP_SHORTS */ 958 /* Description: Shortcut register */ 959 960 /* Bit 4 : Shortcut between CROSS event and STOP task */ 961 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ 962 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ 963 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ 964 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ 965 966 /* Bit 3 : Shortcut between UP event and STOP task */ 967 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ 968 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ 969 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ 970 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ 971 972 /* Bit 2 : Shortcut between DOWN event and STOP task */ 973 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ 974 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ 975 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ 976 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ 977 978 /* Bit 1 : Shortcut between READY event and STOP task */ 979 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ 980 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ 981 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ 982 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ 983 984 /* Bit 0 : Shortcut between READY event and SAMPLE task */ 985 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ 986 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ 987 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ 988 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ 989 990 /* Register: COMP_INTEN */ 991 /* Description: Enable or disable interrupt */ 992 993 /* Bit 3 : Enable or disable interrupt for CROSS event */ 994 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 995 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ 996 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ 997 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ 998 999 /* Bit 2 : Enable or disable interrupt for UP event */ 1000 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ 1001 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ 1002 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ 1003 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ 1004 1005 /* Bit 1 : Enable or disable interrupt for DOWN event */ 1006 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 1007 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ 1008 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ 1009 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ 1010 1011 /* Bit 0 : Enable or disable interrupt for READY event */ 1012 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ 1013 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ 1014 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ 1015 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ 1016 1017 /* Register: COMP_INTENSET */ 1018 /* Description: Enable interrupt */ 1019 1020 /* Bit 3 : Write '1' to enable interrupt for CROSS event */ 1021 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 1022 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ 1023 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ 1024 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ 1025 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ 1026 1027 /* Bit 2 : Write '1' to enable interrupt for UP event */ 1028 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ 1029 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ 1030 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ 1031 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ 1032 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ 1033 1034 /* Bit 1 : Write '1' to enable interrupt for DOWN event */ 1035 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 1036 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ 1037 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ 1038 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ 1039 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ 1040 1041 /* Bit 0 : Write '1' to enable interrupt for READY event */ 1042 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 1043 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 1044 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 1045 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 1046 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ 1047 1048 /* Register: COMP_INTENCLR */ 1049 /* Description: Disable interrupt */ 1050 1051 /* Bit 3 : Write '1' to disable interrupt for CROSS event */ 1052 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 1053 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ 1054 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ 1055 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ 1056 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ 1057 1058 /* Bit 2 : Write '1' to disable interrupt for UP event */ 1059 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ 1060 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ 1061 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ 1062 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ 1063 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ 1064 1065 /* Bit 1 : Write '1' to disable interrupt for DOWN event */ 1066 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 1067 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ 1068 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ 1069 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ 1070 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ 1071 1072 /* Bit 0 : Write '1' to disable interrupt for READY event */ 1073 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 1074 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 1075 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 1076 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 1077 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ 1078 1079 /* Register: COMP_RESULT */ 1080 /* Description: Compare result */ 1081 1082 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ 1083 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 1084 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 1085 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ 1086 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ 1087 1088 /* Register: COMP_ENABLE */ 1089 /* Description: COMP enable */ 1090 1091 /* Bits 1..0 : Enable or disable COMP */ 1092 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1093 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1094 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 1095 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 1096 1097 /* Register: COMP_PSEL */ 1098 /* Description: Pin select */ 1099 1100 /* Bits 2..0 : Analog pin select */ 1101 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ 1102 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ 1103 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ 1104 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ 1105 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ 1106 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ 1107 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ 1108 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ 1109 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ 1110 #define COMP_PSEL_PSEL_VddDiv2 (7UL) /*!< VDD/2 selected as analog input */ 1111 1112 /* Register: COMP_REFSEL */ 1113 /* Description: Reference source select for single-ended mode */ 1114 1115 /* Bits 2..0 : Reference select */ 1116 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ 1117 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 1118 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ 1119 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ 1120 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ 1121 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ 1122 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ 1123 1124 /* Register: COMP_EXTREFSEL */ 1125 /* Description: External reference select */ 1126 1127 /* Bits 2..0 : External analog reference select */ 1128 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ 1129 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 1130 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ 1131 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ 1132 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ 1133 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ 1134 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ 1135 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ 1136 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ 1137 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ 1138 1139 /* Register: COMP_TH */ 1140 /* Description: Threshold configuration for hysteresis unit */ 1141 1142 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */ 1143 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ 1144 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ 1145 1146 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ 1147 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ 1148 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ 1149 1150 /* Register: COMP_MODE */ 1151 /* Description: Mode configuration */ 1152 1153 /* Bit 8 : Main operation modes */ 1154 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ 1155 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ 1156 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ 1157 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ 1158 1159 /* Bits 1..0 : Speed and power modes */ 1160 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ 1161 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ 1162 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ 1163 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ 1164 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ 1165 1166 /* Register: COMP_HYST */ 1167 /* Description: Comparator hysteresis enable */ 1168 1169 /* Bit 0 : Comparator hysteresis */ 1170 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ 1171 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ 1172 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ 1173 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ 1174 1175 1176 /* Peripheral: ECB */ 1177 /* Description: AES ECB Mode Encryption */ 1178 1179 /* Register: ECB_TASKS_STARTECB */ 1180 /* Description: Start ECB block encrypt */ 1181 1182 /* Bit 0 : */ 1183 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ 1184 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ 1185 1186 /* Register: ECB_TASKS_STOPECB */ 1187 /* Description: Abort a possible executing ECB operation */ 1188 1189 /* Bit 0 : */ 1190 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ 1191 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ 1192 1193 /* Register: ECB_EVENTS_ENDECB */ 1194 /* Description: ECB block encrypt complete */ 1195 1196 /* Bit 0 : */ 1197 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ 1198 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ 1199 1200 /* Register: ECB_EVENTS_ERRORECB */ 1201 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ 1202 1203 /* Bit 0 : */ 1204 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ 1205 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ 1206 1207 /* Register: ECB_INTENSET */ 1208 /* Description: Enable interrupt */ 1209 1210 /* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ 1211 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1212 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1213 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1214 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1215 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ 1216 1217 /* Bit 0 : Write '1' to enable interrupt for ENDECB event */ 1218 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1219 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1220 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1221 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1222 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ 1223 1224 /* Register: ECB_INTENCLR */ 1225 /* Description: Disable interrupt */ 1226 1227 /* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ 1228 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1229 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1230 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1231 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1232 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ 1233 1234 /* Bit 0 : Write '1' to disable interrupt for ENDECB event */ 1235 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1236 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1237 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1238 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1239 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ 1240 1241 /* Register: ECB_ECBDATAPTR */ 1242 /* Description: ECB block encrypt memory pointers */ 1243 1244 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ 1245 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ 1246 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ 1247 1248 1249 /* Peripheral: EGU */ 1250 /* Description: Event Generator Unit 0 */ 1251 1252 /* Register: EGU_TASKS_TRIGGER */ 1253 /* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ 1254 1255 /* Bit 0 : */ 1256 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ 1257 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ 1258 1259 /* Register: EGU_EVENTS_TRIGGERED */ 1260 /* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ 1261 1262 /* Bit 0 : */ 1263 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ 1264 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ 1265 1266 /* Register: EGU_INTEN */ 1267 /* Description: Enable or disable interrupt */ 1268 1269 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ 1270 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1271 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1272 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ 1273 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ 1274 1275 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ 1276 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1277 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1278 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ 1279 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ 1280 1281 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ 1282 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1283 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1284 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ 1285 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ 1286 1287 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ 1288 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1289 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1290 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ 1291 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ 1292 1293 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ 1294 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1295 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1296 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ 1297 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ 1298 1299 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ 1300 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1301 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1302 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ 1303 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ 1304 1305 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ 1306 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1307 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1308 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ 1309 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ 1310 1311 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ 1312 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1313 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1314 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ 1315 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ 1316 1317 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ 1318 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1319 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1320 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ 1321 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ 1322 1323 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ 1324 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1325 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1326 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ 1327 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ 1328 1329 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ 1330 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1331 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1332 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ 1333 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ 1334 1335 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ 1336 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1337 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1338 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ 1339 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ 1340 1341 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ 1342 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1343 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1344 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ 1345 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ 1346 1347 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ 1348 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1349 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1350 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ 1351 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ 1352 1353 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ 1354 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1355 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1356 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ 1357 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ 1358 1359 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ 1360 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1361 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1362 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ 1363 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ 1364 1365 /* Register: EGU_INTENSET */ 1366 /* Description: Enable interrupt */ 1367 1368 /* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ 1369 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1370 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1371 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1372 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1373 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ 1374 1375 /* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ 1376 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1377 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1378 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 1379 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 1380 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ 1381 1382 /* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ 1383 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1384 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1385 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 1386 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 1387 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ 1388 1389 /* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ 1390 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1391 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1392 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 1393 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 1394 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ 1395 1396 /* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ 1397 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1398 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1399 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 1400 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 1401 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ 1402 1403 /* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ 1404 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1405 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1406 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 1407 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 1408 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ 1409 1410 /* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ 1411 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1412 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1413 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 1414 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 1415 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ 1416 1417 /* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ 1418 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1419 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1420 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 1421 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 1422 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ 1423 1424 /* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ 1425 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1426 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1427 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 1428 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 1429 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ 1430 1431 /* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ 1432 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1433 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1434 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 1435 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 1436 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ 1437 1438 /* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ 1439 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1440 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1441 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 1442 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 1443 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ 1444 1445 /* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ 1446 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1447 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1448 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 1449 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 1450 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ 1451 1452 /* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ 1453 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1454 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1455 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 1456 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 1457 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ 1458 1459 /* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ 1460 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1461 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1462 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 1463 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 1464 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ 1465 1466 /* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ 1467 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1468 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1469 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 1470 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 1471 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ 1472 1473 /* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ 1474 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1475 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1476 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1477 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1478 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ 1479 1480 /* Register: EGU_INTENCLR */ 1481 /* Description: Disable interrupt */ 1482 1483 /* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ 1484 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1485 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1486 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1487 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1488 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ 1489 1490 /* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ 1491 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 1492 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 1493 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 1494 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 1495 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ 1496 1497 /* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ 1498 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 1499 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 1500 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 1501 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 1502 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ 1503 1504 /* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ 1505 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 1506 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 1507 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 1508 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 1509 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ 1510 1511 /* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ 1512 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 1513 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 1514 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 1515 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 1516 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ 1517 1518 /* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ 1519 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 1520 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 1521 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 1522 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 1523 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ 1524 1525 /* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ 1526 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 1527 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 1528 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 1529 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 1530 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ 1531 1532 /* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ 1533 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 1534 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 1535 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 1536 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 1537 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ 1538 1539 /* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ 1540 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 1541 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 1542 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 1543 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 1544 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ 1545 1546 /* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ 1547 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 1548 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 1549 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 1550 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 1551 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ 1552 1553 /* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ 1554 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 1555 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 1556 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 1557 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 1558 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ 1559 1560 /* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ 1561 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 1562 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 1563 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 1564 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 1565 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ 1566 1567 /* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ 1568 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 1569 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 1570 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 1571 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 1572 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ 1573 1574 /* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ 1575 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 1576 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 1577 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 1578 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 1579 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ 1580 1581 /* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ 1582 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 1583 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 1584 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 1585 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 1586 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ 1587 1588 /* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ 1589 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1590 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1591 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1592 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1593 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ 1594 1595 1596 /* Peripheral: FICR */ 1597 /* Description: Factory information configuration registers */ 1598 1599 /* Register: FICR_CODEPAGESIZE */ 1600 /* Description: Code memory page size */ 1601 1602 /* Bits 31..0 : Code memory page size */ 1603 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ 1604 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ 1605 1606 /* Register: FICR_CODESIZE */ 1607 /* Description: Code memory size */ 1608 1609 /* Bits 31..0 : Code memory size in number of pages */ 1610 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ 1611 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ 1612 1613 /* Register: FICR_DEVICEID */ 1614 /* Description: Description collection[n]: Device identifier */ 1615 1616 /* Bits 31..0 : 64 bit unique device identifier */ 1617 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ 1618 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ 1619 1620 /* Register: FICR_ER */ 1621 /* Description: Description collection[n]: Encryption root, word n */ 1622 1623 /* Bits 31..0 : Encryption root, word n */ 1624 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ 1625 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ 1626 1627 /* Register: FICR_IR */ 1628 /* Description: Description collection[n]: Identity root, word n */ 1629 1630 /* Bits 31..0 : Identity root, word n */ 1631 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ 1632 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ 1633 1634 /* Register: FICR_DEVICEADDRTYPE */ 1635 /* Description: Device address type */ 1636 1637 /* Bit 0 : Device address type */ 1638 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ 1639 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ 1640 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ 1641 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ 1642 1643 /* Register: FICR_DEVICEADDR */ 1644 /* Description: Description collection[n]: Device address n */ 1645 1646 /* Bits 31..0 : 48 bit device address */ 1647 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ 1648 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ 1649 1650 /* Register: FICR_INFO_PART */ 1651 /* Description: Part code */ 1652 1653 /* Bits 31..0 : Part code */ 1654 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ 1655 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ 1656 #define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */ 1657 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1658 1659 /* Register: FICR_INFO_VARIANT */ 1660 /* Description: Part variant, hardware version and production configuration */ 1661 1662 /* Bits 31..0 : Part variant, hardware version and production configuration, encoded as ASCII */ 1663 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 1664 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 1665 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ 1666 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ 1667 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ 1668 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ 1669 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ 1670 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ 1671 #define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ 1672 #define FICR_INFO_VARIANT_VARIANT_AACB (0x41414342UL) /*!< AACB */ 1673 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1674 1675 /* Register: FICR_INFO_PACKAGE */ 1676 /* Description: Package option */ 1677 1678 /* Bits 31..0 : Package option */ 1679 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ 1680 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ 1681 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ 1682 #define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */ 1683 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1684 1685 /* Register: FICR_INFO_RAM */ 1686 /* Description: RAM variant */ 1687 1688 /* Bits 31..0 : RAM variant */ 1689 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 1690 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 1691 #define FICR_INFO_RAM_RAM_K24 (0x18UL) /*!< 24 kByte RAM */ 1692 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1693 1694 /* Register: FICR_INFO_FLASH */ 1695 /* Description: Flash variant */ 1696 1697 /* Bits 31..0 : Flash variant */ 1698 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 1699 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 1700 #define FICR_INFO_FLASH_FLASH_K192 (0xC0UL) /*!< 192 kByte flash */ 1701 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1702 1703 /* Register: FICR_TEMP_A0 */ 1704 /* Description: Slope definition A0 */ 1705 1706 /* Bits 11..0 : A (slope definition) register */ 1707 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ 1708 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ 1709 1710 /* Register: FICR_TEMP_A1 */ 1711 /* Description: Slope definition A1 */ 1712 1713 /* Bits 11..0 : A (slope definition) register */ 1714 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ 1715 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ 1716 1717 /* Register: FICR_TEMP_A2 */ 1718 /* Description: Slope definition A2 */ 1719 1720 /* Bits 11..0 : A (slope definition) register */ 1721 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ 1722 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ 1723 1724 /* Register: FICR_TEMP_A3 */ 1725 /* Description: Slope definition A3 */ 1726 1727 /* Bits 11..0 : A (slope definition) register */ 1728 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ 1729 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ 1730 1731 /* Register: FICR_TEMP_A4 */ 1732 /* Description: Slope definition A4 */ 1733 1734 /* Bits 11..0 : A (slope definition) register */ 1735 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ 1736 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ 1737 1738 /* Register: FICR_TEMP_A5 */ 1739 /* Description: Slope definition A5 */ 1740 1741 /* Bits 11..0 : A (slope definition) register */ 1742 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ 1743 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ 1744 1745 /* Register: FICR_TEMP_B0 */ 1746 /* Description: Y-intercept B0 */ 1747 1748 /* Bits 13..0 : B (y-intercept) */ 1749 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ 1750 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ 1751 1752 /* Register: FICR_TEMP_B1 */ 1753 /* Description: Y-intercept B1 */ 1754 1755 /* Bits 13..0 : B (y-intercept) */ 1756 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ 1757 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ 1758 1759 /* Register: FICR_TEMP_B2 */ 1760 /* Description: Y-intercept B2 */ 1761 1762 /* Bits 13..0 : B (y-intercept) */ 1763 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ 1764 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ 1765 1766 /* Register: FICR_TEMP_B3 */ 1767 /* Description: Y-intercept B3 */ 1768 1769 /* Bits 13..0 : B (y-intercept) */ 1770 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ 1771 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ 1772 1773 /* Register: FICR_TEMP_B4 */ 1774 /* Description: Y-intercept B4 */ 1775 1776 /* Bits 13..0 : B (y-intercept) */ 1777 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ 1778 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ 1779 1780 /* Register: FICR_TEMP_B5 */ 1781 /* Description: Y-intercept B5 */ 1782 1783 /* Bits 13..0 : B (y-intercept) */ 1784 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ 1785 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ 1786 1787 /* Register: FICR_TEMP_T0 */ 1788 /* Description: Segment end T0 */ 1789 1790 /* Bits 7..0 : T (segment end) register */ 1791 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ 1792 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ 1793 1794 /* Register: FICR_TEMP_T1 */ 1795 /* Description: Segment end T1 */ 1796 1797 /* Bits 7..0 : T (segment end) register */ 1798 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ 1799 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ 1800 1801 /* Register: FICR_TEMP_T2 */ 1802 /* Description: Segment end T2 */ 1803 1804 /* Bits 7..0 : T (segment end) register */ 1805 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ 1806 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ 1807 1808 /* Register: FICR_TEMP_T3 */ 1809 /* Description: Segment end T3 */ 1810 1811 /* Bits 7..0 : T (segment end) register */ 1812 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ 1813 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ 1814 1815 /* Register: FICR_TEMP_T4 */ 1816 /* Description: Segment end T4 */ 1817 1818 /* Bits 7..0 : T (segment end) register */ 1819 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ 1820 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ 1821 1822 1823 /* Peripheral: GPIOTE */ 1824 /* Description: GPIO Tasks and Events */ 1825 1826 /* Register: GPIOTE_TASKS_OUT */ 1827 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 1828 1829 /* Bit 0 : */ 1830 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ 1831 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ 1832 1833 /* Register: GPIOTE_TASKS_SET */ 1834 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 1835 1836 /* Bit 0 : */ 1837 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ 1838 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ 1839 1840 /* Register: GPIOTE_TASKS_CLR */ 1841 /* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 1842 1843 /* Bit 0 : */ 1844 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ 1845 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ 1846 1847 /* Register: GPIOTE_EVENTS_IN */ 1848 /* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ 1849 1850 /* Bit 0 : */ 1851 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ 1852 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ 1853 1854 /* Register: GPIOTE_EVENTS_PORT */ 1855 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 1856 1857 /* Bit 0 : */ 1858 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ 1859 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ 1860 1861 /* Register: GPIOTE_INTENSET */ 1862 /* Description: Enable interrupt */ 1863 1864 /* Bit 31 : Write '1' to enable interrupt for PORT event */ 1865 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 1866 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 1867 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ 1868 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ 1869 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ 1870 1871 /* Bit 7 : Write '1' to enable interrupt for IN[7] event */ 1872 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ 1873 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ 1874 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ 1875 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ 1876 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ 1877 1878 /* Bit 6 : Write '1' to enable interrupt for IN[6] event */ 1879 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ 1880 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ 1881 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ 1882 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ 1883 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ 1884 1885 /* Bit 5 : Write '1' to enable interrupt for IN[5] event */ 1886 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ 1887 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ 1888 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ 1889 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ 1890 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ 1891 1892 /* Bit 4 : Write '1' to enable interrupt for IN[4] event */ 1893 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ 1894 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ 1895 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ 1896 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ 1897 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ 1898 1899 /* Bit 3 : Write '1' to enable interrupt for IN[3] event */ 1900 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 1901 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 1902 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ 1903 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ 1904 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ 1905 1906 /* Bit 2 : Write '1' to enable interrupt for IN[2] event */ 1907 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 1908 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 1909 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ 1910 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ 1911 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ 1912 1913 /* Bit 1 : Write '1' to enable interrupt for IN[1] event */ 1914 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 1915 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 1916 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ 1917 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ 1918 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ 1919 1920 /* Bit 0 : Write '1' to enable interrupt for IN[0] event */ 1921 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 1922 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 1923 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ 1924 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ 1925 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ 1926 1927 /* Register: GPIOTE_INTENCLR */ 1928 /* Description: Disable interrupt */ 1929 1930 /* Bit 31 : Write '1' to disable interrupt for PORT event */ 1931 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 1932 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 1933 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ 1934 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ 1935 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ 1936 1937 /* Bit 7 : Write '1' to disable interrupt for IN[7] event */ 1938 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ 1939 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ 1940 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ 1941 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ 1942 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ 1943 1944 /* Bit 6 : Write '1' to disable interrupt for IN[6] event */ 1945 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ 1946 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ 1947 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ 1948 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ 1949 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ 1950 1951 /* Bit 5 : Write '1' to disable interrupt for IN[5] event */ 1952 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ 1953 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ 1954 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ 1955 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ 1956 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ 1957 1958 /* Bit 4 : Write '1' to disable interrupt for IN[4] event */ 1959 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ 1960 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ 1961 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ 1962 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ 1963 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ 1964 1965 /* Bit 3 : Write '1' to disable interrupt for IN[3] event */ 1966 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 1967 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 1968 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ 1969 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ 1970 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ 1971 1972 /* Bit 2 : Write '1' to disable interrupt for IN[2] event */ 1973 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 1974 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 1975 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ 1976 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ 1977 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ 1978 1979 /* Bit 1 : Write '1' to disable interrupt for IN[1] event */ 1980 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 1981 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 1982 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ 1983 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ 1984 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ 1985 1986 /* Bit 0 : Write '1' to disable interrupt for IN[0] event */ 1987 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 1988 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 1989 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ 1990 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ 1991 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ 1992 1993 /* Register: GPIOTE_CONFIG */ 1994 /* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ 1995 1996 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ 1997 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 1998 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 1999 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ 2000 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ 2001 2002 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ 2003 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 2004 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 2005 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ 2006 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ 2007 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ 2008 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ 2009 2010 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ 2011 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 2012 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 2013 2014 /* Bits 1..0 : Mode */ 2015 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 2016 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 2017 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ 2018 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ 2019 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ 2020 2021 2022 /* Peripheral: NVMC */ 2023 /* Description: Non-volatile memory controller */ 2024 2025 /* Register: NVMC_READY */ 2026 /* Description: Ready flag */ 2027 2028 /* Bit 0 : NVMC is ready or busy */ 2029 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 2030 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 2031 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ 2032 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ 2033 2034 /* Register: NVMC_CONFIG */ 2035 /* Description: Configuration register */ 2036 2037 /* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. */ 2038 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 2039 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 2040 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ 2041 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ 2042 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ 2043 2044 /* Register: NVMC_ERASEPAGE */ 2045 /* Description: Register for erasing a page in code area */ 2046 2047 /* Bits 31..0 : Register for starting erase of a page in code area. */ 2048 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ 2049 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ 2050 2051 /* Register: NVMC_ERASEPCR1 */ 2052 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ 2053 2054 /* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ 2055 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ 2056 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ 2057 2058 /* Register: NVMC_ERASEALL */ 2059 /* Description: Register for erasing all non-volatile user memory */ 2060 2061 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ 2062 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 2063 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 2064 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ 2065 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start erase of chip */ 2066 2067 /* Register: NVMC_ERASEPCR0 */ 2068 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ 2069 2070 /* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ 2071 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ 2072 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ 2073 2074 /* Register: NVMC_ERASEUICR */ 2075 /* Description: Register for erasing user information configuration registers */ 2076 2077 /* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ 2078 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ 2079 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ 2080 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ 2081 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ 2082 2083 /* Register: NVMC_ERASEPAGEPARTIAL */ 2084 /* Description: Register for partial erase of a page in code area */ 2085 2086 /* Bits 31..0 : Register for starting partial erase of a page in code area */ 2087 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ 2088 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ 2089 2090 /* Register: NVMC_ERASEPAGEPARTIALCFG */ 2091 /* Description: Register for partial erase configuration */ 2092 2093 /* Bits 6..0 : Duration of the partial erase in milliseconds */ 2094 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ 2095 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ 2096 2097 2098 /* Peripheral: GPIO */ 2099 /* Description: GPIO Port */ 2100 2101 /* Register: GPIO_OUT */ 2102 /* Description: Write GPIO port */ 2103 2104 /* Bit 31 : Pin 31 */ 2105 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2106 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2107 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ 2108 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ 2109 2110 /* Bit 30 : Pin 30 */ 2111 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2112 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2113 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ 2114 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ 2115 2116 /* Bit 29 : Pin 29 */ 2117 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2118 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2119 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ 2120 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ 2121 2122 /* Bit 28 : Pin 28 */ 2123 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2124 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2125 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ 2126 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ 2127 2128 /* Bit 27 : Pin 27 */ 2129 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2130 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2131 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ 2132 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ 2133 2134 /* Bit 26 : Pin 26 */ 2135 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2136 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2137 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ 2138 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ 2139 2140 /* Bit 25 : Pin 25 */ 2141 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2142 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2143 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ 2144 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ 2145 2146 /* Bit 24 : Pin 24 */ 2147 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2148 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2149 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ 2150 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ 2151 2152 /* Bit 23 : Pin 23 */ 2153 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2154 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2155 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ 2156 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ 2157 2158 /* Bit 22 : Pin 22 */ 2159 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2160 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2161 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ 2162 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ 2163 2164 /* Bit 21 : Pin 21 */ 2165 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2166 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2167 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ 2168 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ 2169 2170 /* Bit 20 : Pin 20 */ 2171 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2172 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2173 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ 2174 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ 2175 2176 /* Bit 19 : Pin 19 */ 2177 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2178 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2179 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ 2180 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ 2181 2182 /* Bit 18 : Pin 18 */ 2183 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2184 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2185 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ 2186 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ 2187 2188 /* Bit 17 : Pin 17 */ 2189 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2190 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2191 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ 2192 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ 2193 2194 /* Bit 16 : Pin 16 */ 2195 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2196 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2197 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ 2198 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ 2199 2200 /* Bit 15 : Pin 15 */ 2201 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2202 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2203 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ 2204 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ 2205 2206 /* Bit 14 : Pin 14 */ 2207 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2208 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2209 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ 2210 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ 2211 2212 /* Bit 13 : Pin 13 */ 2213 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2214 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2215 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ 2216 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ 2217 2218 /* Bit 12 : Pin 12 */ 2219 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2220 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2221 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ 2222 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ 2223 2224 /* Bit 11 : Pin 11 */ 2225 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2226 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2227 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ 2228 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ 2229 2230 /* Bit 10 : Pin 10 */ 2231 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2232 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2233 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ 2234 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ 2235 2236 /* Bit 9 : Pin 9 */ 2237 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2238 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2239 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ 2240 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ 2241 2242 /* Bit 8 : Pin 8 */ 2243 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2244 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2245 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ 2246 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ 2247 2248 /* Bit 7 : Pin 7 */ 2249 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2250 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2251 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ 2252 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ 2253 2254 /* Bit 6 : Pin 6 */ 2255 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2256 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2257 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ 2258 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ 2259 2260 /* Bit 5 : Pin 5 */ 2261 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2262 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2263 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ 2264 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ 2265 2266 /* Bit 4 : Pin 4 */ 2267 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2268 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2269 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ 2270 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ 2271 2272 /* Bit 3 : Pin 3 */ 2273 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2274 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2275 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ 2276 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ 2277 2278 /* Bit 2 : Pin 2 */ 2279 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2280 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2281 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ 2282 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ 2283 2284 /* Bit 1 : Pin 1 */ 2285 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2286 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2287 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ 2288 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ 2289 2290 /* Bit 0 : Pin 0 */ 2291 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2292 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2293 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ 2294 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ 2295 2296 /* Register: GPIO_OUTSET */ 2297 /* Description: Set individual bits in GPIO port */ 2298 2299 /* Bit 31 : Pin 31 */ 2300 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2301 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2302 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ 2303 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ 2304 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2305 2306 /* Bit 30 : Pin 30 */ 2307 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2308 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2309 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ 2310 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ 2311 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2312 2313 /* Bit 29 : Pin 29 */ 2314 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2315 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2316 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ 2317 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ 2318 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2319 2320 /* Bit 28 : Pin 28 */ 2321 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2322 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2323 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ 2324 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ 2325 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2326 2327 /* Bit 27 : Pin 27 */ 2328 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2329 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2330 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ 2331 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ 2332 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2333 2334 /* Bit 26 : Pin 26 */ 2335 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2336 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2337 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ 2338 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ 2339 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2340 2341 /* Bit 25 : Pin 25 */ 2342 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2343 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2344 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ 2345 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ 2346 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2347 2348 /* Bit 24 : Pin 24 */ 2349 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2350 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2351 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ 2352 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ 2353 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2354 2355 /* Bit 23 : Pin 23 */ 2356 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2357 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2358 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ 2359 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ 2360 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2361 2362 /* Bit 22 : Pin 22 */ 2363 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2364 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2365 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ 2366 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ 2367 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2368 2369 /* Bit 21 : Pin 21 */ 2370 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2371 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2372 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ 2373 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ 2374 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2375 2376 /* Bit 20 : Pin 20 */ 2377 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2378 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2379 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ 2380 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ 2381 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2382 2383 /* Bit 19 : Pin 19 */ 2384 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2385 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2386 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ 2387 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ 2388 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2389 2390 /* Bit 18 : Pin 18 */ 2391 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2392 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2393 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ 2394 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ 2395 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2396 2397 /* Bit 17 : Pin 17 */ 2398 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2399 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2400 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ 2401 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ 2402 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2403 2404 /* Bit 16 : Pin 16 */ 2405 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2406 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2407 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ 2408 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ 2409 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2410 2411 /* Bit 15 : Pin 15 */ 2412 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2413 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2414 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ 2415 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ 2416 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2417 2418 /* Bit 14 : Pin 14 */ 2419 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2420 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2421 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ 2422 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ 2423 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2424 2425 /* Bit 13 : Pin 13 */ 2426 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2427 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2428 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ 2429 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ 2430 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2431 2432 /* Bit 12 : Pin 12 */ 2433 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2434 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2435 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ 2436 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ 2437 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2438 2439 /* Bit 11 : Pin 11 */ 2440 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2441 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2442 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ 2443 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ 2444 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2445 2446 /* Bit 10 : Pin 10 */ 2447 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2448 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2449 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ 2450 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ 2451 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2452 2453 /* Bit 9 : Pin 9 */ 2454 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2455 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2456 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ 2457 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ 2458 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2459 2460 /* Bit 8 : Pin 8 */ 2461 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2462 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2463 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ 2464 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ 2465 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2466 2467 /* Bit 7 : Pin 7 */ 2468 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2469 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2470 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ 2471 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ 2472 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2473 2474 /* Bit 6 : Pin 6 */ 2475 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2476 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2477 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ 2478 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ 2479 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2480 2481 /* Bit 5 : Pin 5 */ 2482 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2483 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2484 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ 2485 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ 2486 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2487 2488 /* Bit 4 : Pin 4 */ 2489 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2490 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2491 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ 2492 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ 2493 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2494 2495 /* Bit 3 : Pin 3 */ 2496 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2497 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2498 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ 2499 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ 2500 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2501 2502 /* Bit 2 : Pin 2 */ 2503 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2504 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2505 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ 2506 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ 2507 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2508 2509 /* Bit 1 : Pin 1 */ 2510 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2511 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2512 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ 2513 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ 2514 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2515 2516 /* Bit 0 : Pin 0 */ 2517 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2518 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2519 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ 2520 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ 2521 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 2522 2523 /* Register: GPIO_OUTCLR */ 2524 /* Description: Clear individual bits in GPIO port */ 2525 2526 /* Bit 31 : Pin 31 */ 2527 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2528 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2529 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ 2530 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ 2531 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2532 2533 /* Bit 30 : Pin 30 */ 2534 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2535 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2536 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ 2537 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ 2538 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2539 2540 /* Bit 29 : Pin 29 */ 2541 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2542 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2543 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ 2544 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ 2545 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2546 2547 /* Bit 28 : Pin 28 */ 2548 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2549 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2550 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ 2551 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ 2552 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2553 2554 /* Bit 27 : Pin 27 */ 2555 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2556 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2557 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ 2558 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ 2559 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2560 2561 /* Bit 26 : Pin 26 */ 2562 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2563 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2564 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ 2565 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ 2566 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2567 2568 /* Bit 25 : Pin 25 */ 2569 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2570 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2571 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ 2572 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ 2573 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2574 2575 /* Bit 24 : Pin 24 */ 2576 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2577 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2578 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ 2579 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ 2580 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2581 2582 /* Bit 23 : Pin 23 */ 2583 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2584 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2585 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ 2586 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ 2587 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2588 2589 /* Bit 22 : Pin 22 */ 2590 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2591 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2592 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ 2593 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ 2594 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2595 2596 /* Bit 21 : Pin 21 */ 2597 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2598 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2599 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ 2600 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ 2601 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2602 2603 /* Bit 20 : Pin 20 */ 2604 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2605 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2606 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ 2607 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ 2608 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2609 2610 /* Bit 19 : Pin 19 */ 2611 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2612 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2613 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ 2614 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ 2615 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2616 2617 /* Bit 18 : Pin 18 */ 2618 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2619 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2620 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ 2621 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ 2622 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2623 2624 /* Bit 17 : Pin 17 */ 2625 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2626 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2627 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ 2628 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ 2629 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2630 2631 /* Bit 16 : Pin 16 */ 2632 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2633 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2634 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ 2635 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ 2636 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2637 2638 /* Bit 15 : Pin 15 */ 2639 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2640 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2641 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ 2642 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ 2643 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2644 2645 /* Bit 14 : Pin 14 */ 2646 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2647 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2648 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ 2649 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ 2650 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2651 2652 /* Bit 13 : Pin 13 */ 2653 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2654 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2655 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ 2656 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ 2657 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2658 2659 /* Bit 12 : Pin 12 */ 2660 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2661 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2662 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ 2663 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ 2664 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2665 2666 /* Bit 11 : Pin 11 */ 2667 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2668 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2669 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ 2670 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ 2671 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2672 2673 /* Bit 10 : Pin 10 */ 2674 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2675 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2676 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ 2677 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ 2678 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2679 2680 /* Bit 9 : Pin 9 */ 2681 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2682 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2683 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ 2684 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ 2685 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2686 2687 /* Bit 8 : Pin 8 */ 2688 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2689 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2690 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ 2691 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ 2692 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2693 2694 /* Bit 7 : Pin 7 */ 2695 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2696 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2697 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ 2698 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ 2699 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2700 2701 /* Bit 6 : Pin 6 */ 2702 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2703 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2704 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ 2705 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ 2706 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2707 2708 /* Bit 5 : Pin 5 */ 2709 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2710 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2711 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ 2712 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ 2713 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2714 2715 /* Bit 4 : Pin 4 */ 2716 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2717 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2718 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ 2719 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ 2720 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2721 2722 /* Bit 3 : Pin 3 */ 2723 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2724 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2725 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ 2726 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ 2727 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2728 2729 /* Bit 2 : Pin 2 */ 2730 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2731 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2732 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ 2733 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ 2734 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2735 2736 /* Bit 1 : Pin 1 */ 2737 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2738 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2739 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ 2740 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ 2741 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2742 2743 /* Bit 0 : Pin 0 */ 2744 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2745 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2746 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ 2747 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ 2748 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 2749 2750 /* Register: GPIO_IN */ 2751 /* Description: Read GPIO port */ 2752 2753 /* Bit 31 : Pin 31 */ 2754 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2755 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2756 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ 2757 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ 2758 2759 /* Bit 30 : Pin 30 */ 2760 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2761 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2762 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ 2763 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ 2764 2765 /* Bit 29 : Pin 29 */ 2766 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2767 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2768 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ 2769 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ 2770 2771 /* Bit 28 : Pin 28 */ 2772 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2773 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2774 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ 2775 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ 2776 2777 /* Bit 27 : Pin 27 */ 2778 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2779 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2780 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ 2781 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ 2782 2783 /* Bit 26 : Pin 26 */ 2784 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2785 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2786 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ 2787 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ 2788 2789 /* Bit 25 : Pin 25 */ 2790 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2791 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2792 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ 2793 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ 2794 2795 /* Bit 24 : Pin 24 */ 2796 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2797 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2798 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ 2799 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ 2800 2801 /* Bit 23 : Pin 23 */ 2802 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2803 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2804 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ 2805 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ 2806 2807 /* Bit 22 : Pin 22 */ 2808 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2809 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2810 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ 2811 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ 2812 2813 /* Bit 21 : Pin 21 */ 2814 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2815 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2816 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ 2817 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ 2818 2819 /* Bit 20 : Pin 20 */ 2820 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2821 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2822 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ 2823 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ 2824 2825 /* Bit 19 : Pin 19 */ 2826 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2827 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2828 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ 2829 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ 2830 2831 /* Bit 18 : Pin 18 */ 2832 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2833 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2834 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ 2835 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ 2836 2837 /* Bit 17 : Pin 17 */ 2838 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2839 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2840 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ 2841 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ 2842 2843 /* Bit 16 : Pin 16 */ 2844 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2845 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2846 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ 2847 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ 2848 2849 /* Bit 15 : Pin 15 */ 2850 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2851 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2852 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ 2853 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ 2854 2855 /* Bit 14 : Pin 14 */ 2856 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2857 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2858 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ 2859 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ 2860 2861 /* Bit 13 : Pin 13 */ 2862 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2863 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2864 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ 2865 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ 2866 2867 /* Bit 12 : Pin 12 */ 2868 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2869 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2870 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ 2871 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ 2872 2873 /* Bit 11 : Pin 11 */ 2874 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2875 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2876 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ 2877 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ 2878 2879 /* Bit 10 : Pin 10 */ 2880 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2881 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2882 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ 2883 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ 2884 2885 /* Bit 9 : Pin 9 */ 2886 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2887 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2888 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ 2889 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ 2890 2891 /* Bit 8 : Pin 8 */ 2892 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2893 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2894 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ 2895 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ 2896 2897 /* Bit 7 : Pin 7 */ 2898 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2899 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2900 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ 2901 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ 2902 2903 /* Bit 6 : Pin 6 */ 2904 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2905 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2906 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ 2907 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ 2908 2909 /* Bit 5 : Pin 5 */ 2910 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2911 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2912 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ 2913 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ 2914 2915 /* Bit 4 : Pin 4 */ 2916 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2917 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2918 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ 2919 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ 2920 2921 /* Bit 3 : Pin 3 */ 2922 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2923 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2924 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ 2925 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ 2926 2927 /* Bit 2 : Pin 2 */ 2928 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2929 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2930 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ 2931 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ 2932 2933 /* Bit 1 : Pin 1 */ 2934 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2935 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2936 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ 2937 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ 2938 2939 /* Bit 0 : Pin 0 */ 2940 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2941 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2942 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ 2943 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ 2944 2945 /* Register: GPIO_DIR */ 2946 /* Description: Direction of GPIO pins */ 2947 2948 /* Bit 31 : Pin 31 */ 2949 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2950 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2951 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ 2952 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ 2953 2954 /* Bit 30 : Pin 30 */ 2955 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2956 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2957 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ 2958 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ 2959 2960 /* Bit 29 : Pin 29 */ 2961 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2962 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2963 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ 2964 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ 2965 2966 /* Bit 28 : Pin 28 */ 2967 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2968 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2969 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ 2970 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ 2971 2972 /* Bit 27 : Pin 27 */ 2973 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2974 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2975 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ 2976 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ 2977 2978 /* Bit 26 : Pin 26 */ 2979 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2980 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2981 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ 2982 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ 2983 2984 /* Bit 25 : Pin 25 */ 2985 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2986 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2987 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ 2988 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ 2989 2990 /* Bit 24 : Pin 24 */ 2991 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2992 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2993 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ 2994 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ 2995 2996 /* Bit 23 : Pin 23 */ 2997 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2998 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2999 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ 3000 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ 3001 3002 /* Bit 22 : Pin 22 */ 3003 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3004 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3005 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ 3006 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ 3007 3008 /* Bit 21 : Pin 21 */ 3009 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3010 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3011 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ 3012 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ 3013 3014 /* Bit 20 : Pin 20 */ 3015 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3016 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3017 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ 3018 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ 3019 3020 /* Bit 19 : Pin 19 */ 3021 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3022 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3023 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ 3024 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ 3025 3026 /* Bit 18 : Pin 18 */ 3027 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3028 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3029 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ 3030 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ 3031 3032 /* Bit 17 : Pin 17 */ 3033 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3034 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3035 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ 3036 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ 3037 3038 /* Bit 16 : Pin 16 */ 3039 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3040 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3041 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ 3042 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ 3043 3044 /* Bit 15 : Pin 15 */ 3045 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3046 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3047 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ 3048 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ 3049 3050 /* Bit 14 : Pin 14 */ 3051 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3052 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3053 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ 3054 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ 3055 3056 /* Bit 13 : Pin 13 */ 3057 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3058 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3059 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ 3060 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ 3061 3062 /* Bit 12 : Pin 12 */ 3063 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3064 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3065 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ 3066 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ 3067 3068 /* Bit 11 : Pin 11 */ 3069 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3070 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3071 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ 3072 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ 3073 3074 /* Bit 10 : Pin 10 */ 3075 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3076 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3077 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ 3078 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ 3079 3080 /* Bit 9 : Pin 9 */ 3081 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3082 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3083 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ 3084 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ 3085 3086 /* Bit 8 : Pin 8 */ 3087 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3088 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3089 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ 3090 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ 3091 3092 /* Bit 7 : Pin 7 */ 3093 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3094 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3095 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ 3096 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ 3097 3098 /* Bit 6 : Pin 6 */ 3099 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3100 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3101 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ 3102 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ 3103 3104 /* Bit 5 : Pin 5 */ 3105 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3106 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3107 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ 3108 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ 3109 3110 /* Bit 4 : Pin 4 */ 3111 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3112 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3113 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ 3114 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ 3115 3116 /* Bit 3 : Pin 3 */ 3117 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3118 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3119 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ 3120 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ 3121 3122 /* Bit 2 : Pin 2 */ 3123 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3124 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3125 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ 3126 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ 3127 3128 /* Bit 1 : Pin 1 */ 3129 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3130 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3131 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ 3132 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ 3133 3134 /* Bit 0 : Pin 0 */ 3135 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3136 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3137 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ 3138 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ 3139 3140 /* Register: GPIO_DIRSET */ 3141 /* Description: DIR set register */ 3142 3143 /* Bit 31 : Set as output pin 31 */ 3144 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3145 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3146 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ 3147 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ 3148 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3149 3150 /* Bit 30 : Set as output pin 30 */ 3151 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3152 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3153 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ 3154 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ 3155 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3156 3157 /* Bit 29 : Set as output pin 29 */ 3158 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3159 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3160 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ 3161 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ 3162 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3163 3164 /* Bit 28 : Set as output pin 28 */ 3165 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3166 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3167 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ 3168 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ 3169 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3170 3171 /* Bit 27 : Set as output pin 27 */ 3172 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3173 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3174 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ 3175 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ 3176 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3177 3178 /* Bit 26 : Set as output pin 26 */ 3179 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3180 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3181 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ 3182 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ 3183 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3184 3185 /* Bit 25 : Set as output pin 25 */ 3186 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3187 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3188 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ 3189 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ 3190 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3191 3192 /* Bit 24 : Set as output pin 24 */ 3193 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3194 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3195 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ 3196 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ 3197 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3198 3199 /* Bit 23 : Set as output pin 23 */ 3200 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3201 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3202 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ 3203 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ 3204 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3205 3206 /* Bit 22 : Set as output pin 22 */ 3207 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3208 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3209 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ 3210 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ 3211 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3212 3213 /* Bit 21 : Set as output pin 21 */ 3214 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3215 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3216 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ 3217 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ 3218 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3219 3220 /* Bit 20 : Set as output pin 20 */ 3221 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3222 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3223 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ 3224 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ 3225 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3226 3227 /* Bit 19 : Set as output pin 19 */ 3228 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3229 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3230 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ 3231 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ 3232 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3233 3234 /* Bit 18 : Set as output pin 18 */ 3235 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3236 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3237 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ 3238 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ 3239 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3240 3241 /* Bit 17 : Set as output pin 17 */ 3242 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3243 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3244 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ 3245 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ 3246 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3247 3248 /* Bit 16 : Set as output pin 16 */ 3249 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3250 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3251 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ 3252 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ 3253 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3254 3255 /* Bit 15 : Set as output pin 15 */ 3256 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3257 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3258 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ 3259 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ 3260 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3261 3262 /* Bit 14 : Set as output pin 14 */ 3263 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3264 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3265 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ 3266 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ 3267 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3268 3269 /* Bit 13 : Set as output pin 13 */ 3270 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3271 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3272 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ 3273 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ 3274 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3275 3276 /* Bit 12 : Set as output pin 12 */ 3277 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3278 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3279 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ 3280 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ 3281 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3282 3283 /* Bit 11 : Set as output pin 11 */ 3284 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3285 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3286 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ 3287 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ 3288 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3289 3290 /* Bit 10 : Set as output pin 10 */ 3291 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3292 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3293 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ 3294 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ 3295 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3296 3297 /* Bit 9 : Set as output pin 9 */ 3298 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3299 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3300 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ 3301 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ 3302 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3303 3304 /* Bit 8 : Set as output pin 8 */ 3305 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3306 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3307 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ 3308 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ 3309 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3310 3311 /* Bit 7 : Set as output pin 7 */ 3312 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3313 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3314 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ 3315 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ 3316 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3317 3318 /* Bit 6 : Set as output pin 6 */ 3319 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3320 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3321 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ 3322 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ 3323 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3324 3325 /* Bit 5 : Set as output pin 5 */ 3326 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3327 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3328 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ 3329 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ 3330 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3331 3332 /* Bit 4 : Set as output pin 4 */ 3333 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3334 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3335 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ 3336 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ 3337 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3338 3339 /* Bit 3 : Set as output pin 3 */ 3340 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3341 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3342 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ 3343 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ 3344 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3345 3346 /* Bit 2 : Set as output pin 2 */ 3347 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3348 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3349 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ 3350 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ 3351 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3352 3353 /* Bit 1 : Set as output pin 1 */ 3354 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3355 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3356 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ 3357 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ 3358 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3359 3360 /* Bit 0 : Set as output pin 0 */ 3361 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3362 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3363 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ 3364 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ 3365 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 3366 3367 /* Register: GPIO_DIRCLR */ 3368 /* Description: DIR clear register */ 3369 3370 /* Bit 31 : Set as input pin 31 */ 3371 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3372 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3373 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ 3374 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ 3375 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3376 3377 /* Bit 30 : Set as input pin 30 */ 3378 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3379 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3380 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ 3381 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ 3382 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3383 3384 /* Bit 29 : Set as input pin 29 */ 3385 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3386 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3387 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ 3388 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ 3389 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3390 3391 /* Bit 28 : Set as input pin 28 */ 3392 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3393 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3394 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ 3395 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ 3396 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3397 3398 /* Bit 27 : Set as input pin 27 */ 3399 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3400 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3401 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ 3402 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ 3403 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3404 3405 /* Bit 26 : Set as input pin 26 */ 3406 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3407 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3408 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ 3409 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ 3410 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3411 3412 /* Bit 25 : Set as input pin 25 */ 3413 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3414 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3415 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ 3416 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ 3417 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3418 3419 /* Bit 24 : Set as input pin 24 */ 3420 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3421 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3422 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ 3423 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ 3424 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3425 3426 /* Bit 23 : Set as input pin 23 */ 3427 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3428 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3429 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ 3430 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ 3431 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3432 3433 /* Bit 22 : Set as input pin 22 */ 3434 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3435 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3436 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ 3437 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ 3438 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3439 3440 /* Bit 21 : Set as input pin 21 */ 3441 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3442 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3443 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ 3444 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ 3445 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3446 3447 /* Bit 20 : Set as input pin 20 */ 3448 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3449 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3450 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ 3451 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ 3452 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3453 3454 /* Bit 19 : Set as input pin 19 */ 3455 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3456 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3457 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ 3458 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ 3459 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3460 3461 /* Bit 18 : Set as input pin 18 */ 3462 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3463 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3464 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ 3465 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ 3466 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3467 3468 /* Bit 17 : Set as input pin 17 */ 3469 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3470 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3471 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ 3472 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ 3473 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3474 3475 /* Bit 16 : Set as input pin 16 */ 3476 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3477 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3478 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ 3479 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ 3480 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3481 3482 /* Bit 15 : Set as input pin 15 */ 3483 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3484 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3485 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ 3486 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ 3487 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3488 3489 /* Bit 14 : Set as input pin 14 */ 3490 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3491 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3492 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ 3493 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ 3494 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3495 3496 /* Bit 13 : Set as input pin 13 */ 3497 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3498 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3499 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ 3500 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ 3501 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3502 3503 /* Bit 12 : Set as input pin 12 */ 3504 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3505 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3506 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ 3507 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ 3508 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3509 3510 /* Bit 11 : Set as input pin 11 */ 3511 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3512 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3513 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ 3514 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ 3515 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3516 3517 /* Bit 10 : Set as input pin 10 */ 3518 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3519 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3520 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ 3521 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ 3522 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3523 3524 /* Bit 9 : Set as input pin 9 */ 3525 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3526 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3527 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ 3528 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ 3529 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3530 3531 /* Bit 8 : Set as input pin 8 */ 3532 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3533 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3534 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ 3535 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ 3536 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3537 3538 /* Bit 7 : Set as input pin 7 */ 3539 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3540 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3541 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ 3542 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ 3543 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3544 3545 /* Bit 6 : Set as input pin 6 */ 3546 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3547 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3548 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ 3549 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ 3550 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3551 3552 /* Bit 5 : Set as input pin 5 */ 3553 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3554 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3555 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ 3556 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ 3557 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3558 3559 /* Bit 4 : Set as input pin 4 */ 3560 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3561 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3562 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ 3563 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ 3564 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3565 3566 /* Bit 3 : Set as input pin 3 */ 3567 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3568 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3569 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ 3570 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ 3571 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3572 3573 /* Bit 2 : Set as input pin 2 */ 3574 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3575 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3576 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ 3577 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ 3578 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3579 3580 /* Bit 1 : Set as input pin 1 */ 3581 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3582 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3583 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ 3584 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ 3585 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3586 3587 /* Bit 0 : Set as input pin 0 */ 3588 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3589 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3590 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ 3591 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ 3592 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 3593 3594 /* Register: GPIO_LATCH */ 3595 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ 3596 3597 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ 3598 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 3599 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 3600 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ 3601 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ 3602 3603 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ 3604 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 3605 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 3606 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ 3607 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ 3608 3609 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ 3610 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 3611 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 3612 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ 3613 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ 3614 3615 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ 3616 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 3617 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 3618 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ 3619 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ 3620 3621 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ 3622 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 3623 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 3624 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ 3625 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ 3626 3627 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ 3628 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 3629 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 3630 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ 3631 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ 3632 3633 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ 3634 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 3635 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 3636 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ 3637 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ 3638 3639 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ 3640 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 3641 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 3642 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ 3643 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ 3644 3645 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ 3646 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 3647 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 3648 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ 3649 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ 3650 3651 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ 3652 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 3653 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 3654 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ 3655 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ 3656 3657 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ 3658 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 3659 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 3660 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ 3661 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ 3662 3663 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ 3664 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 3665 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 3666 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ 3667 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ 3668 3669 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ 3670 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 3671 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 3672 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ 3673 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ 3674 3675 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ 3676 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 3677 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 3678 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ 3679 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ 3680 3681 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ 3682 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 3683 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 3684 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ 3685 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ 3686 3687 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ 3688 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 3689 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 3690 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ 3691 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ 3692 3693 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ 3694 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 3695 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 3696 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ 3697 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ 3698 3699 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ 3700 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 3701 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 3702 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ 3703 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ 3704 3705 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ 3706 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 3707 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 3708 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ 3709 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ 3710 3711 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ 3712 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 3713 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 3714 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ 3715 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ 3716 3717 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ 3718 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 3719 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 3720 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ 3721 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ 3722 3723 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ 3724 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 3725 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 3726 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ 3727 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ 3728 3729 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ 3730 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 3731 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 3732 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ 3733 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ 3734 3735 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ 3736 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 3737 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 3738 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ 3739 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ 3740 3741 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ 3742 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 3743 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 3744 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ 3745 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ 3746 3747 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ 3748 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 3749 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 3750 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ 3751 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ 3752 3753 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ 3754 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 3755 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 3756 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ 3757 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ 3758 3759 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ 3760 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 3761 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 3762 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ 3763 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ 3764 3765 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ 3766 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 3767 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 3768 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ 3769 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ 3770 3771 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ 3772 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 3773 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 3774 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ 3775 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ 3776 3777 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ 3778 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 3779 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 3780 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ 3781 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ 3782 3783 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ 3784 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 3785 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 3786 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ 3787 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ 3788 3789 /* Register: GPIO_DETECTMODE */ 3790 /* Description: Select between default DETECT signal behaviour and LDETECT mode */ 3791 3792 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ 3793 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 3794 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 3795 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ 3796 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ 3797 3798 /* Register: GPIO_PIN_CNF */ 3799 /* Description: Description collection[n]: Configuration of GPIO pins */ 3800 3801 /* Bits 17..16 : Pin sensing mechanism */ 3802 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 3803 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 3804 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ 3805 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ 3806 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ 3807 3808 /* Bits 10..8 : Drive configuration */ 3809 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 3810 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 3811 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ 3812 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ 3813 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ 3814 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ 3815 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ 3816 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ 3817 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ 3818 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ 3819 3820 /* Bits 3..2 : Pull configuration */ 3821 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 3822 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 3823 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ 3824 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ 3825 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ 3826 3827 /* Bit 1 : Connect or disconnect input buffer */ 3828 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 3829 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 3830 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ 3831 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ 3832 3833 /* Bit 0 : Pin direction. Same physical register as DIR register */ 3834 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 3835 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 3836 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ 3837 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ 3838 3839 3840 /* Peripheral: PDM */ 3841 /* Description: Pulse Density Modulation (Digital Microphone) Interface */ 3842 3843 /* Register: PDM_TASKS_START */ 3844 /* Description: Starts continuous PDM transfer */ 3845 3846 /* Bit 0 : */ 3847 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 3848 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 3849 3850 /* Register: PDM_TASKS_STOP */ 3851 /* Description: Stops PDM transfer */ 3852 3853 /* Bit 0 : */ 3854 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 3855 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 3856 3857 /* Register: PDM_EVENTS_STARTED */ 3858 /* Description: PDM transfer has started */ 3859 3860 /* Bit 0 : */ 3861 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 3862 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 3863 3864 /* Register: PDM_EVENTS_STOPPED */ 3865 /* Description: PDM transfer has finished */ 3866 3867 /* Bit 0 : */ 3868 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 3869 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 3870 3871 /* Register: PDM_EVENTS_END */ 3872 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ 3873 3874 /* Bit 0 : */ 3875 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 3876 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 3877 3878 /* Register: PDM_INTEN */ 3879 /* Description: Enable or disable interrupt */ 3880 3881 /* Bit 2 : Enable or disable interrupt for END event */ 3882 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ 3883 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ 3884 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ 3885 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ 3886 3887 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 3888 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 3889 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 3890 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 3891 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 3892 3893 /* Bit 0 : Enable or disable interrupt for STARTED event */ 3894 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 3895 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 3896 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 3897 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 3898 3899 /* Register: PDM_INTENSET */ 3900 /* Description: Enable interrupt */ 3901 3902 /* Bit 2 : Write '1' to enable interrupt for END event */ 3903 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ 3904 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 3905 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 3906 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 3907 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ 3908 3909 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */ 3910 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 3911 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 3912 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 3913 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 3914 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 3915 3916 /* Bit 0 : Write '1' to enable interrupt for STARTED event */ 3917 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 3918 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 3919 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 3920 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 3921 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 3922 3923 /* Register: PDM_INTENCLR */ 3924 /* Description: Disable interrupt */ 3925 3926 /* Bit 2 : Write '1' to disable interrupt for END event */ 3927 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ 3928 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 3929 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 3930 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 3931 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ 3932 3933 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */ 3934 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 3935 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 3936 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 3937 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 3938 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 3939 3940 /* Bit 0 : Write '1' to disable interrupt for STARTED event */ 3941 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 3942 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 3943 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 3944 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 3945 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 3946 3947 /* Register: PDM_ENABLE */ 3948 /* Description: PDM module enable register */ 3949 3950 /* Bit 0 : Enable or disable PDM module */ 3951 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 3952 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 3953 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 3954 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 3955 3956 /* Register: PDM_PDMCLKCTRL */ 3957 /* Description: PDM clock generator control */ 3958 3959 /* Bits 31..0 : PDM_CLK frequency */ 3960 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ 3961 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ 3962 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ 3963 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ 3964 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ 3965 3966 /* Register: PDM_MODE */ 3967 /* Description: Defines the routing of the connected PDM microphones' signals */ 3968 3969 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ 3970 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ 3971 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ 3972 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ 3973 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ 3974 3975 /* Bit 0 : Mono or stereo operation */ 3976 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ 3977 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ 3978 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ 3979 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ 3980 3981 /* Register: PDM_GAINL */ 3982 /* Description: Left output gain adjustment */ 3983 3984 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ 3985 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ 3986 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ 3987 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ 3988 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ 3989 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ 3990 3991 /* Register: PDM_GAINR */ 3992 /* Description: Right output gain adjustment */ 3993 3994 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ 3995 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ 3996 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ 3997 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ 3998 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ 3999 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ 4000 4001 /* Register: PDM_PSEL_CLK */ 4002 /* Description: Pin number configuration for PDM CLK signal */ 4003 4004 /* Bit 31 : Connection */ 4005 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4006 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4007 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ 4008 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4009 4010 /* Bits 4..0 : Pin number */ 4011 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ 4012 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ 4013 4014 /* Register: PDM_PSEL_DIN */ 4015 /* Description: Pin number configuration for PDM DIN signal */ 4016 4017 /* Bit 31 : Connection */ 4018 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4019 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4020 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ 4021 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4022 4023 /* Bits 4..0 : Pin number */ 4024 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 4025 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ 4026 4027 /* Register: PDM_SAMPLE_PTR */ 4028 /* Description: RAM address pointer to write samples to with EasyDMA */ 4029 4030 /* Bits 31..0 : Address to write PDM samples to over DMA */ 4031 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ 4032 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ 4033 4034 /* Register: PDM_SAMPLE_MAXCNT */ 4035 /* Description: Number of samples to allocate memory for in EasyDMA mode */ 4036 4037 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */ 4038 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ 4039 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ 4040 4041 4042 /* Peripheral: POWER */ 4043 /* Description: Power control */ 4044 4045 /* Register: POWER_TASKS_CONSTLAT */ 4046 /* Description: Enable constant latency mode */ 4047 4048 /* Bit 0 : */ 4049 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ 4050 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ 4051 4052 /* Register: POWER_TASKS_LOWPWR */ 4053 /* Description: Enable low power mode (variable latency) */ 4054 4055 /* Bit 0 : */ 4056 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ 4057 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ 4058 4059 /* Register: POWER_EVENTS_POFWARN */ 4060 /* Description: Power failure warning */ 4061 4062 /* Bit 0 : */ 4063 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ 4064 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ 4065 4066 /* Register: POWER_EVENTS_SLEEPENTER */ 4067 /* Description: CPU entered WFI/WFE sleep */ 4068 4069 /* Bit 0 : */ 4070 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ 4071 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ 4072 4073 /* Register: POWER_EVENTS_SLEEPEXIT */ 4074 /* Description: CPU exited WFI/WFE sleep */ 4075 4076 /* Bit 0 : */ 4077 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ 4078 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ 4079 4080 /* Register: POWER_INTENSET */ 4081 /* Description: Enable interrupt */ 4082 4083 /* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ 4084 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 4085 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 4086 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 4087 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 4088 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ 4089 4090 /* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ 4091 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 4092 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 4093 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 4094 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 4095 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ 4096 4097 /* Bit 2 : Write '1' to enable interrupt for POFWARN event */ 4098 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 4099 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 4100 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 4101 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 4102 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ 4103 4104 /* Register: POWER_INTENCLR */ 4105 /* Description: Disable interrupt */ 4106 4107 /* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ 4108 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 4109 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 4110 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 4111 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 4112 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ 4113 4114 /* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ 4115 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 4116 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 4117 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 4118 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 4119 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ 4120 4121 /* Bit 2 : Write '1' to disable interrupt for POFWARN event */ 4122 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 4123 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 4124 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 4125 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 4126 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ 4127 4128 /* Register: POWER_RESETREAS */ 4129 /* Description: Reset reason */ 4130 4131 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ 4132 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ 4133 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 4134 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ 4135 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ 4136 4137 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ 4138 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ 4139 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 4140 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ 4141 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ 4142 4143 /* Bit 3 : Reset from CPU lock-up detected */ 4144 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ 4145 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 4146 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ 4147 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ 4148 4149 /* Bit 2 : Reset from soft reset detected */ 4150 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ 4151 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 4152 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ 4153 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ 4154 4155 /* Bit 1 : Reset from watchdog detected */ 4156 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 4157 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 4158 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ 4159 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ 4160 4161 /* Bit 0 : Reset from pin-reset detected */ 4162 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 4163 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 4164 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ 4165 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ 4166 4167 /* Register: POWER_SYSTEMOFF */ 4168 /* Description: System OFF register */ 4169 4170 /* Bit 0 : Enable System OFF mode */ 4171 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 4172 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 4173 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ 4174 4175 /* Register: POWER_POFCON */ 4176 /* Description: Power failure comparator configuration */ 4177 4178 /* Bits 4..1 : Power failure comparator threshold setting */ 4179 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ 4180 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 4181 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ 4182 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ 4183 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ 4184 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ 4185 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ 4186 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ 4187 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ 4188 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ 4189 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ 4190 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ 4191 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ 4192 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ 4193 4194 /* Bit 0 : Enable or disable power failure comparator */ 4195 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ 4196 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ 4197 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ 4198 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ 4199 4200 /* Register: POWER_GPREGRET */ 4201 /* Description: General purpose retention register */ 4202 4203 /* Bits 7..0 : General purpose retention register */ 4204 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 4205 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 4206 4207 /* Register: POWER_GPREGRET2 */ 4208 /* Description: General purpose retention register */ 4209 4210 /* Bits 7..0 : General purpose retention register */ 4211 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 4212 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 4213 4214 /* Register: POWER_DCDCEN */ 4215 /* Description: DC/DC enable register */ 4216 4217 /* Bit 0 : Enable or disable DC/DC converter */ 4218 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 4219 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 4220 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ 4221 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ 4222 4223 /* Register: POWER_RAM_POWER */ 4224 /* Description: Description cluster[n]: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ 4225 4226 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ 4227 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 4228 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 4229 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ 4230 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ 4231 4232 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ 4233 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 4234 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 4235 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ 4236 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ 4237 4238 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ 4239 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 4240 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 4241 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ 4242 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ 4243 4244 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ 4245 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 4246 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 4247 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ 4248 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ 4249 4250 /* Register: POWER_RAM_POWERSET */ 4251 /* Description: Description cluster[n]: RAMn power control set register */ 4252 4253 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ 4254 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 4255 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 4256 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ 4257 4258 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ 4259 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 4260 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 4261 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ 4262 4263 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ 4264 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 4265 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 4266 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ 4267 4268 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ 4269 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 4270 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 4271 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ 4272 4273 /* Register: POWER_RAM_POWERCLR */ 4274 /* Description: Description cluster[n]: RAMn power control clear register */ 4275 4276 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ 4277 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 4278 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 4279 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ 4280 4281 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ 4282 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 4283 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 4284 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ 4285 4286 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ 4287 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 4288 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 4289 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ 4290 4291 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ 4292 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 4293 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 4294 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ 4295 4296 4297 /* Peripheral: PPI */ 4298 /* Description: Programmable Peripheral Interconnect */ 4299 4300 /* Register: PPI_TASKS_CHG_EN */ 4301 /* Description: Description cluster[n]: Enable channel group n */ 4302 4303 /* Bit 0 : */ 4304 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ 4305 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 4306 4307 /* Register: PPI_TASKS_CHG_DIS */ 4308 /* Description: Description cluster[n]: Disable channel group n */ 4309 4310 /* Bit 0 : */ 4311 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ 4312 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ 4313 4314 /* Register: PPI_CHEN */ 4315 /* Description: Channel enable register */ 4316 4317 /* Bit 31 : Enable or disable channel 31 */ 4318 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4319 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 4320 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ 4321 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ 4322 4323 /* Bit 30 : Enable or disable channel 30 */ 4324 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4325 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ 4326 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ 4327 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ 4328 4329 /* Bit 29 : Enable or disable channel 29 */ 4330 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4331 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ 4332 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ 4333 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ 4334 4335 /* Bit 28 : Enable or disable channel 28 */ 4336 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4337 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ 4338 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ 4339 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ 4340 4341 /* Bit 27 : Enable or disable channel 27 */ 4342 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4343 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ 4344 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ 4345 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ 4346 4347 /* Bit 26 : Enable or disable channel 26 */ 4348 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4349 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ 4350 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ 4351 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ 4352 4353 /* Bit 25 : Enable or disable channel 25 */ 4354 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4355 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ 4356 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ 4357 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ 4358 4359 /* Bit 24 : Enable or disable channel 24 */ 4360 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4361 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ 4362 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ 4363 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ 4364 4365 /* Bit 23 : Enable or disable channel 23 */ 4366 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4367 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ 4368 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ 4369 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ 4370 4371 /* Bit 22 : Enable or disable channel 22 */ 4372 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4373 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ 4374 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ 4375 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ 4376 4377 /* Bit 21 : Enable or disable channel 21 */ 4378 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4379 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ 4380 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ 4381 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ 4382 4383 /* Bit 20 : Enable or disable channel 20 */ 4384 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4385 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ 4386 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ 4387 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ 4388 4389 /* Bit 19 : Enable or disable channel 19 */ 4390 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ 4391 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ 4392 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ 4393 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ 4394 4395 /* Bit 18 : Enable or disable channel 18 */ 4396 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ 4397 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ 4398 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ 4399 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ 4400 4401 /* Bit 17 : Enable or disable channel 17 */ 4402 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ 4403 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ 4404 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ 4405 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ 4406 4407 /* Bit 16 : Enable or disable channel 16 */ 4408 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ 4409 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ 4410 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ 4411 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ 4412 4413 /* Bit 15 : Enable or disable channel 15 */ 4414 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 4415 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 4416 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ 4417 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ 4418 4419 /* Bit 14 : Enable or disable channel 14 */ 4420 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 4421 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 4422 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ 4423 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ 4424 4425 /* Bit 13 : Enable or disable channel 13 */ 4426 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 4427 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 4428 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ 4429 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ 4430 4431 /* Bit 12 : Enable or disable channel 12 */ 4432 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 4433 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 4434 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ 4435 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ 4436 4437 /* Bit 11 : Enable or disable channel 11 */ 4438 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 4439 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 4440 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ 4441 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ 4442 4443 /* Bit 10 : Enable or disable channel 10 */ 4444 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4445 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 4446 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ 4447 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ 4448 4449 /* Bit 9 : Enable or disable channel 9 */ 4450 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4451 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 4452 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ 4453 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ 4454 4455 /* Bit 8 : Enable or disable channel 8 */ 4456 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4457 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 4458 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ 4459 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ 4460 4461 /* Bit 7 : Enable or disable channel 7 */ 4462 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4463 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 4464 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ 4465 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ 4466 4467 /* Bit 6 : Enable or disable channel 6 */ 4468 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4469 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 4470 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ 4471 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ 4472 4473 /* Bit 5 : Enable or disable channel 5 */ 4474 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4475 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 4476 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ 4477 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ 4478 4479 /* Bit 4 : Enable or disable channel 4 */ 4480 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4481 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 4482 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ 4483 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ 4484 4485 /* Bit 3 : Enable or disable channel 3 */ 4486 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4487 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 4488 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ 4489 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ 4490 4491 /* Bit 2 : Enable or disable channel 2 */ 4492 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4493 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 4494 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ 4495 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ 4496 4497 /* Bit 1 : Enable or disable channel 1 */ 4498 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4499 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 4500 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ 4501 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ 4502 4503 /* Bit 0 : Enable or disable channel 0 */ 4504 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4505 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 4506 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ 4507 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ 4508 4509 /* Register: PPI_CHENSET */ 4510 /* Description: Channel enable set register */ 4511 4512 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ 4513 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4514 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 4515 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ 4516 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ 4517 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ 4518 4519 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ 4520 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4521 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ 4522 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ 4523 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ 4524 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ 4525 4526 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ 4527 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4528 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ 4529 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ 4530 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ 4531 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ 4532 4533 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ 4534 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4535 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ 4536 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ 4537 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ 4538 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ 4539 4540 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ 4541 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4542 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ 4543 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ 4544 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ 4545 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ 4546 4547 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ 4548 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4549 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ 4550 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ 4551 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ 4552 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ 4553 4554 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ 4555 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4556 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ 4557 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ 4558 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ 4559 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ 4560 4561 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ 4562 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4563 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ 4564 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ 4565 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ 4566 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ 4567 4568 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ 4569 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4570 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ 4571 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ 4572 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ 4573 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ 4574 4575 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ 4576 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4577 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ 4578 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ 4579 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ 4580 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ 4581 4582 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ 4583 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4584 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ 4585 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ 4586 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ 4587 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ 4588 4589 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ 4590 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4591 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ 4592 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ 4593 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ 4594 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ 4595 4596 /* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ 4597 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ 4598 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ 4599 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ 4600 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ 4601 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ 4602 4603 /* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ 4604 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ 4605 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ 4606 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ 4607 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ 4608 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ 4609 4610 /* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ 4611 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ 4612 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ 4613 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ 4614 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ 4615 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ 4616 4617 /* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ 4618 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ 4619 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ 4620 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ 4621 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ 4622 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ 4623 4624 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ 4625 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 4626 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 4627 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ 4628 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ 4629 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ 4630 4631 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ 4632 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 4633 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 4634 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ 4635 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ 4636 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ 4637 4638 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ 4639 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 4640 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 4641 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ 4642 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ 4643 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ 4644 4645 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ 4646 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 4647 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 4648 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ 4649 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ 4650 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ 4651 4652 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ 4653 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 4654 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 4655 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ 4656 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ 4657 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ 4658 4659 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ 4660 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4661 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 4662 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ 4663 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ 4664 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ 4665 4666 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ 4667 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4668 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 4669 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ 4670 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ 4671 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ 4672 4673 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ 4674 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4675 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 4676 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ 4677 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ 4678 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ 4679 4680 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ 4681 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4682 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 4683 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ 4684 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ 4685 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ 4686 4687 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ 4688 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4689 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 4690 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ 4691 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ 4692 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ 4693 4694 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ 4695 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4696 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 4697 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ 4698 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ 4699 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ 4700 4701 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ 4702 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4703 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 4704 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ 4705 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ 4706 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ 4707 4708 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ 4709 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4710 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 4711 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ 4712 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ 4713 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ 4714 4715 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ 4716 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4717 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 4718 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ 4719 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ 4720 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ 4721 4722 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ 4723 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4724 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 4725 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ 4726 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ 4727 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ 4728 4729 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ 4730 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4731 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 4732 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ 4733 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ 4734 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ 4735 4736 /* Register: PPI_CHENCLR */ 4737 /* Description: Channel enable clear register */ 4738 4739 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ 4740 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4741 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 4742 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ 4743 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ 4744 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ 4745 4746 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ 4747 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4748 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ 4749 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ 4750 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ 4751 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ 4752 4753 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ 4754 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4755 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ 4756 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ 4757 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ 4758 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ 4759 4760 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ 4761 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4762 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ 4763 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ 4764 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ 4765 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ 4766 4767 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ 4768 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4769 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ 4770 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ 4771 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ 4772 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ 4773 4774 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ 4775 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4776 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ 4777 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ 4778 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ 4779 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ 4780 4781 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ 4782 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4783 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ 4784 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ 4785 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ 4786 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ 4787 4788 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ 4789 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4790 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ 4791 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ 4792 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ 4793 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ 4794 4795 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ 4796 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4797 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ 4798 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ 4799 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ 4800 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ 4801 4802 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ 4803 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4804 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ 4805 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ 4806 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ 4807 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ 4808 4809 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ 4810 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4811 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ 4812 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ 4813 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ 4814 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ 4815 4816 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ 4817 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4818 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ 4819 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ 4820 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ 4821 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ 4822 4823 /* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ 4824 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ 4825 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ 4826 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ 4827 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ 4828 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ 4829 4830 /* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ 4831 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ 4832 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ 4833 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ 4834 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ 4835 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ 4836 4837 /* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ 4838 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ 4839 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ 4840 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ 4841 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ 4842 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ 4843 4844 /* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ 4845 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ 4846 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ 4847 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ 4848 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ 4849 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ 4850 4851 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ 4852 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 4853 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 4854 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ 4855 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ 4856 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ 4857 4858 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ 4859 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 4860 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 4861 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ 4862 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ 4863 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ 4864 4865 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ 4866 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 4867 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 4868 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ 4869 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ 4870 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ 4871 4872 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ 4873 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 4874 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 4875 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ 4876 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ 4877 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ 4878 4879 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ 4880 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 4881 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 4882 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ 4883 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ 4884 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ 4885 4886 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ 4887 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4888 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 4889 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ 4890 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ 4891 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ 4892 4893 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ 4894 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4895 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 4896 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ 4897 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ 4898 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ 4899 4900 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ 4901 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4902 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 4903 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ 4904 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ 4905 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ 4906 4907 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ 4908 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4909 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 4910 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ 4911 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ 4912 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ 4913 4914 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ 4915 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4916 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 4917 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ 4918 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ 4919 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ 4920 4921 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ 4922 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4923 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 4924 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ 4925 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ 4926 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ 4927 4928 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ 4929 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4930 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 4931 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ 4932 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ 4933 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ 4934 4935 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ 4936 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4937 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 4938 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ 4939 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ 4940 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ 4941 4942 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ 4943 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4944 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 4945 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ 4946 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ 4947 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ 4948 4949 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ 4950 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4951 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 4952 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ 4953 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ 4954 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ 4955 4956 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ 4957 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4958 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 4959 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ 4960 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ 4961 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ 4962 4963 /* Register: PPI_CH_EEP */ 4964 /* Description: Description cluster[n]: Channel n event end-point */ 4965 4966 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ 4967 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ 4968 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ 4969 4970 /* Register: PPI_CH_TEP */ 4971 /* Description: Description cluster[n]: Channel n task end-point */ 4972 4973 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ 4974 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ 4975 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ 4976 4977 /* Register: PPI_CHG */ 4978 /* Description: Description collection[n]: Channel group n */ 4979 4980 /* Bit 31 : Include or exclude channel 31 */ 4981 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4982 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 4983 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ 4984 #define PPI_CHG_CH31_Included (1UL) /*!< Include */ 4985 4986 /* Bit 30 : Include or exclude channel 30 */ 4987 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4988 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ 4989 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ 4990 #define PPI_CHG_CH30_Included (1UL) /*!< Include */ 4991 4992 /* Bit 29 : Include or exclude channel 29 */ 4993 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4994 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ 4995 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ 4996 #define PPI_CHG_CH29_Included (1UL) /*!< Include */ 4997 4998 /* Bit 28 : Include or exclude channel 28 */ 4999 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ 5000 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ 5001 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ 5002 #define PPI_CHG_CH28_Included (1UL) /*!< Include */ 5003 5004 /* Bit 27 : Include or exclude channel 27 */ 5005 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ 5006 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ 5007 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ 5008 #define PPI_CHG_CH27_Included (1UL) /*!< Include */ 5009 5010 /* Bit 26 : Include or exclude channel 26 */ 5011 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ 5012 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ 5013 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ 5014 #define PPI_CHG_CH26_Included (1UL) /*!< Include */ 5015 5016 /* Bit 25 : Include or exclude channel 25 */ 5017 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ 5018 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ 5019 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ 5020 #define PPI_CHG_CH25_Included (1UL) /*!< Include */ 5021 5022 /* Bit 24 : Include or exclude channel 24 */ 5023 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ 5024 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ 5025 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ 5026 #define PPI_CHG_CH24_Included (1UL) /*!< Include */ 5027 5028 /* Bit 23 : Include or exclude channel 23 */ 5029 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ 5030 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ 5031 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ 5032 #define PPI_CHG_CH23_Included (1UL) /*!< Include */ 5033 5034 /* Bit 22 : Include or exclude channel 22 */ 5035 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ 5036 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ 5037 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ 5038 #define PPI_CHG_CH22_Included (1UL) /*!< Include */ 5039 5040 /* Bit 21 : Include or exclude channel 21 */ 5041 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ 5042 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ 5043 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ 5044 #define PPI_CHG_CH21_Included (1UL) /*!< Include */ 5045 5046 /* Bit 20 : Include or exclude channel 20 */ 5047 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ 5048 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ 5049 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ 5050 #define PPI_CHG_CH20_Included (1UL) /*!< Include */ 5051 5052 /* Bit 19 : Include or exclude channel 19 */ 5053 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ 5054 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ 5055 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ 5056 #define PPI_CHG_CH19_Included (1UL) /*!< Include */ 5057 5058 /* Bit 18 : Include or exclude channel 18 */ 5059 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ 5060 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ 5061 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ 5062 #define PPI_CHG_CH18_Included (1UL) /*!< Include */ 5063 5064 /* Bit 17 : Include or exclude channel 17 */ 5065 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ 5066 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ 5067 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ 5068 #define PPI_CHG_CH17_Included (1UL) /*!< Include */ 5069 5070 /* Bit 16 : Include or exclude channel 16 */ 5071 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ 5072 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ 5073 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ 5074 #define PPI_CHG_CH16_Included (1UL) /*!< Include */ 5075 5076 /* Bit 15 : Include or exclude channel 15 */ 5077 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 5078 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 5079 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ 5080 #define PPI_CHG_CH15_Included (1UL) /*!< Include */ 5081 5082 /* Bit 14 : Include or exclude channel 14 */ 5083 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 5084 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 5085 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ 5086 #define PPI_CHG_CH14_Included (1UL) /*!< Include */ 5087 5088 /* Bit 13 : Include or exclude channel 13 */ 5089 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 5090 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 5091 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ 5092 #define PPI_CHG_CH13_Included (1UL) /*!< Include */ 5093 5094 /* Bit 12 : Include or exclude channel 12 */ 5095 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 5096 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 5097 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ 5098 #define PPI_CHG_CH12_Included (1UL) /*!< Include */ 5099 5100 /* Bit 11 : Include or exclude channel 11 */ 5101 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 5102 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 5103 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ 5104 #define PPI_CHG_CH11_Included (1UL) /*!< Include */ 5105 5106 /* Bit 10 : Include or exclude channel 10 */ 5107 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 5108 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 5109 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ 5110 #define PPI_CHG_CH10_Included (1UL) /*!< Include */ 5111 5112 /* Bit 9 : Include or exclude channel 9 */ 5113 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 5114 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 5115 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ 5116 #define PPI_CHG_CH9_Included (1UL) /*!< Include */ 5117 5118 /* Bit 8 : Include or exclude channel 8 */ 5119 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 5120 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 5121 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ 5122 #define PPI_CHG_CH8_Included (1UL) /*!< Include */ 5123 5124 /* Bit 7 : Include or exclude channel 7 */ 5125 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 5126 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 5127 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ 5128 #define PPI_CHG_CH7_Included (1UL) /*!< Include */ 5129 5130 /* Bit 6 : Include or exclude channel 6 */ 5131 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 5132 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 5133 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ 5134 #define PPI_CHG_CH6_Included (1UL) /*!< Include */ 5135 5136 /* Bit 5 : Include or exclude channel 5 */ 5137 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 5138 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 5139 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ 5140 #define PPI_CHG_CH5_Included (1UL) /*!< Include */ 5141 5142 /* Bit 4 : Include or exclude channel 4 */ 5143 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 5144 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 5145 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ 5146 #define PPI_CHG_CH4_Included (1UL) /*!< Include */ 5147 5148 /* Bit 3 : Include or exclude channel 3 */ 5149 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 5150 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 5151 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ 5152 #define PPI_CHG_CH3_Included (1UL) /*!< Include */ 5153 5154 /* Bit 2 : Include or exclude channel 2 */ 5155 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 5156 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 5157 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ 5158 #define PPI_CHG_CH2_Included (1UL) /*!< Include */ 5159 5160 /* Bit 1 : Include or exclude channel 1 */ 5161 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 5162 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 5163 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ 5164 #define PPI_CHG_CH1_Included (1UL) /*!< Include */ 5165 5166 /* Bit 0 : Include or exclude channel 0 */ 5167 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 5168 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 5169 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ 5170 #define PPI_CHG_CH0_Included (1UL) /*!< Include */ 5171 5172 /* Register: PPI_FORK_TEP */ 5173 /* Description: Description cluster[n]: Channel n task end-point */ 5174 5175 /* Bits 31..0 : Pointer to task register */ 5176 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ 5177 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ 5178 5179 5180 /* Peripheral: PWM */ 5181 /* Description: Pulse width modulation unit */ 5182 5183 /* Register: PWM_TASKS_STOP */ 5184 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ 5185 5186 /* Bit 0 : */ 5187 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5188 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5189 5190 /* Register: PWM_TASKS_SEQSTART */ 5191 /* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ 5192 5193 /* Bit 0 : */ 5194 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ 5195 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ 5196 5197 /* Register: PWM_TASKS_NEXTSTEP */ 5198 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ 5199 5200 /* Bit 0 : */ 5201 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ 5202 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ 5203 5204 /* Register: PWM_EVENTS_STOPPED */ 5205 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ 5206 5207 /* Bit 0 : */ 5208 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 5209 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 5210 5211 /* Register: PWM_EVENTS_SEQSTARTED */ 5212 /* Description: Description collection[n]: First PWM period started on sequence n */ 5213 5214 /* Bit 0 : */ 5215 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ 5216 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ 5217 5218 /* Register: PWM_EVENTS_SEQEND */ 5219 /* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ 5220 5221 /* Bit 0 : */ 5222 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ 5223 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ 5224 5225 /* Register: PWM_EVENTS_PWMPERIODEND */ 5226 /* Description: Emitted at the end of each PWM period */ 5227 5228 /* Bit 0 : */ 5229 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ 5230 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ 5231 5232 /* Register: PWM_EVENTS_LOOPSDONE */ 5233 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ 5234 5235 /* Bit 0 : */ 5236 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ 5237 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ 5238 5239 /* Register: PWM_SHORTS */ 5240 /* Description: Shortcut register */ 5241 5242 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ 5243 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ 5244 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ 5245 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ 5246 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ 5247 5248 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ 5249 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ 5250 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ 5251 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ 5252 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ 5253 5254 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ 5255 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ 5256 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ 5257 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ 5258 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ 5259 5260 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ 5261 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ 5262 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ 5263 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ 5264 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ 5265 5266 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ 5267 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ 5268 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ 5269 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ 5270 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ 5271 5272 /* Register: PWM_INTEN */ 5273 /* Description: Enable or disable interrupt */ 5274 5275 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ 5276 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 5277 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 5278 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ 5279 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ 5280 5281 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ 5282 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 5283 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 5284 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ 5285 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ 5286 5287 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ 5288 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 5289 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 5290 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ 5291 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ 5292 5293 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ 5294 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 5295 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 5296 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ 5297 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ 5298 5299 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ 5300 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 5301 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 5302 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ 5303 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ 5304 5305 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ 5306 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 5307 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 5308 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ 5309 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ 5310 5311 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 5312 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5313 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5314 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 5315 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 5316 5317 /* Register: PWM_INTENSET */ 5318 /* Description: Enable interrupt */ 5319 5320 /* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ 5321 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 5322 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 5323 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ 5324 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ 5325 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ 5326 5327 /* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ 5328 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 5329 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 5330 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ 5331 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ 5332 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ 5333 5334 /* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ 5335 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 5336 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 5337 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ 5338 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ 5339 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ 5340 5341 /* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ 5342 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 5343 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 5344 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ 5345 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ 5346 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ 5347 5348 /* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ 5349 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 5350 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 5351 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ 5352 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ 5353 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ 5354 5355 /* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ 5356 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 5357 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 5358 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ 5359 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ 5360 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ 5361 5362 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */ 5363 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5364 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5365 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 5366 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 5367 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 5368 5369 /* Register: PWM_INTENCLR */ 5370 /* Description: Disable interrupt */ 5371 5372 /* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ 5373 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 5374 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 5375 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ 5376 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ 5377 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ 5378 5379 /* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ 5380 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 5381 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 5382 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ 5383 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ 5384 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ 5385 5386 /* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ 5387 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 5388 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 5389 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ 5390 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ 5391 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ 5392 5393 /* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ 5394 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 5395 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 5396 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ 5397 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ 5398 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ 5399 5400 /* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ 5401 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 5402 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 5403 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ 5404 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ 5405 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ 5406 5407 /* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ 5408 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 5409 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 5410 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ 5411 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ 5412 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ 5413 5414 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */ 5415 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5416 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5417 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 5418 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 5419 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 5420 5421 /* Register: PWM_ENABLE */ 5422 /* Description: PWM module enable register */ 5423 5424 /* Bit 0 : Enable or disable PWM module */ 5425 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5426 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5427 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ 5428 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 5429 5430 /* Register: PWM_MODE */ 5431 /* Description: Selects operating mode of the wave counter */ 5432 5433 /* Bit 0 : Selects up mode or up-and-down mode for the counter */ 5434 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ 5435 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ 5436 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ 5437 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ 5438 5439 /* Register: PWM_COUNTERTOP */ 5440 /* Description: Value up to which the pulse generator counter counts */ 5441 5442 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ 5443 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ 5444 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ 5445 5446 /* Register: PWM_PRESCALER */ 5447 /* Description: Configuration for PWM_CLK */ 5448 5449 /* Bits 2..0 : Prescaler of PWM_CLK */ 5450 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5451 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5452 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ 5453 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ 5454 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ 5455 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ 5456 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ 5457 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ 5458 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ 5459 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ 5460 5461 /* Register: PWM_DECODER */ 5462 /* Description: Configuration of the decoder */ 5463 5464 /* Bit 8 : Selects source for advancing the active sequence */ 5465 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ 5466 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ 5467 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ 5468 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ 5469 5470 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ 5471 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ 5472 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ 5473 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ 5474 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ 5475 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ 5476 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ 5477 5478 /* Register: PWM_LOOP */ 5479 /* Description: Number of playbacks of a loop */ 5480 5481 /* Bits 15..0 : Number of playbacks of pattern cycles */ 5482 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ 5483 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ 5484 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ 5485 5486 /* Register: PWM_SEQ_PTR */ 5487 /* Description: Description cluster[n]: Beginning address in RAM of this sequence */ 5488 5489 /* Bits 31..0 : Beginning address in RAM of this sequence */ 5490 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 5491 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 5492 5493 /* Register: PWM_SEQ_CNT */ 5494 /* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ 5495 5496 /* Bits 14..0 : Number of values (duty cycles) in this sequence */ 5497 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ 5498 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ 5499 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ 5500 5501 /* Register: PWM_SEQ_REFRESH */ 5502 /* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ 5503 5504 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ 5505 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ 5506 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ 5507 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ 5508 5509 /* Register: PWM_SEQ_ENDDELAY */ 5510 /* Description: Description cluster[n]: Time added after the sequence */ 5511 5512 /* Bits 23..0 : Time added after the sequence in PWM periods */ 5513 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ 5514 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ 5515 5516 /* Register: PWM_PSEL_OUT */ 5517 /* Description: Description collection[n]: Output pin select for PWM channel n */ 5518 5519 /* Bit 31 : Connection */ 5520 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5521 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5522 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ 5523 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5524 5525 /* Bits 4..0 : Pin number */ 5526 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 5527 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ 5528 5529 5530 /* Peripheral: QDEC */ 5531 /* Description: Quadrature Decoder */ 5532 5533 /* Register: QDEC_TASKS_START */ 5534 /* Description: Task starting the quadrature decoder */ 5535 5536 /* Bit 0 : */ 5537 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5538 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5539 5540 /* Register: QDEC_TASKS_STOP */ 5541 /* Description: Task stopping the quadrature decoder */ 5542 5543 /* Bit 0 : */ 5544 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5545 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5546 5547 /* Register: QDEC_TASKS_READCLRACC */ 5548 /* Description: Read and clear ACC and ACCDBL */ 5549 5550 /* Bit 0 : */ 5551 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ 5552 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ 5553 5554 /* Register: QDEC_TASKS_RDCLRACC */ 5555 /* Description: Read and clear ACC */ 5556 5557 /* Bit 0 : */ 5558 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ 5559 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ 5560 5561 /* Register: QDEC_TASKS_RDCLRDBL */ 5562 /* Description: Read and clear ACCDBL */ 5563 5564 /* Bit 0 : */ 5565 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ 5566 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ 5567 5568 /* Register: QDEC_EVENTS_SAMPLERDY */ 5569 /* Description: Event being generated for every new sample value written to the SAMPLE register */ 5570 5571 /* Bit 0 : */ 5572 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ 5573 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ 5574 5575 /* Register: QDEC_EVENTS_REPORTRDY */ 5576 /* Description: Non-null report ready */ 5577 5578 /* Bit 0 : */ 5579 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ 5580 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ 5581 5582 /* Register: QDEC_EVENTS_ACCOF */ 5583 /* Description: ACC or ACCDBL register overflow */ 5584 5585 /* Bit 0 : */ 5586 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ 5587 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ 5588 5589 /* Register: QDEC_EVENTS_DBLRDY */ 5590 /* Description: Double displacement(s) detected */ 5591 5592 /* Bit 0 : */ 5593 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ 5594 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ 5595 5596 /* Register: QDEC_EVENTS_STOPPED */ 5597 /* Description: QDEC has been stopped */ 5598 5599 /* Bit 0 : */ 5600 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 5601 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 5602 5603 /* Register: QDEC_SHORTS */ 5604 /* Description: Shortcut register */ 5605 5606 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ 5607 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ 5608 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ 5609 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ 5610 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ 5611 5612 /* Bit 5 : Shortcut between DBLRDY event and STOP task */ 5613 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ 5614 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ 5615 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 5616 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 5617 5618 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ 5619 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ 5620 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ 5621 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ 5622 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ 5623 5624 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */ 5625 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ 5626 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ 5627 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 5628 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 5629 5630 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ 5631 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ 5632 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ 5633 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ 5634 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ 5635 5636 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ 5637 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ 5638 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ 5639 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 5640 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 5641 5642 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ 5643 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ 5644 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ 5645 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ 5646 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ 5647 5648 /* Register: QDEC_INTENSET */ 5649 /* Description: Enable interrupt */ 5650 5651 /* Bit 4 : Write '1' to enable interrupt for STOPPED event */ 5652 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ 5653 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5654 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 5655 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 5656 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 5657 5658 /* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ 5659 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ 5660 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ 5661 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ 5662 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ 5663 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ 5664 5665 /* Bit 2 : Write '1' to enable interrupt for ACCOF event */ 5666 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 5667 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 5668 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ 5669 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ 5670 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ 5671 5672 /* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ 5673 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 5674 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 5675 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ 5676 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ 5677 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ 5678 5679 /* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ 5680 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 5681 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 5682 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ 5683 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ 5684 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ 5685 5686 /* Register: QDEC_INTENCLR */ 5687 /* Description: Disable interrupt */ 5688 5689 /* Bit 4 : Write '1' to disable interrupt for STOPPED event */ 5690 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ 5691 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5692 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 5693 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 5694 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 5695 5696 /* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ 5697 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ 5698 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ 5699 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ 5700 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ 5701 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ 5702 5703 /* Bit 2 : Write '1' to disable interrupt for ACCOF event */ 5704 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 5705 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 5706 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ 5707 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ 5708 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ 5709 5710 /* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ 5711 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 5712 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 5713 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ 5714 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ 5715 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ 5716 5717 /* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ 5718 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 5719 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 5720 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ 5721 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ 5722 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ 5723 5724 /* Register: QDEC_ENABLE */ 5725 /* Description: Enable the quadrature decoder */ 5726 5727 /* Bit 0 : Enable or disable the quadrature decoder */ 5728 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5729 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5730 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 5731 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 5732 5733 /* Register: QDEC_LEDPOL */ 5734 /* Description: LED output pin polarity */ 5735 5736 /* Bit 0 : LED output pin polarity */ 5737 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ 5738 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ 5739 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ 5740 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ 5741 5742 /* Register: QDEC_SAMPLEPER */ 5743 /* Description: Sample period */ 5744 5745 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ 5746 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ 5747 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ 5748 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ 5749 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ 5750 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ 5751 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ 5752 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ 5753 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ 5754 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ 5755 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ 5756 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ 5757 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ 5758 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ 5759 5760 /* Register: QDEC_SAMPLE */ 5761 /* Description: Motion sample value */ 5762 5763 /* Bits 31..0 : Last motion sample */ 5764 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ 5765 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ 5766 5767 /* Register: QDEC_REPORTPER */ 5768 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ 5769 5770 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ 5771 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ 5772 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ 5773 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ 5774 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ 5775 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ 5776 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ 5777 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ 5778 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ 5779 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ 5780 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ 5781 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ 5782 5783 /* Register: QDEC_ACC */ 5784 /* Description: Register accumulating the valid transitions */ 5785 5786 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ 5787 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ 5788 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ 5789 5790 /* Register: QDEC_ACCREAD */ 5791 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ 5792 5793 /* Bits 31..0 : Snapshot of the ACC register. */ 5794 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ 5795 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ 5796 5797 /* Register: QDEC_PSEL_LED */ 5798 /* Description: Pin select for LED signal */ 5799 5800 /* Bit 31 : Connection */ 5801 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5802 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5803 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ 5804 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5805 5806 /* Bits 4..0 : Pin number */ 5807 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ 5808 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ 5809 5810 /* Register: QDEC_PSEL_A */ 5811 /* Description: Pin select for A signal */ 5812 5813 /* Bit 31 : Connection */ 5814 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5815 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5816 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ 5817 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5818 5819 /* Bits 4..0 : Pin number */ 5820 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ 5821 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ 5822 5823 /* Register: QDEC_PSEL_B */ 5824 /* Description: Pin select for B signal */ 5825 5826 /* Bit 31 : Connection */ 5827 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5828 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5829 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ 5830 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5831 5832 /* Bits 4..0 : Pin number */ 5833 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ 5834 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ 5835 5836 /* Register: QDEC_DBFEN */ 5837 /* Description: Enable input debounce filters */ 5838 5839 /* Bit 0 : Enable input debounce filters */ 5840 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ 5841 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ 5842 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ 5843 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ 5844 5845 /* Register: QDEC_LEDPRE */ 5846 /* Description: Time period the LED is switched ON prior to sampling */ 5847 5848 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */ 5849 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ 5850 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ 5851 5852 /* Register: QDEC_ACCDBL */ 5853 /* Description: Register accumulating the number of detected double transitions */ 5854 5855 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ 5856 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ 5857 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ 5858 5859 /* Register: QDEC_ACCDBLREAD */ 5860 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ 5861 5862 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ 5863 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ 5864 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ 5865 5866 5867 /* Peripheral: RADIO */ 5868 /* Description: 2.4 GHz Radio */ 5869 5870 /* Register: RADIO_TASKS_TXEN */ 5871 /* Description: Enable RADIO in TX mode */ 5872 5873 /* Bit 0 : */ 5874 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ 5875 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ 5876 5877 /* Register: RADIO_TASKS_RXEN */ 5878 /* Description: Enable RADIO in RX mode */ 5879 5880 /* Bit 0 : */ 5881 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ 5882 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ 5883 5884 /* Register: RADIO_TASKS_START */ 5885 /* Description: Start RADIO */ 5886 5887 /* Bit 0 : */ 5888 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5889 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5890 5891 /* Register: RADIO_TASKS_STOP */ 5892 /* Description: Stop RADIO */ 5893 5894 /* Bit 0 : */ 5895 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5896 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5897 5898 /* Register: RADIO_TASKS_DISABLE */ 5899 /* Description: Disable RADIO */ 5900 5901 /* Bit 0 : */ 5902 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ 5903 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ 5904 5905 /* Register: RADIO_TASKS_RSSISTART */ 5906 /* Description: Start the RSSI and take one single sample of the receive signal strength. */ 5907 5908 /* Bit 0 : */ 5909 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ 5910 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ 5911 5912 /* Register: RADIO_TASKS_RSSISTOP */ 5913 /* Description: Stop the RSSI measurement */ 5914 5915 /* Bit 0 : */ 5916 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ 5917 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ 5918 5919 /* Register: RADIO_TASKS_BCSTART */ 5920 /* Description: Start the bit counter */ 5921 5922 /* Bit 0 : */ 5923 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ 5924 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ 5925 5926 /* Register: RADIO_TASKS_BCSTOP */ 5927 /* Description: Stop the bit counter */ 5928 5929 /* Bit 0 : */ 5930 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ 5931 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ 5932 5933 /* Register: RADIO_EVENTS_READY */ 5934 /* Description: RADIO has ramped up and is ready to be started */ 5935 5936 /* Bit 0 : */ 5937 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ 5938 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ 5939 5940 /* Register: RADIO_EVENTS_ADDRESS */ 5941 /* Description: Address sent or received */ 5942 5943 /* Bit 0 : */ 5944 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ 5945 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ 5946 5947 /* Register: RADIO_EVENTS_PAYLOAD */ 5948 /* Description: Packet payload sent or received */ 5949 5950 /* Bit 0 : */ 5951 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ 5952 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ 5953 5954 /* Register: RADIO_EVENTS_END */ 5955 /* Description: Packet sent or received */ 5956 5957 /* Bit 0 : */ 5958 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 5959 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 5960 5961 /* Register: RADIO_EVENTS_DISABLED */ 5962 /* Description: RADIO has been disabled */ 5963 5964 /* Bit 0 : */ 5965 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ 5966 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ 5967 5968 /* Register: RADIO_EVENTS_DEVMATCH */ 5969 /* Description: A device address match occurred on the last received packet */ 5970 5971 /* Bit 0 : */ 5972 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ 5973 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ 5974 5975 /* Register: RADIO_EVENTS_DEVMISS */ 5976 /* Description: No device address match occurred on the last received packet */ 5977 5978 /* Bit 0 : */ 5979 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ 5980 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ 5981 5982 /* Register: RADIO_EVENTS_RSSIEND */ 5983 /* Description: Sampling of receive signal strength complete. */ 5984 5985 /* Bit 0 : */ 5986 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ 5987 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ 5988 5989 /* Register: RADIO_EVENTS_BCMATCH */ 5990 /* Description: Bit counter reached bit count value. */ 5991 5992 /* Bit 0 : */ 5993 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ 5994 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ 5995 5996 /* Register: RADIO_EVENTS_CRCOK */ 5997 /* Description: Packet received with CRC ok */ 5998 5999 /* Bit 0 : */ 6000 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ 6001 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ 6002 6003 /* Register: RADIO_EVENTS_CRCERROR */ 6004 /* Description: Packet received with CRC error */ 6005 6006 /* Bit 0 : */ 6007 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ 6008 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ 6009 6010 /* Register: RADIO_SHORTS */ 6011 /* Description: Shortcut register */ 6012 6013 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ 6014 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 6015 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 6016 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ 6017 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ 6018 6019 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ 6020 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 6021 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 6022 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 6023 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 6024 6025 /* Bit 5 : Shortcut between END event and START task */ 6026 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 6027 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 6028 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 6029 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 6030 6031 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ 6032 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 6033 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 6034 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ 6035 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ 6036 6037 /* Bit 3 : Shortcut between DISABLED event and RXEN task */ 6038 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 6039 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 6040 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ 6041 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ 6042 6043 /* Bit 2 : Shortcut between DISABLED event and TXEN task */ 6044 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 6045 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 6046 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ 6047 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ 6048 6049 /* Bit 1 : Shortcut between END event and DISABLE task */ 6050 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 6051 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 6052 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 6053 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 6054 6055 /* Bit 0 : Shortcut between READY event and START task */ 6056 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 6057 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 6058 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ 6059 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ 6060 6061 /* Register: RADIO_INTENSET */ 6062 /* Description: Enable interrupt */ 6063 6064 /* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ 6065 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 6066 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 6067 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 6068 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 6069 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ 6070 6071 /* Bit 12 : Write '1' to enable interrupt for CRCOK event */ 6072 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 6073 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 6074 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 6075 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 6076 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ 6077 6078 /* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ 6079 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 6080 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 6081 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 6082 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 6083 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ 6084 6085 /* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ 6086 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 6087 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 6088 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 6089 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 6090 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ 6091 6092 /* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ 6093 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 6094 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 6095 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 6096 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 6097 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ 6098 6099 /* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ 6100 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 6101 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 6102 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 6103 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 6104 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ 6105 6106 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */ 6107 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 6108 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 6109 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 6110 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 6111 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ 6112 6113 /* Bit 3 : Write '1' to enable interrupt for END event */ 6114 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 6115 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 6116 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 6117 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 6118 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ 6119 6120 /* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ 6121 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 6122 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 6123 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 6124 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 6125 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ 6126 6127 /* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ 6128 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 6129 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 6130 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 6131 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 6132 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ 6133 6134 /* Bit 0 : Write '1' to enable interrupt for READY event */ 6135 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 6136 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 6137 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 6138 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 6139 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ 6140 6141 /* Register: RADIO_INTENCLR */ 6142 /* Description: Disable interrupt */ 6143 6144 /* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ 6145 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 6146 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 6147 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 6148 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 6149 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ 6150 6151 /* Bit 12 : Write '1' to disable interrupt for CRCOK event */ 6152 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 6153 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 6154 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 6155 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 6156 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ 6157 6158 /* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ 6159 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 6160 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 6161 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 6162 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 6163 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ 6164 6165 /* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ 6166 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 6167 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 6168 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 6169 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 6170 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ 6171 6172 /* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ 6173 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 6174 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 6175 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 6176 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 6177 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ 6178 6179 /* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ 6180 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 6181 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 6182 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 6183 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 6184 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ 6185 6186 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */ 6187 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 6188 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 6189 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 6190 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 6191 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ 6192 6193 /* Bit 3 : Write '1' to disable interrupt for END event */ 6194 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 6195 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 6196 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 6197 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 6198 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ 6199 6200 /* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ 6201 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 6202 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 6203 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 6204 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 6205 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ 6206 6207 /* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ 6208 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 6209 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 6210 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 6211 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 6212 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ 6213 6214 /* Bit 0 : Write '1' to disable interrupt for READY event */ 6215 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 6216 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 6217 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 6218 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 6219 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ 6220 6221 /* Register: RADIO_CRCSTATUS */ 6222 /* Description: CRC status */ 6223 6224 /* Bit 0 : CRC status of packet received */ 6225 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 6226 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 6227 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ 6228 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ 6229 6230 /* Register: RADIO_RXMATCH */ 6231 /* Description: Received address */ 6232 6233 /* Bits 2..0 : Received address */ 6234 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 6235 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 6236 6237 /* Register: RADIO_RXCRC */ 6238 /* Description: CRC field of previously received packet */ 6239 6240 /* Bits 23..0 : CRC field of previously received packet */ 6241 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 6242 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 6243 6244 /* Register: RADIO_DAI */ 6245 /* Description: Device address match index */ 6246 6247 /* Bits 2..0 : Device address match index */ 6248 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 6249 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 6250 6251 /* Register: RADIO_PACKETPTR */ 6252 /* Description: Packet pointer */ 6253 6254 /* Bits 31..0 : Packet pointer */ 6255 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ 6256 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ 6257 6258 /* Register: RADIO_FREQUENCY */ 6259 /* Description: Frequency */ 6260 6261 /* Bit 8 : Channel map selection. */ 6262 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ 6263 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ 6264 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ 6265 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ 6266 6267 /* Bits 6..0 : Radio channel frequency */ 6268 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 6269 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 6270 6271 /* Register: RADIO_TXPOWER */ 6272 /* Description: Output power */ 6273 6274 /* Bits 7..0 : RADIO output power. */ 6275 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 6276 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 6277 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ 6278 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ 6279 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ 6280 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ 6281 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ 6282 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ 6283 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ 6284 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ 6285 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ 6286 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ 6287 6288 /* Register: RADIO_MODE */ 6289 /* Description: Data rate and modulation */ 6290 6291 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ 6292 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 6293 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 6294 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ 6295 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ 6296 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ 6297 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ 6298 6299 /* Register: RADIO_PCNF0 */ 6300 /* Description: Packet configuration register 0 */ 6301 6302 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ 6303 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ 6304 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ 6305 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ 6306 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ 6307 6308 /* Bit 20 : Include or exclude S1 field in RAM */ 6309 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ 6310 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ 6311 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ 6312 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ 6313 6314 /* Bits 19..16 : Length on air of S1 field in number of bits. */ 6315 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 6316 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 6317 6318 /* Bit 8 : Length on air of S0 field in number of bytes. */ 6319 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 6320 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 6321 6322 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */ 6323 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 6324 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 6325 6326 /* Register: RADIO_PCNF1 */ 6327 /* Description: Packet configuration register 1 */ 6328 6329 /* Bit 25 : Enable or disable packet whitening */ 6330 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 6331 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 6332 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ 6333 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ 6334 6335 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ 6336 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 6337 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 6338 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ 6339 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 6340 6341 /* Bits 18..16 : Base address length in number of bytes */ 6342 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 6343 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 6344 6345 /* Bits 15..8 : Static length in number of bytes */ 6346 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 6347 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 6348 6349 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ 6350 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 6351 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 6352 6353 /* Register: RADIO_BASE0 */ 6354 /* Description: Base address 0 */ 6355 6356 /* Bits 31..0 : Base address 0 */ 6357 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ 6358 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ 6359 6360 /* Register: RADIO_BASE1 */ 6361 /* Description: Base address 1 */ 6362 6363 /* Bits 31..0 : Base address 1 */ 6364 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ 6365 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ 6366 6367 /* Register: RADIO_PREFIX0 */ 6368 /* Description: Prefixes bytes for logical addresses 0-3 */ 6369 6370 /* Bits 31..24 : Address prefix 3. */ 6371 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 6372 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 6373 6374 /* Bits 23..16 : Address prefix 2. */ 6375 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 6376 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 6377 6378 /* Bits 15..8 : Address prefix 1. */ 6379 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 6380 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 6381 6382 /* Bits 7..0 : Address prefix 0. */ 6383 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 6384 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 6385 6386 /* Register: RADIO_PREFIX1 */ 6387 /* Description: Prefixes bytes for logical addresses 4-7 */ 6388 6389 /* Bits 31..24 : Address prefix 7. */ 6390 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 6391 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 6392 6393 /* Bits 23..16 : Address prefix 6. */ 6394 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 6395 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 6396 6397 /* Bits 15..8 : Address prefix 5. */ 6398 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 6399 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 6400 6401 /* Bits 7..0 : Address prefix 4. */ 6402 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 6403 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 6404 6405 /* Register: RADIO_TXADDRESS */ 6406 /* Description: Transmit address select */ 6407 6408 /* Bits 2..0 : Transmit address select */ 6409 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 6410 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 6411 6412 /* Register: RADIO_RXADDRESSES */ 6413 /* Description: Receive address select */ 6414 6415 /* Bit 7 : Enable or disable reception on logical address 7. */ 6416 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 6417 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 6418 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ 6419 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ 6420 6421 /* Bit 6 : Enable or disable reception on logical address 6. */ 6422 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 6423 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 6424 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ 6425 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ 6426 6427 /* Bit 5 : Enable or disable reception on logical address 5. */ 6428 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 6429 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 6430 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ 6431 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ 6432 6433 /* Bit 4 : Enable or disable reception on logical address 4. */ 6434 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 6435 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 6436 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ 6437 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ 6438 6439 /* Bit 3 : Enable or disable reception on logical address 3. */ 6440 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 6441 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 6442 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ 6443 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ 6444 6445 /* Bit 2 : Enable or disable reception on logical address 2. */ 6446 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 6447 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 6448 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ 6449 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ 6450 6451 /* Bit 1 : Enable or disable reception on logical address 1. */ 6452 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 6453 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 6454 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ 6455 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ 6456 6457 /* Bit 0 : Enable or disable reception on logical address 0. */ 6458 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 6459 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 6460 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ 6461 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ 6462 6463 /* Register: RADIO_CRCCNF */ 6464 /* Description: CRC configuration */ 6465 6466 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */ 6467 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 6468 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 6469 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ 6470 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ 6471 6472 /* Bits 1..0 : CRC length in number of bytes. */ 6473 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 6474 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 6475 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ 6476 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ 6477 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ 6478 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ 6479 6480 /* Register: RADIO_CRCPOLY */ 6481 /* Description: CRC polynomial */ 6482 6483 /* Bits 23..0 : CRC polynomial */ 6484 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 6485 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 6486 6487 /* Register: RADIO_CRCINIT */ 6488 /* Description: CRC initial value */ 6489 6490 /* Bits 23..0 : CRC initial value */ 6491 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 6492 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 6493 6494 /* Register: RADIO_TIFS */ 6495 /* Description: Inter Frame Spacing in us */ 6496 6497 /* Bits 7..0 : Inter Frame Spacing in us */ 6498 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 6499 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 6500 6501 /* Register: RADIO_RSSISAMPLE */ 6502 /* Description: RSSI sample */ 6503 6504 /* Bits 6..0 : RSSI sample */ 6505 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 6506 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 6507 6508 /* Register: RADIO_STATE */ 6509 /* Description: Current radio state */ 6510 6511 /* Bits 3..0 : Current radio state */ 6512 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 6513 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 6514 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ 6515 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ 6516 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ 6517 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ 6518 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ 6519 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ 6520 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ 6521 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ 6522 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ 6523 6524 /* Register: RADIO_DATAWHITEIV */ 6525 /* Description: Data whitening initial value */ 6526 6527 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ 6528 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 6529 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 6530 6531 /* Register: RADIO_BCC */ 6532 /* Description: Bit counter compare */ 6533 6534 /* Bits 31..0 : Bit counter compare */ 6535 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ 6536 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ 6537 6538 /* Register: RADIO_DAB */ 6539 /* Description: Description collection[n]: Device address base segment n */ 6540 6541 /* Bits 31..0 : Device address base segment n */ 6542 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ 6543 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ 6544 6545 /* Register: RADIO_DAP */ 6546 /* Description: Description collection[n]: Device address prefix n */ 6547 6548 /* Bits 15..0 : Device address prefix n */ 6549 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 6550 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 6551 6552 /* Register: RADIO_DACNF */ 6553 /* Description: Device address match configuration */ 6554 6555 /* Bit 15 : TxAdd for device address 7 */ 6556 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 6557 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 6558 6559 /* Bit 14 : TxAdd for device address 6 */ 6560 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 6561 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 6562 6563 /* Bit 13 : TxAdd for device address 5 */ 6564 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 6565 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 6566 6567 /* Bit 12 : TxAdd for device address 4 */ 6568 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 6569 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 6570 6571 /* Bit 11 : TxAdd for device address 3 */ 6572 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 6573 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 6574 6575 /* Bit 10 : TxAdd for device address 2 */ 6576 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 6577 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 6578 6579 /* Bit 9 : TxAdd for device address 1 */ 6580 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 6581 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 6582 6583 /* Bit 8 : TxAdd for device address 0 */ 6584 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 6585 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 6586 6587 /* Bit 7 : Enable or disable device address matching using device address 7 */ 6588 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 6589 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 6590 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ 6591 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ 6592 6593 /* Bit 6 : Enable or disable device address matching using device address 6 */ 6594 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 6595 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 6596 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ 6597 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ 6598 6599 /* Bit 5 : Enable or disable device address matching using device address 5 */ 6600 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 6601 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 6602 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ 6603 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ 6604 6605 /* Bit 4 : Enable or disable device address matching using device address 4 */ 6606 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 6607 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 6608 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ 6609 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ 6610 6611 /* Bit 3 : Enable or disable device address matching using device address 3 */ 6612 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 6613 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 6614 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ 6615 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ 6616 6617 /* Bit 2 : Enable or disable device address matching using device address 2 */ 6618 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 6619 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 6620 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ 6621 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ 6622 6623 /* Bit 1 : Enable or disable device address matching using device address 1 */ 6624 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 6625 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 6626 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ 6627 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ 6628 6629 /* Bit 0 : Enable or disable device address matching using device address 0 */ 6630 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 6631 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 6632 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ 6633 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ 6634 6635 /* Register: RADIO_MODECNF0 */ 6636 /* Description: Radio mode configuration register 0 */ 6637 6638 /* Bits 9..8 : Default TX value */ 6639 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ 6640 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ 6641 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ 6642 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ 6643 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ 6644 6645 /* Bit 0 : Radio ramp-up time */ 6646 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ 6647 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ 6648 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ 6649 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ 6650 6651 /* Register: RADIO_POWER */ 6652 /* Description: Peripheral power control */ 6653 6654 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ 6655 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6656 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6657 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ 6658 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ 6659 6660 6661 /* Peripheral: RNG */ 6662 /* Description: Random Number Generator */ 6663 6664 /* Register: RNG_TASKS_START */ 6665 /* Description: Task starting the random number generator */ 6666 6667 /* Bit 0 : */ 6668 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 6669 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 6670 6671 /* Register: RNG_TASKS_STOP */ 6672 /* Description: Task stopping the random number generator */ 6673 6674 /* Bit 0 : */ 6675 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 6676 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 6677 6678 /* Register: RNG_EVENTS_VALRDY */ 6679 /* Description: Event being generated for every new random number written to the VALUE register */ 6680 6681 /* Bit 0 : */ 6682 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ 6683 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ 6684 6685 /* Register: RNG_SHORTS */ 6686 /* Description: Shortcut register */ 6687 6688 /* Bit 0 : Shortcut between VALRDY event and STOP task */ 6689 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 6690 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 6691 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 6692 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 6693 6694 /* Register: RNG_INTENSET */ 6695 /* Description: Enable interrupt */ 6696 6697 /* Bit 0 : Write '1' to enable interrupt for VALRDY event */ 6698 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 6699 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 6700 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 6701 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 6702 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ 6703 6704 /* Register: RNG_INTENCLR */ 6705 /* Description: Disable interrupt */ 6706 6707 /* Bit 0 : Write '1' to disable interrupt for VALRDY event */ 6708 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 6709 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 6710 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 6711 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 6712 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ 6713 6714 /* Register: RNG_CONFIG */ 6715 /* Description: Configuration register */ 6716 6717 /* Bit 0 : Bias correction */ 6718 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 6719 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 6720 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ 6721 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ 6722 6723 /* Register: RNG_VALUE */ 6724 /* Description: Output random number */ 6725 6726 /* Bits 7..0 : Generated random number */ 6727 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 6728 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 6729 6730 6731 /* Peripheral: RTC */ 6732 /* Description: Real time counter 0 */ 6733 6734 /* Register: RTC_TASKS_START */ 6735 /* Description: Start RTC COUNTER */ 6736 6737 /* Bit 0 : */ 6738 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 6739 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 6740 6741 /* Register: RTC_TASKS_STOP */ 6742 /* Description: Stop RTC COUNTER */ 6743 6744 /* Bit 0 : */ 6745 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 6746 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 6747 6748 /* Register: RTC_TASKS_CLEAR */ 6749 /* Description: Clear RTC COUNTER */ 6750 6751 /* Bit 0 : */ 6752 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 6753 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 6754 6755 /* Register: RTC_TASKS_TRIGOVRFLW */ 6756 /* Description: Set COUNTER to 0xFFFFF0 */ 6757 6758 /* Bit 0 : */ 6759 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ 6760 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ 6761 6762 /* Register: RTC_EVENTS_TICK */ 6763 /* Description: Event on COUNTER increment */ 6764 6765 /* Bit 0 : */ 6766 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ 6767 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ 6768 6769 /* Register: RTC_EVENTS_OVRFLW */ 6770 /* Description: Event on COUNTER overflow */ 6771 6772 /* Bit 0 : */ 6773 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ 6774 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ 6775 6776 /* Register: RTC_EVENTS_COMPARE */ 6777 /* Description: Description collection[n]: Compare event on CC[n] match */ 6778 6779 /* Bit 0 : */ 6780 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 6781 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 6782 6783 /* Register: RTC_INTENSET */ 6784 /* Description: Enable interrupt */ 6785 6786 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ 6787 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6788 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6789 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6790 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6791 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 6792 6793 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ 6794 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6795 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6796 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6797 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6798 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 6799 6800 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ 6801 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6802 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6803 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6804 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6805 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 6806 6807 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ 6808 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6809 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6810 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6811 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6812 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 6813 6814 /* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ 6815 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6816 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6817 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6818 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6819 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ 6820 6821 /* Bit 0 : Write '1' to enable interrupt for TICK event */ 6822 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 6823 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 6824 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 6825 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 6826 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ 6827 6828 /* Register: RTC_INTENCLR */ 6829 /* Description: Disable interrupt */ 6830 6831 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ 6832 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6833 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6834 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6835 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6836 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 6837 6838 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ 6839 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6840 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6841 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6842 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6843 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 6844 6845 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ 6846 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6847 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6848 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6849 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6850 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 6851 6852 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ 6853 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6854 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6855 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6856 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6857 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 6858 6859 /* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ 6860 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6861 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6862 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6863 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6864 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 6865 6866 /* Bit 0 : Write '1' to disable interrupt for TICK event */ 6867 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 6868 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 6869 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 6870 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 6871 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ 6872 6873 /* Register: RTC_EVTEN */ 6874 /* Description: Enable or disable event routing */ 6875 6876 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */ 6877 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6878 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6879 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ 6880 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ 6881 6882 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */ 6883 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6884 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6885 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ 6886 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ 6887 6888 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */ 6889 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6890 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6891 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ 6892 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ 6893 6894 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */ 6895 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6896 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6897 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 6898 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 6899 6900 /* Bit 1 : Enable or disable event routing for OVRFLW event */ 6901 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6902 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6903 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ 6904 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ 6905 6906 /* Bit 0 : Enable or disable event routing for TICK event */ 6907 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 6908 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 6909 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ 6910 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ 6911 6912 /* Register: RTC_EVTENSET */ 6913 /* Description: Enable event routing */ 6914 6915 /* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ 6916 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6917 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6918 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6919 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6920 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ 6921 6922 /* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ 6923 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6924 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6925 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6926 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6927 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ 6928 6929 /* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ 6930 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6931 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6932 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6933 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6934 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ 6935 6936 /* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ 6937 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6938 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6939 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6940 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6941 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ 6942 6943 /* Bit 1 : Write '1' to enable event routing for OVRFLW event */ 6944 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6945 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6946 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6947 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6948 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ 6949 6950 /* Bit 0 : Write '1' to enable event routing for TICK event */ 6951 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 6952 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 6953 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 6954 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 6955 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ 6956 6957 /* Register: RTC_EVTENCLR */ 6958 /* Description: Disable event routing */ 6959 6960 /* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ 6961 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6962 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6963 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 6964 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 6965 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 6966 6967 /* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ 6968 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6969 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6970 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 6971 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 6972 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 6973 6974 /* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ 6975 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6976 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6977 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 6978 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 6979 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 6980 6981 /* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ 6982 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6983 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6984 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 6985 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 6986 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 6987 6988 /* Bit 1 : Write '1' to disable event routing for OVRFLW event */ 6989 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 6990 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 6991 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 6992 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 6993 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 6994 6995 /* Bit 0 : Write '1' to disable event routing for TICK event */ 6996 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 6997 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 6998 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 6999 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 7000 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ 7001 7002 /* Register: RTC_COUNTER */ 7003 /* Description: Current COUNTER value */ 7004 7005 /* Bits 23..0 : Counter value */ 7006 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 7007 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 7008 7009 /* Register: RTC_PRESCALER */ 7010 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ 7011 7012 /* Bits 11..0 : Prescaler value */ 7013 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 7014 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 7015 7016 /* Register: RTC_CC */ 7017 /* Description: Description collection[n]: Compare register n */ 7018 7019 /* Bits 23..0 : Compare value */ 7020 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 7021 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 7022 7023 7024 /* Peripheral: SAADC */ 7025 /* Description: Analog to Digital Converter */ 7026 7027 /* Register: SAADC_TASKS_START */ 7028 /* Description: Start the ADC and prepare the result buffer in RAM */ 7029 7030 /* Bit 0 : */ 7031 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 7032 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 7033 7034 /* Register: SAADC_TASKS_SAMPLE */ 7035 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */ 7036 7037 /* Bit 0 : */ 7038 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ 7039 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ 7040 7041 /* Register: SAADC_TASKS_STOP */ 7042 /* Description: Stop the ADC and terminate any on-going conversion */ 7043 7044 /* Bit 0 : */ 7045 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 7046 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 7047 7048 /* Register: SAADC_TASKS_CALIBRATEOFFSET */ 7049 /* Description: Starts offset auto-calibration */ 7050 7051 /* Bit 0 : */ 7052 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ 7053 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ 7054 7055 /* Register: SAADC_EVENTS_STARTED */ 7056 /* Description: The ADC has started */ 7057 7058 /* Bit 0 : */ 7059 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 7060 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 7061 7062 /* Register: SAADC_EVENTS_END */ 7063 /* Description: The ADC has filled up the Result buffer */ 7064 7065 /* Bit 0 : */ 7066 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 7067 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 7068 7069 /* Register: SAADC_EVENTS_DONE */ 7070 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 7071 7072 /* Bit 0 : */ 7073 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 7074 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 7075 7076 /* Register: SAADC_EVENTS_RESULTDONE */ 7077 /* Description: A result is ready to get transferred to RAM. */ 7078 7079 /* Bit 0 : */ 7080 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ 7081 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ 7082 7083 /* Register: SAADC_EVENTS_CALIBRATEDONE */ 7084 /* Description: Calibration is complete */ 7085 7086 /* Bit 0 : */ 7087 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ 7088 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ 7089 7090 /* Register: SAADC_EVENTS_STOPPED */ 7091 /* Description: The ADC has stopped */ 7092 7093 /* Bit 0 : */ 7094 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 7095 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 7096 7097 /* Register: SAADC_EVENTS_CH_LIMITH */ 7098 /* Description: Description cluster[n]: Last results is equal or above CH[n].LIMIT.HIGH */ 7099 7100 /* Bit 0 : */ 7101 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ 7102 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ 7103 7104 /* Register: SAADC_EVENTS_CH_LIMITL */ 7105 /* Description: Description cluster[n]: Last results is equal or below CH[n].LIMIT.LOW */ 7106 7107 /* Bit 0 : */ 7108 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ 7109 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ 7110 7111 /* Register: SAADC_INTEN */ 7112 /* Description: Enable or disable interrupt */ 7113 7114 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ 7115 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 7116 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 7117 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ 7118 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ 7119 7120 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ 7121 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 7122 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 7123 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ 7124 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ 7125 7126 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ 7127 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 7128 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 7129 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ 7130 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ 7131 7132 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ 7133 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 7134 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 7135 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ 7136 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ 7137 7138 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ 7139 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 7140 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 7141 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ 7142 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ 7143 7144 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ 7145 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 7146 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 7147 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ 7148 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ 7149 7150 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ 7151 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 7152 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 7153 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ 7154 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ 7155 7156 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ 7157 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 7158 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 7159 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ 7160 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ 7161 7162 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ 7163 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 7164 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 7165 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ 7166 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ 7167 7168 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ 7169 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 7170 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 7171 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ 7172 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ 7173 7174 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ 7175 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 7176 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 7177 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ 7178 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ 7179 7180 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ 7181 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 7182 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 7183 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ 7184 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ 7185 7186 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ 7187 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 7188 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 7189 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ 7190 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ 7191 7192 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ 7193 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 7194 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 7195 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ 7196 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ 7197 7198 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ 7199 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 7200 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 7201 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ 7202 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ 7203 7204 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ 7205 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 7206 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 7207 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ 7208 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ 7209 7210 /* Bit 5 : Enable or disable interrupt for STOPPED event */ 7211 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 7212 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7213 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 7214 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 7215 7216 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ 7217 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 7218 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 7219 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ 7220 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ 7221 7222 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */ 7223 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 7224 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 7225 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ 7226 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ 7227 7228 /* Bit 2 : Enable or disable interrupt for DONE event */ 7229 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ 7230 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 7231 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ 7232 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ 7233 7234 /* Bit 1 : Enable or disable interrupt for END event */ 7235 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ 7236 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ 7237 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ 7238 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ 7239 7240 /* Bit 0 : Enable or disable interrupt for STARTED event */ 7241 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 7242 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7243 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 7244 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 7245 7246 /* Register: SAADC_INTENSET */ 7247 /* Description: Enable interrupt */ 7248 7249 /* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ 7250 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 7251 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 7252 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7253 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7254 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ 7255 7256 /* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ 7257 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 7258 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 7259 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7260 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7261 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ 7262 7263 /* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ 7264 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 7265 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 7266 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7267 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7268 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ 7269 7270 /* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ 7271 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 7272 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 7273 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7274 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7275 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ 7276 7277 /* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ 7278 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 7279 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 7280 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7281 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7282 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ 7283 7284 /* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ 7285 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 7286 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 7287 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7288 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7289 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ 7290 7291 /* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ 7292 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 7293 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 7294 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7295 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7296 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ 7297 7298 /* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ 7299 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 7300 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 7301 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7302 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7303 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ 7304 7305 /* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ 7306 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 7307 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 7308 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7309 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7310 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ 7311 7312 /* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ 7313 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 7314 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 7315 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7316 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7317 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ 7318 7319 /* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ 7320 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 7321 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 7322 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7323 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7324 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ 7325 7326 /* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ 7327 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 7328 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 7329 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7330 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7331 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ 7332 7333 /* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ 7334 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 7335 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 7336 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7337 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7338 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ 7339 7340 /* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ 7341 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 7342 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 7343 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7344 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7345 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ 7346 7347 /* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ 7348 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 7349 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 7350 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7351 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7352 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ 7353 7354 /* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ 7355 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 7356 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 7357 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7358 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7359 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ 7360 7361 /* Bit 5 : Write '1' to enable interrupt for STOPPED event */ 7362 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 7363 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7364 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7365 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7366 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 7367 7368 /* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ 7369 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 7370 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 7371 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 7372 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 7373 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ 7374 7375 /* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ 7376 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 7377 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 7378 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 7379 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 7380 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ 7381 7382 /* Bit 2 : Write '1' to enable interrupt for DONE event */ 7383 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ 7384 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 7385 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 7386 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 7387 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ 7388 7389 /* Bit 1 : Write '1' to enable interrupt for END event */ 7390 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 7391 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 7392 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 7393 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 7394 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ 7395 7396 /* Bit 0 : Write '1' to enable interrupt for STARTED event */ 7397 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 7398 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7399 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7400 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7401 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ 7402 7403 /* Register: SAADC_INTENCLR */ 7404 /* Description: Disable interrupt */ 7405 7406 /* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ 7407 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 7408 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 7409 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7410 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7411 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ 7412 7413 /* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ 7414 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 7415 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 7416 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7417 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7418 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ 7419 7420 /* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ 7421 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 7422 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 7423 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7424 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7425 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ 7426 7427 /* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ 7428 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 7429 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 7430 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7431 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7432 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ 7433 7434 /* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ 7435 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 7436 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 7437 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7438 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7439 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ 7440 7441 /* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ 7442 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 7443 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 7444 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7445 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7446 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ 7447 7448 /* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ 7449 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 7450 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 7451 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7452 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7453 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ 7454 7455 /* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ 7456 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 7457 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 7458 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7459 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7460 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ 7461 7462 /* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ 7463 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 7464 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 7465 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7466 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7467 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ 7468 7469 /* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ 7470 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 7471 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 7472 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7473 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7474 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ 7475 7476 /* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ 7477 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 7478 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 7479 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7480 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7481 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ 7482 7483 /* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ 7484 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 7485 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 7486 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7487 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7488 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ 7489 7490 /* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ 7491 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 7492 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 7493 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7494 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7495 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ 7496 7497 /* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ 7498 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 7499 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 7500 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7501 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7502 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ 7503 7504 /* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ 7505 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 7506 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 7507 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 7508 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 7509 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ 7510 7511 /* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ 7512 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 7513 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 7514 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 7515 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 7516 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ 7517 7518 /* Bit 5 : Write '1' to disable interrupt for STOPPED event */ 7519 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 7520 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7521 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7522 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7523 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 7524 7525 /* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ 7526 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 7527 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 7528 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 7529 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 7530 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ 7531 7532 /* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ 7533 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 7534 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 7535 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 7536 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 7537 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ 7538 7539 /* Bit 2 : Write '1' to disable interrupt for DONE event */ 7540 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ 7541 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 7542 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 7543 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 7544 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 7545 7546 /* Bit 1 : Write '1' to disable interrupt for END event */ 7547 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 7548 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 7549 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 7550 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 7551 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ 7552 7553 /* Bit 0 : Write '1' to disable interrupt for STARTED event */ 7554 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 7555 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7556 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7557 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7558 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 7559 7560 /* Register: SAADC_STATUS */ 7561 /* Description: Status */ 7562 7563 /* Bit 0 : Status */ 7564 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 7565 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 7566 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ 7567 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ 7568 7569 /* Register: SAADC_ENABLE */ 7570 /* Description: Enable or disable ADC */ 7571 7572 /* Bit 0 : Enable or disable ADC */ 7573 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 7574 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 7575 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ 7576 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ 7577 7578 /* Register: SAADC_CH_PSELP */ 7579 /* Description: Description cluster[n]: Input positive pin selection for CH[n] */ 7580 7581 /* Bits 4..0 : Analog positive input channel */ 7582 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ 7583 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ 7584 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ 7585 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ 7586 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ 7587 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ 7588 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ 7589 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ 7590 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ 7591 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ 7592 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ 7593 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ 7594 7595 /* Register: SAADC_CH_PSELN */ 7596 /* Description: Description cluster[n]: Input negative pin selection for CH[n] */ 7597 7598 /* Bits 4..0 : Analog negative input, enables differential channel */ 7599 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ 7600 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ 7601 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ 7602 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ 7603 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ 7604 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ 7605 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ 7606 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ 7607 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ 7608 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ 7609 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ 7610 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ 7611 7612 /* Register: SAADC_CH_CONFIG */ 7613 /* Description: Description cluster[n]: Input configuration for CH[n] */ 7614 7615 /* Bit 24 : Enable burst mode */ 7616 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ 7617 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ 7618 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ 7619 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ 7620 7621 /* Bit 20 : Enable differential mode */ 7622 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ 7623 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 7624 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ 7625 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ 7626 7627 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ 7628 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ 7629 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ 7630 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ 7631 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ 7632 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ 7633 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ 7634 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ 7635 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ 7636 7637 /* Bit 12 : Reference control */ 7638 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ 7639 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 7640 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ 7641 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ 7642 7643 /* Bits 10..8 : Gain control */ 7644 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ 7645 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ 7646 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ 7647 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ 7648 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ 7649 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ 7650 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ 7651 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ 7652 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ 7653 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ 7654 7655 /* Bits 5..4 : Negative channel resistor control */ 7656 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ 7657 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ 7658 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ 7659 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ 7660 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ 7661 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ 7662 7663 /* Bits 1..0 : Positive channel resistor control */ 7664 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ 7665 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ 7666 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ 7667 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ 7668 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ 7669 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ 7670 7671 /* Register: SAADC_CH_LIMIT */ 7672 /* Description: Description cluster[n]: High/low limits for event monitoring a channel */ 7673 7674 /* Bits 31..16 : High level limit */ 7675 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ 7676 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ 7677 7678 /* Bits 15..0 : Low level limit */ 7679 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ 7680 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ 7681 7682 /* Register: SAADC_RESOLUTION */ 7683 /* Description: Resolution configuration */ 7684 7685 /* Bits 2..0 : Set the resolution */ 7686 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ 7687 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ 7688 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ 7689 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ 7690 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ 7691 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ 7692 7693 /* Register: SAADC_OVERSAMPLE */ 7694 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ 7695 7696 /* Bits 3..0 : Oversample control */ 7697 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ 7698 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ 7699 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ 7700 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ 7701 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ 7702 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ 7703 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ 7704 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ 7705 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ 7706 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ 7707 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ 7708 7709 /* Register: SAADC_SAMPLERATE */ 7710 /* Description: Controls normal or continuous sample rate */ 7711 7712 /* Bit 12 : Select mode for sample rate control */ 7713 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ 7714 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ 7715 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ 7716 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ 7717 7718 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ 7719 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ 7720 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ 7721 7722 /* Register: SAADC_RESULT_PTR */ 7723 /* Description: Data pointer */ 7724 7725 /* Bits 31..0 : Data pointer */ 7726 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7727 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7728 7729 /* Register: SAADC_RESULT_MAXCNT */ 7730 /* Description: Maximum number of buffer words to transfer */ 7731 7732 /* Bits 14..0 : Maximum number of buffer words to transfer */ 7733 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7734 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7735 7736 /* Register: SAADC_RESULT_AMOUNT */ 7737 /* Description: Number of buffer words transferred since last START */ 7738 7739 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ 7740 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7741 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7742 7743 7744 /* Peripheral: SPIM */ 7745 /* Description: Serial Peripheral Interface Master with EasyDMA */ 7746 7747 /* Register: SPIM_TASKS_START */ 7748 /* Description: Start SPI transaction */ 7749 7750 /* Bit 0 : */ 7751 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 7752 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 7753 7754 /* Register: SPIM_TASKS_STOP */ 7755 /* Description: Stop SPI transaction */ 7756 7757 /* Bit 0 : */ 7758 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 7759 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 7760 7761 /* Register: SPIM_TASKS_SUSPEND */ 7762 /* Description: Suspend SPI transaction */ 7763 7764 /* Bit 0 : */ 7765 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 7766 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 7767 7768 /* Register: SPIM_TASKS_RESUME */ 7769 /* Description: Resume SPI transaction */ 7770 7771 /* Bit 0 : */ 7772 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 7773 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 7774 7775 /* Register: SPIM_EVENTS_STOPPED */ 7776 /* Description: SPI transaction has stopped */ 7777 7778 /* Bit 0 : */ 7779 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 7780 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 7781 7782 /* Register: SPIM_EVENTS_ENDRX */ 7783 /* Description: End of RXD buffer reached */ 7784 7785 /* Bit 0 : */ 7786 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 7787 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 7788 7789 /* Register: SPIM_EVENTS_END */ 7790 /* Description: End of RXD buffer and TXD buffer reached */ 7791 7792 /* Bit 0 : */ 7793 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 7794 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 7795 7796 /* Register: SPIM_EVENTS_ENDTX */ 7797 /* Description: End of TXD buffer reached */ 7798 7799 /* Bit 0 : */ 7800 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 7801 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 7802 7803 /* Register: SPIM_EVENTS_STARTED */ 7804 /* Description: Transaction started */ 7805 7806 /* Bit 0 : */ 7807 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 7808 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 7809 7810 /* Register: SPIM_SHORTS */ 7811 /* Description: Shortcut register */ 7812 7813 /* Bit 17 : Shortcut between END event and START task */ 7814 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 7815 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 7816 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 7817 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 7818 7819 /* Register: SPIM_INTENSET */ 7820 /* Description: Enable interrupt */ 7821 7822 /* Bit 19 : Write '1' to enable interrupt for STARTED event */ 7823 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 7824 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7825 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7826 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7827 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 7828 7829 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */ 7830 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 7831 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 7832 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 7833 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 7834 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 7835 7836 /* Bit 6 : Write '1' to enable interrupt for END event */ 7837 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 7838 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 7839 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 7840 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 7841 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ 7842 7843 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */ 7844 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7845 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7846 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7847 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7848 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 7849 7850 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */ 7851 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 7852 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7853 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7854 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7855 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 7856 7857 /* Register: SPIM_INTENCLR */ 7858 /* Description: Disable interrupt */ 7859 7860 /* Bit 19 : Write '1' to disable interrupt for STARTED event */ 7861 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 7862 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 7863 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 7864 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 7865 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 7866 7867 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */ 7868 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 7869 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 7870 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 7871 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 7872 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 7873 7874 /* Bit 6 : Write '1' to disable interrupt for END event */ 7875 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 7876 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 7877 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 7878 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 7879 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ 7880 7881 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */ 7882 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 7883 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 7884 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 7885 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 7886 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 7887 7888 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */ 7889 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 7890 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 7891 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 7892 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 7893 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 7894 7895 /* Register: SPIM_ENABLE */ 7896 /* Description: Enable SPIM */ 7897 7898 /* Bits 3..0 : Enable or disable SPIM */ 7899 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 7900 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 7901 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ 7902 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ 7903 7904 /* Register: SPIM_PSEL_SCK */ 7905 /* Description: Pin select for SCK */ 7906 7907 /* Bit 31 : Connection */ 7908 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7909 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7910 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 7911 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7912 7913 /* Bits 4..0 : Pin number */ 7914 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 7915 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 7916 7917 /* Register: SPIM_PSEL_MOSI */ 7918 /* Description: Pin select for MOSI signal */ 7919 7920 /* Bit 31 : Connection */ 7921 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7922 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7923 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 7924 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7925 7926 /* Bits 4..0 : Pin number */ 7927 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 7928 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 7929 7930 /* Register: SPIM_PSEL_MISO */ 7931 /* Description: Pin select for MISO signal */ 7932 7933 /* Bit 31 : Connection */ 7934 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 7935 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 7936 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 7937 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 7938 7939 /* Bits 4..0 : Pin number */ 7940 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 7941 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 7942 7943 /* Register: SPIM_FREQUENCY */ 7944 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ 7945 7946 /* Bits 31..0 : SPI master data rate */ 7947 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 7948 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 7949 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 7950 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 7951 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 7952 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 7953 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 7954 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 7955 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 7956 7957 /* Register: SPIM_RXD_PTR */ 7958 /* Description: Data pointer */ 7959 7960 /* Bits 31..0 : Data pointer */ 7961 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7962 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7963 7964 /* Register: SPIM_RXD_MAXCNT */ 7965 /* Description: Maximum number of bytes in receive buffer */ 7966 7967 /* Bits 9..0 : Maximum number of bytes in receive buffer */ 7968 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7969 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 7970 7971 /* Register: SPIM_RXD_AMOUNT */ 7972 /* Description: Number of bytes transferred in the last transaction */ 7973 7974 /* Bits 9..0 : Number of bytes transferred in the last transaction */ 7975 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 7976 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 7977 7978 /* Register: SPIM_RXD_LIST */ 7979 /* Description: EasyDMA list type */ 7980 7981 /* Bits 2..0 : List type */ 7982 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 7983 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 7984 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 7985 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 7986 7987 /* Register: SPIM_TXD_PTR */ 7988 /* Description: Data pointer */ 7989 7990 /* Bits 31..0 : Data pointer */ 7991 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 7992 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 7993 7994 /* Register: SPIM_TXD_MAXCNT */ 7995 /* Description: Maximum number of bytes in transmit buffer */ 7996 7997 /* Bits 9..0 : Maximum number of bytes in transmit buffer */ 7998 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 7999 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 8000 8001 /* Register: SPIM_TXD_AMOUNT */ 8002 /* Description: Number of bytes transferred in the last transaction */ 8003 8004 /* Bits 9..0 : Number of bytes transferred in the last transaction */ 8005 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 8006 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 8007 8008 /* Register: SPIM_TXD_LIST */ 8009 /* Description: EasyDMA list type */ 8010 8011 /* Bits 2..0 : List type */ 8012 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 8013 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 8014 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 8015 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 8016 8017 /* Register: SPIM_CONFIG */ 8018 /* Description: Configuration register */ 8019 8020 /* Bit 2 : Serial clock (SCK) polarity */ 8021 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 8022 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 8023 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 8024 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 8025 8026 /* Bit 1 : Serial clock (SCK) phase */ 8027 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 8028 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 8029 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 8030 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 8031 8032 /* Bit 0 : Bit order */ 8033 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 8034 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 8035 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 8036 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 8037 8038 /* Register: SPIM_ORC */ 8039 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ 8040 8041 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ 8042 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 8043 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 8044 8045 8046 /* Peripheral: SPIS */ 8047 /* Description: SPI Slave */ 8048 8049 /* Register: SPIS_TASKS_ACQUIRE */ 8050 /* Description: Acquire SPI semaphore */ 8051 8052 /* Bit 0 : */ 8053 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ 8054 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ 8055 8056 /* Register: SPIS_TASKS_RELEASE */ 8057 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ 8058 8059 /* Bit 0 : */ 8060 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ 8061 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ 8062 8063 /* Register: SPIS_EVENTS_END */ 8064 /* Description: Granted transaction completed */ 8065 8066 /* Bit 0 : */ 8067 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 8068 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 8069 8070 /* Register: SPIS_EVENTS_ENDRX */ 8071 /* Description: End of RXD buffer reached */ 8072 8073 /* Bit 0 : */ 8074 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 8075 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 8076 8077 /* Register: SPIS_EVENTS_ACQUIRED */ 8078 /* Description: Semaphore acquired */ 8079 8080 /* Bit 0 : */ 8081 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ 8082 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ 8083 8084 /* Register: SPIS_SHORTS */ 8085 /* Description: Shortcut register */ 8086 8087 /* Bit 2 : Shortcut between END event and ACQUIRE task */ 8088 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 8089 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 8090 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ 8091 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ 8092 8093 /* Register: SPIS_INTENSET */ 8094 /* Description: Enable interrupt */ 8095 8096 /* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ 8097 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 8098 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 8099 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 8100 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 8101 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ 8102 8103 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */ 8104 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 8105 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 8106 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 8107 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 8108 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 8109 8110 /* Bit 1 : Write '1' to enable interrupt for END event */ 8111 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 8112 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 8113 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 8114 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 8115 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ 8116 8117 /* Register: SPIS_INTENCLR */ 8118 /* Description: Disable interrupt */ 8119 8120 /* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ 8121 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 8122 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 8123 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 8124 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 8125 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ 8126 8127 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */ 8128 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 8129 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 8130 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 8131 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 8132 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 8133 8134 /* Bit 1 : Write '1' to disable interrupt for END event */ 8135 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 8136 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 8137 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 8138 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 8139 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ 8140 8141 /* Register: SPIS_SEMSTAT */ 8142 /* Description: Semaphore status register */ 8143 8144 /* Bits 1..0 : Semaphore status */ 8145 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 8146 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 8147 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ 8148 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ 8149 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ 8150 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ 8151 8152 /* Register: SPIS_STATUS */ 8153 /* Description: Status from last transaction */ 8154 8155 /* Bit 1 : RX buffer overflow detected, and prevented */ 8156 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 8157 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 8158 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ 8159 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ 8160 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ 8161 8162 /* Bit 0 : TX buffer over-read detected, and prevented */ 8163 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 8164 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 8165 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ 8166 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ 8167 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ 8168 8169 /* Register: SPIS_ENABLE */ 8170 /* Description: Enable SPI slave */ 8171 8172 /* Bits 3..0 : Enable or disable SPI slave */ 8173 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 8174 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 8175 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ 8176 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ 8177 8178 /* Register: SPIS_PSEL_SCK */ 8179 /* Description: Pin select for SCK */ 8180 8181 /* Bit 31 : Connection */ 8182 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8183 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8184 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 8185 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8186 8187 /* Bits 4..0 : Pin number */ 8188 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 8189 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 8190 8191 /* Register: SPIS_PSEL_MISO */ 8192 /* Description: Pin select for MISO signal */ 8193 8194 /* Bit 31 : Connection */ 8195 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8196 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8197 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 8198 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8199 8200 /* Bits 4..0 : Pin number */ 8201 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 8202 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 8203 8204 /* Register: SPIS_PSEL_MOSI */ 8205 /* Description: Pin select for MOSI signal */ 8206 8207 /* Bit 31 : Connection */ 8208 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8209 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8210 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 8211 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8212 8213 /* Bits 4..0 : Pin number */ 8214 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 8215 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 8216 8217 /* Register: SPIS_PSEL_CSN */ 8218 /* Description: Pin select for CSN signal */ 8219 8220 /* Bit 31 : Connection */ 8221 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 8222 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 8223 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ 8224 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 8225 8226 /* Bits 4..0 : Pin number */ 8227 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ 8228 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ 8229 8230 /* Register: SPIS_RXD_PTR */ 8231 /* Description: RXD data pointer */ 8232 8233 /* Bits 31..0 : RXD data pointer */ 8234 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 8235 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 8236 8237 /* Register: SPIS_RXD_MAXCNT */ 8238 /* Description: Maximum number of bytes in receive buffer */ 8239 8240 /* Bits 9..0 : Maximum number of bytes in receive buffer */ 8241 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 8242 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 8243 8244 /* Register: SPIS_RXD_AMOUNT */ 8245 /* Description: Number of bytes received in last granted transaction */ 8246 8247 /* Bits 9..0 : Number of bytes received in the last granted transaction */ 8248 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 8249 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 8250 8251 /* Register: SPIS_TXD_PTR */ 8252 /* Description: TXD data pointer */ 8253 8254 /* Bits 31..0 : TXD data pointer */ 8255 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 8256 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 8257 8258 /* Register: SPIS_TXD_MAXCNT */ 8259 /* Description: Maximum number of bytes in transmit buffer */ 8260 8261 /* Bits 9..0 : Maximum number of bytes in transmit buffer */ 8262 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 8263 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 8264 8265 /* Register: SPIS_TXD_AMOUNT */ 8266 /* Description: Number of bytes transmitted in last granted transaction */ 8267 8268 /* Bits 9..0 : Number of bytes transmitted in last granted transaction */ 8269 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 8270 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 8271 8272 /* Register: SPIS_CONFIG */ 8273 /* Description: Configuration register */ 8274 8275 /* Bit 2 : Serial clock (SCK) polarity */ 8276 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 8277 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 8278 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 8279 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 8280 8281 /* Bit 1 : Serial clock (SCK) phase */ 8282 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 8283 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 8284 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 8285 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 8286 8287 /* Bit 0 : Bit order */ 8288 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 8289 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 8290 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 8291 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 8292 8293 /* Register: SPIS_DEF */ 8294 /* Description: Default character. Character clocked out in case of an ignored transaction. */ 8295 8296 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ 8297 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 8298 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 8299 8300 /* Register: SPIS_ORC */ 8301 /* Description: Over-read character */ 8302 8303 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ 8304 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 8305 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 8306 8307 8308 /* Peripheral: TEMP */ 8309 /* Description: Temperature Sensor */ 8310 8311 /* Register: TEMP_TASKS_START */ 8312 /* Description: Start temperature measurement */ 8313 8314 /* Bit 0 : */ 8315 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 8316 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 8317 8318 /* Register: TEMP_TASKS_STOP */ 8319 /* Description: Stop temperature measurement */ 8320 8321 /* Bit 0 : */ 8322 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8323 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8324 8325 /* Register: TEMP_EVENTS_DATARDY */ 8326 /* Description: Temperature measurement complete, data ready */ 8327 8328 /* Bit 0 : */ 8329 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ 8330 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ 8331 8332 /* Register: TEMP_INTENSET */ 8333 /* Description: Enable interrupt */ 8334 8335 /* Bit 0 : Write '1' to enable interrupt for DATARDY event */ 8336 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 8337 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 8338 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 8339 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 8340 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ 8341 8342 /* Register: TEMP_INTENCLR */ 8343 /* Description: Disable interrupt */ 8344 8345 /* Bit 0 : Write '1' to disable interrupt for DATARDY event */ 8346 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 8347 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 8348 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 8349 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 8350 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ 8351 8352 /* Register: TEMP_TEMP */ 8353 /* Description: Temperature in degC (0.25deg steps) */ 8354 8355 /* Bits 31..0 : Temperature in degC (0.25deg steps) */ 8356 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ 8357 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ 8358 8359 /* Register: TEMP_A0 */ 8360 /* Description: Slope of 1st piece wise linear function */ 8361 8362 /* Bits 11..0 : Slope of 1st piece wise linear function */ 8363 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ 8364 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ 8365 8366 /* Register: TEMP_A1 */ 8367 /* Description: Slope of 2nd piece wise linear function */ 8368 8369 /* Bits 11..0 : Slope of 2nd piece wise linear function */ 8370 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ 8371 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ 8372 8373 /* Register: TEMP_A2 */ 8374 /* Description: Slope of 3rd piece wise linear function */ 8375 8376 /* Bits 11..0 : Slope of 3rd piece wise linear function */ 8377 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ 8378 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ 8379 8380 /* Register: TEMP_A3 */ 8381 /* Description: Slope of 4th piece wise linear function */ 8382 8383 /* Bits 11..0 : Slope of 4th piece wise linear function */ 8384 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ 8385 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ 8386 8387 /* Register: TEMP_A4 */ 8388 /* Description: Slope of 5th piece wise linear function */ 8389 8390 /* Bits 11..0 : Slope of 5th piece wise linear function */ 8391 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ 8392 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ 8393 8394 /* Register: TEMP_A5 */ 8395 /* Description: Slope of 6th piece wise linear function */ 8396 8397 /* Bits 11..0 : Slope of 6th piece wise linear function */ 8398 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ 8399 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ 8400 8401 /* Register: TEMP_B0 */ 8402 /* Description: y-intercept of 1st piece wise linear function */ 8403 8404 /* Bits 13..0 : y-intercept of 1st piece wise linear function */ 8405 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ 8406 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ 8407 8408 /* Register: TEMP_B1 */ 8409 /* Description: y-intercept of 2nd piece wise linear function */ 8410 8411 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */ 8412 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ 8413 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ 8414 8415 /* Register: TEMP_B2 */ 8416 /* Description: y-intercept of 3rd piece wise linear function */ 8417 8418 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */ 8419 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ 8420 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ 8421 8422 /* Register: TEMP_B3 */ 8423 /* Description: y-intercept of 4th piece wise linear function */ 8424 8425 /* Bits 13..0 : y-intercept of 4th piece wise linear function */ 8426 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ 8427 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ 8428 8429 /* Register: TEMP_B4 */ 8430 /* Description: y-intercept of 5th piece wise linear function */ 8431 8432 /* Bits 13..0 : y-intercept of 5th piece wise linear function */ 8433 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ 8434 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ 8435 8436 /* Register: TEMP_B5 */ 8437 /* Description: y-intercept of 6th piece wise linear function */ 8438 8439 /* Bits 13..0 : y-intercept of 6th piece wise linear function */ 8440 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ 8441 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ 8442 8443 /* Register: TEMP_T0 */ 8444 /* Description: End point of 1st piece wise linear function */ 8445 8446 /* Bits 7..0 : End point of 1st piece wise linear function */ 8447 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ 8448 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ 8449 8450 /* Register: TEMP_T1 */ 8451 /* Description: End point of 2nd piece wise linear function */ 8452 8453 /* Bits 7..0 : End point of 2nd piece wise linear function */ 8454 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ 8455 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ 8456 8457 /* Register: TEMP_T2 */ 8458 /* Description: End point of 3rd piece wise linear function */ 8459 8460 /* Bits 7..0 : End point of 3rd piece wise linear function */ 8461 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ 8462 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ 8463 8464 /* Register: TEMP_T3 */ 8465 /* Description: End point of 4th piece wise linear function */ 8466 8467 /* Bits 7..0 : End point of 4th piece wise linear function */ 8468 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ 8469 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ 8470 8471 /* Register: TEMP_T4 */ 8472 /* Description: End point of 5th piece wise linear function */ 8473 8474 /* Bits 7..0 : End point of 5th piece wise linear function */ 8475 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ 8476 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ 8477 8478 8479 /* Peripheral: TIMER */ 8480 /* Description: Timer/Counter 0 */ 8481 8482 /* Register: TIMER_TASKS_START */ 8483 /* Description: Start Timer */ 8484 8485 /* Bit 0 : */ 8486 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 8487 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 8488 8489 /* Register: TIMER_TASKS_STOP */ 8490 /* Description: Stop Timer */ 8491 8492 /* Bit 0 : */ 8493 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8494 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8495 8496 /* Register: TIMER_TASKS_COUNT */ 8497 /* Description: Increment Timer (Counter mode only) */ 8498 8499 /* Bit 0 : */ 8500 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ 8501 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ 8502 8503 /* Register: TIMER_TASKS_CLEAR */ 8504 /* Description: Clear time */ 8505 8506 /* Bit 0 : */ 8507 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 8508 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 8509 8510 /* Register: TIMER_TASKS_SHUTDOWN */ 8511 /* Description: Deprecated register - Shut down timer */ 8512 8513 /* Bit 0 : */ 8514 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ 8515 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ 8516 8517 /* Register: TIMER_TASKS_CAPTURE */ 8518 /* Description: Description collection[n]: Capture Timer value to CC[n] register */ 8519 8520 /* Bit 0 : */ 8521 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 8522 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 8523 8524 /* Register: TIMER_EVENTS_COMPARE */ 8525 /* Description: Description collection[n]: Compare event on CC[n] match */ 8526 8527 /* Bit 0 : */ 8528 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 8529 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 8530 8531 /* Register: TIMER_SHORTS */ 8532 /* Description: Shortcut register */ 8533 8534 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ 8535 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ 8536 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ 8537 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ 8538 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ 8539 8540 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ 8541 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ 8542 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ 8543 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ 8544 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ 8545 8546 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ 8547 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 8548 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 8549 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ 8550 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ 8551 8552 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ 8553 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 8554 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 8555 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ 8556 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ 8557 8558 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ 8559 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 8560 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 8561 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ 8562 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ 8563 8564 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ 8565 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 8566 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 8567 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ 8568 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ 8569 8570 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ 8571 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ 8572 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ 8573 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8574 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8575 8576 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ 8577 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ 8578 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ 8579 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8580 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8581 8582 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ 8583 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 8584 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 8585 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8586 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8587 8588 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ 8589 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 8590 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 8591 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8592 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8593 8594 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ 8595 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 8596 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 8597 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8598 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8599 8600 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ 8601 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 8602 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 8603 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 8604 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 8605 8606 /* Register: TIMER_INTENSET */ 8607 /* Description: Enable interrupt */ 8608 8609 /* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ 8610 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 8611 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 8612 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 8613 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 8614 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ 8615 8616 /* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ 8617 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 8618 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 8619 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 8620 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 8621 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ 8622 8623 /* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ 8624 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 8625 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 8626 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 8627 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 8628 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 8629 8630 /* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ 8631 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 8632 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 8633 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 8634 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 8635 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 8636 8637 /* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ 8638 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 8639 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 8640 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 8641 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 8642 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 8643 8644 /* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ 8645 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 8646 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 8647 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 8648 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 8649 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 8650 8651 /* Register: TIMER_INTENCLR */ 8652 /* Description: Disable interrupt */ 8653 8654 /* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ 8655 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 8656 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 8657 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 8658 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 8659 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ 8660 8661 /* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ 8662 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 8663 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 8664 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 8665 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 8666 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ 8667 8668 /* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ 8669 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 8670 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 8671 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 8672 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 8673 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 8674 8675 /* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ 8676 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 8677 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 8678 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 8679 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 8680 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 8681 8682 /* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ 8683 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 8684 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 8685 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 8686 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 8687 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 8688 8689 /* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ 8690 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 8691 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 8692 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 8693 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 8694 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 8695 8696 /* Register: TIMER_MODE */ 8697 /* Description: Timer mode selection */ 8698 8699 /* Bits 1..0 : Timer mode */ 8700 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 8701 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 8702 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ 8703 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ 8704 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ 8705 8706 /* Register: TIMER_BITMODE */ 8707 /* Description: Configure the number of bits used by the TIMER */ 8708 8709 /* Bits 1..0 : Timer bit width */ 8710 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 8711 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 8712 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ 8713 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ 8714 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ 8715 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ 8716 8717 /* Register: TIMER_PRESCALER */ 8718 /* Description: Timer prescaler register */ 8719 8720 /* Bits 3..0 : Prescaler value */ 8721 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 8722 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 8723 8724 /* Register: TIMER_CC */ 8725 /* Description: Description collection[n]: Capture/Compare register n */ 8726 8727 /* Bits 31..0 : Capture/Compare value */ 8728 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 8729 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 8730 8731 8732 /* Peripheral: TWIM */ 8733 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA */ 8734 8735 /* Register: TWIM_TASKS_STARTRX */ 8736 /* Description: Start TWI receive sequence */ 8737 8738 /* Bit 0 : */ 8739 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 8740 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 8741 8742 /* Register: TWIM_TASKS_STARTTX */ 8743 /* Description: Start TWI transmit sequence */ 8744 8745 /* Bit 0 : */ 8746 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 8747 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 8748 8749 /* Register: TWIM_TASKS_STOP */ 8750 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 8751 8752 /* Bit 0 : */ 8753 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8754 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8755 8756 /* Register: TWIM_TASKS_SUSPEND */ 8757 /* Description: Suspend TWI transaction */ 8758 8759 /* Bit 0 : */ 8760 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 8761 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 8762 8763 /* Register: TWIM_TASKS_RESUME */ 8764 /* Description: Resume TWI transaction */ 8765 8766 /* Bit 0 : */ 8767 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 8768 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 8769 8770 /* Register: TWIM_EVENTS_STOPPED */ 8771 /* Description: TWI stopped */ 8772 8773 /* Bit 0 : */ 8774 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 8775 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 8776 8777 /* Register: TWIM_EVENTS_ERROR */ 8778 /* Description: TWI error */ 8779 8780 /* Bit 0 : */ 8781 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 8782 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 8783 8784 /* Register: TWIM_EVENTS_SUSPENDED */ 8785 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ 8786 8787 /* Bit 0 : */ 8788 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ 8789 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ 8790 8791 /* Register: TWIM_EVENTS_RXSTARTED */ 8792 /* Description: Receive sequence started */ 8793 8794 /* Bit 0 : */ 8795 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 8796 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 8797 8798 /* Register: TWIM_EVENTS_TXSTARTED */ 8799 /* Description: Transmit sequence started */ 8800 8801 /* Bit 0 : */ 8802 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 8803 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 8804 8805 /* Register: TWIM_EVENTS_LASTRX */ 8806 /* Description: Byte boundary, starting to receive the last byte */ 8807 8808 /* Bit 0 : */ 8809 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ 8810 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ 8811 8812 /* Register: TWIM_EVENTS_LASTTX */ 8813 /* Description: Byte boundary, starting to transmit the last byte */ 8814 8815 /* Bit 0 : */ 8816 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ 8817 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ 8818 8819 /* Register: TWIM_SHORTS */ 8820 /* Description: Shortcut register */ 8821 8822 /* Bit 12 : Shortcut between LASTRX event and STOP task */ 8823 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ 8824 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ 8825 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ 8826 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ 8827 8828 /* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ 8829 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ 8830 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ 8831 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8832 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8833 8834 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */ 8835 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ 8836 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ 8837 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ 8838 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ 8839 8840 /* Bit 9 : Shortcut between LASTTX event and STOP task */ 8841 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ 8842 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ 8843 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ 8844 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ 8845 8846 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ 8847 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ 8848 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ 8849 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 8850 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 8851 8852 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */ 8853 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ 8854 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ 8855 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 8856 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 8857 8858 /* Register: TWIM_INTEN */ 8859 /* Description: Enable or disable interrupt */ 8860 8861 /* Bit 24 : Enable or disable interrupt for LASTTX event */ 8862 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 8863 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 8864 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ 8865 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ 8866 8867 /* Bit 23 : Enable or disable interrupt for LASTRX event */ 8868 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 8869 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 8870 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ 8871 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ 8872 8873 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */ 8874 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8875 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8876 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 8877 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 8878 8879 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */ 8880 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8881 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8882 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 8883 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 8884 8885 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */ 8886 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8887 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8888 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ 8889 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ 8890 8891 /* Bit 9 : Enable or disable interrupt for ERROR event */ 8892 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8893 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8894 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 8895 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 8896 8897 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 8898 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8899 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8900 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 8901 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 8902 8903 /* Register: TWIM_INTENSET */ 8904 /* Description: Enable interrupt */ 8905 8906 /* Bit 24 : Write '1' to enable interrupt for LASTTX event */ 8907 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 8908 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 8909 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 8910 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 8911 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ 8912 8913 /* Bit 23 : Write '1' to enable interrupt for LASTRX event */ 8914 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 8915 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 8916 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 8917 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 8918 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ 8919 8920 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ 8921 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8922 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8923 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8924 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8925 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 8926 8927 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ 8928 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8929 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8930 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8931 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8932 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 8933 8934 /* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ 8935 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8936 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8937 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 8938 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 8939 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ 8940 8941 /* Bit 9 : Write '1' to enable interrupt for ERROR event */ 8942 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8943 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8944 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 8945 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 8946 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 8947 8948 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */ 8949 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8950 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8951 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 8952 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 8953 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 8954 8955 /* Register: TWIM_INTENCLR */ 8956 /* Description: Disable interrupt */ 8957 8958 /* Bit 24 : Write '1' to disable interrupt for LASTTX event */ 8959 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 8960 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 8961 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 8962 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 8963 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ 8964 8965 /* Bit 23 : Write '1' to disable interrupt for LASTRX event */ 8966 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 8967 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 8968 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 8969 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 8970 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ 8971 8972 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ 8973 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 8974 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 8975 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8976 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8977 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 8978 8979 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ 8980 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 8981 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 8982 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 8983 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 8984 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 8985 8986 /* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ 8987 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 8988 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 8989 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 8990 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 8991 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ 8992 8993 /* Bit 9 : Write '1' to disable interrupt for ERROR event */ 8994 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 8995 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 8996 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 8997 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 8998 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 8999 9000 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */ 9001 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9002 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9003 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9004 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9005 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 9006 9007 /* Register: TWIM_ERRORSRC */ 9008 /* Description: Error source */ 9009 9010 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 9011 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 9012 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 9013 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 9014 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 9015 9016 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 9017 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 9018 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 9019 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ 9020 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ 9021 9022 /* Bit 0 : Overrun error */ 9023 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 9024 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 9025 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ 9026 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ 9027 9028 /* Register: TWIM_ENABLE */ 9029 /* Description: Enable TWIM */ 9030 9031 /* Bits 3..0 : Enable or disable TWIM */ 9032 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9033 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9034 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ 9035 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ 9036 9037 /* Register: TWIM_PSEL_SCL */ 9038 /* Description: Pin select for SCL signal */ 9039 9040 /* Bit 31 : Connection */ 9041 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9042 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9043 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 9044 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9045 9046 /* Bits 4..0 : Pin number */ 9047 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 9048 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 9049 9050 /* Register: TWIM_PSEL_SDA */ 9051 /* Description: Pin select for SDA signal */ 9052 9053 /* Bit 31 : Connection */ 9054 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9055 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9056 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 9057 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9058 9059 /* Bits 4..0 : Pin number */ 9060 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 9061 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 9062 9063 /* Register: TWIM_FREQUENCY */ 9064 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ 9065 9066 /* Bits 31..0 : TWI master clock frequency */ 9067 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 9068 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 9069 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 9070 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 9071 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ 9072 9073 /* Register: TWIM_RXD_PTR */ 9074 /* Description: Data pointer */ 9075 9076 /* Bits 31..0 : Data pointer */ 9077 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9078 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9079 9080 /* Register: TWIM_RXD_MAXCNT */ 9081 /* Description: Maximum number of bytes in receive buffer */ 9082 9083 /* Bits 9..0 : Maximum number of bytes in receive buffer */ 9084 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9085 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9086 9087 /* Register: TWIM_RXD_AMOUNT */ 9088 /* Description: Number of bytes transferred in the last transaction */ 9089 9090 /* Bits 9..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 9091 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9092 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9093 9094 /* Register: TWIM_RXD_LIST */ 9095 /* Description: EasyDMA list type */ 9096 9097 /* Bits 2..0 : List type */ 9098 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9099 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9100 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9101 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9102 9103 /* Register: TWIM_TXD_PTR */ 9104 /* Description: Data pointer */ 9105 9106 /* Bits 31..0 : Data pointer */ 9107 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9108 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9109 9110 /* Register: TWIM_TXD_MAXCNT */ 9111 /* Description: Maximum number of bytes in transmit buffer */ 9112 9113 /* Bits 9..0 : Maximum number of bytes in transmit buffer */ 9114 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9115 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9116 9117 /* Register: TWIM_TXD_AMOUNT */ 9118 /* Description: Number of bytes transferred in the last transaction */ 9119 9120 /* Bits 9..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 9121 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9122 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9123 9124 /* Register: TWIM_TXD_LIST */ 9125 /* Description: EasyDMA list type */ 9126 9127 /* Bits 2..0 : List type */ 9128 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 9129 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 9130 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 9131 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 9132 9133 /* Register: TWIM_ADDRESS */ 9134 /* Description: Address used in the TWI transfer */ 9135 9136 /* Bits 6..0 : Address used in the TWI transfer */ 9137 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 9138 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 9139 9140 9141 /* Peripheral: TWIS */ 9142 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */ 9143 9144 /* Register: TWIS_TASKS_STOP */ 9145 /* Description: Stop TWI transaction */ 9146 9147 /* Bit 0 : */ 9148 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 9149 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 9150 9151 /* Register: TWIS_TASKS_SUSPEND */ 9152 /* Description: Suspend TWI transaction */ 9153 9154 /* Bit 0 : */ 9155 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 9156 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 9157 9158 /* Register: TWIS_TASKS_RESUME */ 9159 /* Description: Resume TWI transaction */ 9160 9161 /* Bit 0 : */ 9162 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 9163 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 9164 9165 /* Register: TWIS_TASKS_PREPARERX */ 9166 /* Description: Prepare the TWI slave to respond to a write command */ 9167 9168 /* Bit 0 : */ 9169 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ 9170 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ 9171 9172 /* Register: TWIS_TASKS_PREPARETX */ 9173 /* Description: Prepare the TWI slave to respond to a read command */ 9174 9175 /* Bit 0 : */ 9176 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ 9177 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ 9178 9179 /* Register: TWIS_EVENTS_STOPPED */ 9180 /* Description: TWI stopped */ 9181 9182 /* Bit 0 : */ 9183 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 9184 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 9185 9186 /* Register: TWIS_EVENTS_ERROR */ 9187 /* Description: TWI error */ 9188 9189 /* Bit 0 : */ 9190 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 9191 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 9192 9193 /* Register: TWIS_EVENTS_RXSTARTED */ 9194 /* Description: Receive sequence started */ 9195 9196 /* Bit 0 : */ 9197 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 9198 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 9199 9200 /* Register: TWIS_EVENTS_TXSTARTED */ 9201 /* Description: Transmit sequence started */ 9202 9203 /* Bit 0 : */ 9204 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 9205 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 9206 9207 /* Register: TWIS_EVENTS_WRITE */ 9208 /* Description: Write command received */ 9209 9210 /* Bit 0 : */ 9211 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ 9212 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ 9213 9214 /* Register: TWIS_EVENTS_READ */ 9215 /* Description: Read command received */ 9216 9217 /* Bit 0 : */ 9218 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ 9219 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ 9220 9221 /* Register: TWIS_SHORTS */ 9222 /* Description: Shortcut register */ 9223 9224 /* Bit 14 : Shortcut between READ event and SUSPEND task */ 9225 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ 9226 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ 9227 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 9228 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 9229 9230 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */ 9231 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ 9232 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ 9233 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 9234 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 9235 9236 /* Register: TWIS_INTEN */ 9237 /* Description: Enable or disable interrupt */ 9238 9239 /* Bit 26 : Enable or disable interrupt for READ event */ 9240 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ 9241 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ 9242 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ 9243 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ 9244 9245 /* Bit 25 : Enable or disable interrupt for WRITE event */ 9246 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9247 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9248 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ 9249 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ 9250 9251 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */ 9252 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9253 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9254 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 9255 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 9256 9257 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */ 9258 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9259 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9260 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 9261 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 9262 9263 /* Bit 9 : Enable or disable interrupt for ERROR event */ 9264 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9265 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9266 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 9267 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 9268 9269 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 9270 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9271 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9272 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 9273 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 9274 9275 /* Register: TWIS_INTENSET */ 9276 /* Description: Enable interrupt */ 9277 9278 /* Bit 26 : Write '1' to enable interrupt for READ event */ 9279 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ 9280 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ 9281 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ 9282 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ 9283 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ 9284 9285 /* Bit 25 : Write '1' to enable interrupt for WRITE event */ 9286 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9287 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9288 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ 9289 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ 9290 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ 9291 9292 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ 9293 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9294 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9295 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9296 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9297 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 9298 9299 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ 9300 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9301 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9302 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9303 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9304 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 9305 9306 /* Bit 9 : Write '1' to enable interrupt for ERROR event */ 9307 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9308 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9309 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9310 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9311 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9312 9313 /* Bit 1 : Write '1' to enable interrupt for STOPPED event */ 9314 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9315 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9316 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9317 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9318 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 9319 9320 /* Register: TWIS_INTENCLR */ 9321 /* Description: Disable interrupt */ 9322 9323 /* Bit 26 : Write '1' to disable interrupt for READ event */ 9324 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ 9325 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ 9326 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ 9327 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ 9328 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ 9329 9330 /* Bit 25 : Write '1' to disable interrupt for WRITE event */ 9331 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 9332 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ 9333 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ 9334 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ 9335 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ 9336 9337 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ 9338 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9339 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9340 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9341 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9342 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 9343 9344 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ 9345 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9346 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9347 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9348 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9349 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 9350 9351 /* Bit 9 : Write '1' to disable interrupt for ERROR event */ 9352 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9353 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9354 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9355 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9356 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9357 9358 /* Bit 1 : Write '1' to disable interrupt for STOPPED event */ 9359 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9360 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9361 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 9362 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 9363 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 9364 9365 /* Register: TWIS_ERRORSRC */ 9366 /* Description: Error source */ 9367 9368 /* Bit 3 : TX buffer over-read detected, and prevented */ 9369 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ 9370 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 9371 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ 9372 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ 9373 9374 /* Bit 2 : NACK sent after receiving a data byte */ 9375 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 9376 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 9377 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 9378 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 9379 9380 /* Bit 0 : RX buffer overflow detected, and prevented */ 9381 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ 9382 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 9383 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ 9384 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ 9385 9386 /* Register: TWIS_MATCH */ 9387 /* Description: Status register indicating which address had a match */ 9388 9389 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ 9390 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ 9391 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ 9392 9393 /* Register: TWIS_ENABLE */ 9394 /* Description: Enable TWIS */ 9395 9396 /* Bits 3..0 : Enable or disable TWIS */ 9397 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9398 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9399 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ 9400 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ 9401 9402 /* Register: TWIS_PSEL_SCL */ 9403 /* Description: Pin select for SCL signal */ 9404 9405 /* Bit 31 : Connection */ 9406 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9407 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9408 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 9409 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9410 9411 /* Bits 4..0 : Pin number */ 9412 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 9413 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 9414 9415 /* Register: TWIS_PSEL_SDA */ 9416 /* Description: Pin select for SDA signal */ 9417 9418 /* Bit 31 : Connection */ 9419 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9420 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9421 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 9422 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9423 9424 /* Bits 4..0 : Pin number */ 9425 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 9426 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 9427 9428 /* Register: TWIS_RXD_PTR */ 9429 /* Description: RXD Data pointer */ 9430 9431 /* Bits 31..0 : RXD Data pointer */ 9432 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9433 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9434 9435 /* Register: TWIS_RXD_MAXCNT */ 9436 /* Description: Maximum number of bytes in RXD buffer */ 9437 9438 /* Bits 9..0 : Maximum number of bytes in RXD buffer */ 9439 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9440 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9441 9442 /* Register: TWIS_RXD_AMOUNT */ 9443 /* Description: Number of bytes transferred in the last RXD transaction */ 9444 9445 /* Bits 9..0 : Number of bytes transferred in the last RXD transaction */ 9446 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9447 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9448 9449 /* Register: TWIS_TXD_PTR */ 9450 /* Description: TXD Data pointer */ 9451 9452 /* Bits 31..0 : TXD Data pointer */ 9453 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9454 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9455 9456 /* Register: TWIS_TXD_MAXCNT */ 9457 /* Description: Maximum number of bytes in TXD buffer */ 9458 9459 /* Bits 9..0 : Maximum number of bytes in TXD buffer */ 9460 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9461 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9462 9463 /* Register: TWIS_TXD_AMOUNT */ 9464 /* Description: Number of bytes transferred in the last TXD transaction */ 9465 9466 /* Bits 9..0 : Number of bytes transferred in the last TXD transaction */ 9467 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9468 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9469 9470 /* Register: TWIS_ADDRESS */ 9471 /* Description: Description collection[n]: TWI slave address n */ 9472 9473 /* Bits 6..0 : TWI slave address */ 9474 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 9475 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 9476 9477 /* Register: TWIS_CONFIG */ 9478 /* Description: Configuration register for the address match mechanism */ 9479 9480 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */ 9481 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ 9482 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ 9483 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ 9484 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ 9485 9486 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */ 9487 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ 9488 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ 9489 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ 9490 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ 9491 9492 /* Register: TWIS_ORC */ 9493 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 9494 9495 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 9496 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 9497 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 9498 9499 9500 /* Peripheral: UARTE */ 9501 /* Description: UART with EasyDMA */ 9502 9503 /* Register: UARTE_TASKS_STARTRX */ 9504 /* Description: Start UART receiver */ 9505 9506 /* Bit 0 : */ 9507 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 9508 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 9509 9510 /* Register: UARTE_TASKS_STOPRX */ 9511 /* Description: Stop UART receiver */ 9512 9513 /* Bit 0 : */ 9514 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ 9515 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ 9516 9517 /* Register: UARTE_TASKS_STARTTX */ 9518 /* Description: Start UART transmitter */ 9519 9520 /* Bit 0 : */ 9521 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 9522 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 9523 9524 /* Register: UARTE_TASKS_STOPTX */ 9525 /* Description: Stop UART transmitter */ 9526 9527 /* Bit 0 : */ 9528 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ 9529 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ 9530 9531 /* Register: UARTE_TASKS_FLUSHRX */ 9532 /* Description: Flush RX FIFO into RX buffer */ 9533 9534 /* Bit 0 : */ 9535 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ 9536 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ 9537 9538 /* Register: UARTE_EVENTS_CTS */ 9539 /* Description: CTS is activated (set low). Clear To Send. */ 9540 9541 /* Bit 0 : */ 9542 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ 9543 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ 9544 9545 /* Register: UARTE_EVENTS_NCTS */ 9546 /* Description: CTS is deactivated (set high). Not Clear To Send. */ 9547 9548 /* Bit 0 : */ 9549 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ 9550 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ 9551 9552 /* Register: UARTE_EVENTS_RXDRDY */ 9553 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ 9554 9555 /* Bit 0 : */ 9556 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ 9557 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ 9558 9559 /* Register: UARTE_EVENTS_ENDRX */ 9560 /* Description: Receive buffer is filled up */ 9561 9562 /* Bit 0 : */ 9563 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 9564 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 9565 9566 /* Register: UARTE_EVENTS_TXDRDY */ 9567 /* Description: Data sent from TXD */ 9568 9569 /* Bit 0 : */ 9570 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ 9571 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ 9572 9573 /* Register: UARTE_EVENTS_ENDTX */ 9574 /* Description: Last TX byte transmitted */ 9575 9576 /* Bit 0 : */ 9577 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 9578 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 9579 9580 /* Register: UARTE_EVENTS_ERROR */ 9581 /* Description: Error detected */ 9582 9583 /* Bit 0 : */ 9584 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 9585 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 9586 9587 /* Register: UARTE_EVENTS_RXTO */ 9588 /* Description: Receiver timeout */ 9589 9590 /* Bit 0 : */ 9591 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ 9592 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ 9593 9594 /* Register: UARTE_EVENTS_RXSTARTED */ 9595 /* Description: UART receiver has started */ 9596 9597 /* Bit 0 : */ 9598 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 9599 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 9600 9601 /* Register: UARTE_EVENTS_TXSTARTED */ 9602 /* Description: UART transmitter has started */ 9603 9604 /* Bit 0 : */ 9605 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 9606 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 9607 9608 /* Register: UARTE_EVENTS_TXSTOPPED */ 9609 /* Description: Transmitter stopped */ 9610 9611 /* Bit 0 : */ 9612 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ 9613 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ 9614 9615 /* Register: UARTE_SHORTS */ 9616 /* Description: Shortcut register */ 9617 9618 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */ 9619 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ 9620 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ 9621 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 9622 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 9623 9624 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */ 9625 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ 9626 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ 9627 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 9628 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 9629 9630 /* Register: UARTE_INTEN */ 9631 /* Description: Enable or disable interrupt */ 9632 9633 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ 9634 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 9635 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 9636 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ 9637 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ 9638 9639 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */ 9640 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9641 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9642 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 9643 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 9644 9645 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */ 9646 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9647 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9648 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 9649 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 9650 9651 /* Bit 17 : Enable or disable interrupt for RXTO event */ 9652 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9653 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9654 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ 9655 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ 9656 9657 /* Bit 9 : Enable or disable interrupt for ERROR event */ 9658 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9659 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9660 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 9661 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 9662 9663 /* Bit 8 : Enable or disable interrupt for ENDTX event */ 9664 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 9665 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 9666 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ 9667 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ 9668 9669 /* Bit 7 : Enable or disable interrupt for TXDRDY event */ 9670 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9671 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9672 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ 9673 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ 9674 9675 /* Bit 4 : Enable or disable interrupt for ENDRX event */ 9676 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 9677 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 9678 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ 9679 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ 9680 9681 /* Bit 2 : Enable or disable interrupt for RXDRDY event */ 9682 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9683 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9684 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ 9685 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ 9686 9687 /* Bit 1 : Enable or disable interrupt for NCTS event */ 9688 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9689 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9690 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ 9691 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ 9692 9693 /* Bit 0 : Enable or disable interrupt for CTS event */ 9694 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ 9695 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ 9696 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ 9697 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ 9698 9699 /* Register: UARTE_INTENSET */ 9700 /* Description: Enable interrupt */ 9701 9702 /* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ 9703 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 9704 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 9705 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 9706 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 9707 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ 9708 9709 /* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ 9710 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9711 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9712 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9713 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9714 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 9715 9716 /* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ 9717 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9718 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9719 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9720 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9721 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 9722 9723 /* Bit 17 : Write '1' to enable interrupt for RXTO event */ 9724 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9725 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9726 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 9727 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 9728 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ 9729 9730 /* Bit 9 : Write '1' to enable interrupt for ERROR event */ 9731 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9732 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9733 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9734 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9735 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ 9736 9737 /* Bit 8 : Write '1' to enable interrupt for ENDTX event */ 9738 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 9739 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 9740 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 9741 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 9742 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 9743 9744 /* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ 9745 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9746 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9747 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9748 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9749 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ 9750 9751 /* Bit 4 : Write '1' to enable interrupt for ENDRX event */ 9752 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 9753 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 9754 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 9755 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 9756 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 9757 9758 /* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ 9759 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9760 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9761 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9762 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9763 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ 9764 9765 /* Bit 1 : Write '1' to enable interrupt for NCTS event */ 9766 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9767 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9768 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 9769 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 9770 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ 9771 9772 /* Bit 0 : Write '1' to enable interrupt for CTS event */ 9773 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 9774 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 9775 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 9776 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 9777 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ 9778 9779 /* Register: UARTE_INTENCLR */ 9780 /* Description: Disable interrupt */ 9781 9782 /* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ 9783 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 9784 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 9785 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 9786 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 9787 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ 9788 9789 /* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ 9790 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 9791 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 9792 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9793 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9794 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 9795 9796 /* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ 9797 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 9798 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 9799 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 9800 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 9801 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 9802 9803 /* Bit 17 : Write '1' to disable interrupt for RXTO event */ 9804 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 9805 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 9806 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ 9807 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ 9808 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ 9809 9810 /* Bit 9 : Write '1' to disable interrupt for ERROR event */ 9811 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 9812 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 9813 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 9814 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 9815 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 9816 9817 /* Bit 8 : Write '1' to disable interrupt for ENDTX event */ 9818 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 9819 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 9820 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 9821 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 9822 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 9823 9824 /* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ 9825 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 9826 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 9827 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9828 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9829 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ 9830 9831 /* Bit 4 : Write '1' to disable interrupt for ENDRX event */ 9832 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 9833 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 9834 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 9835 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 9836 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 9837 9838 /* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ 9839 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 9840 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 9841 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 9842 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 9843 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ 9844 9845 /* Bit 1 : Write '1' to disable interrupt for NCTS event */ 9846 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 9847 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 9848 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ 9849 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ 9850 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ 9851 9852 /* Bit 0 : Write '1' to disable interrupt for CTS event */ 9853 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 9854 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 9855 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ 9856 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ 9857 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ 9858 9859 /* Register: UARTE_ERRORSRC */ 9860 /* Description: Error source Note : this register is read / write one to clear. */ 9861 9862 /* Bit 3 : Break condition */ 9863 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 9864 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 9865 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 9866 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 9867 9868 /* Bit 2 : Framing error occurred */ 9869 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 9870 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 9871 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 9872 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 9873 9874 /* Bit 1 : Parity error */ 9875 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 9876 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 9877 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 9878 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 9879 9880 /* Bit 0 : Overrun error */ 9881 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 9882 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 9883 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 9884 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 9885 9886 /* Register: UARTE_ENABLE */ 9887 /* Description: Enable UART */ 9888 9889 /* Bits 3..0 : Enable or disable UARTE */ 9890 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9891 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9892 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ 9893 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ 9894 9895 /* Register: UARTE_PSEL_RTS */ 9896 /* Description: Pin select for RTS signal */ 9897 9898 /* Bit 31 : Connection */ 9899 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9900 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9901 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 9902 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9903 9904 /* Bits 4..0 : Pin number */ 9905 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 9906 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 9907 9908 /* Register: UARTE_PSEL_TXD */ 9909 /* Description: Pin select for TXD signal */ 9910 9911 /* Bit 31 : Connection */ 9912 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9913 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9914 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 9915 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9916 9917 /* Bits 4..0 : Pin number */ 9918 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 9919 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 9920 9921 /* Register: UARTE_PSEL_CTS */ 9922 /* Description: Pin select for CTS signal */ 9923 9924 /* Bit 31 : Connection */ 9925 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9926 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9927 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 9928 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9929 9930 /* Bits 4..0 : Pin number */ 9931 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 9932 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 9933 9934 /* Register: UARTE_PSEL_RXD */ 9935 /* Description: Pin select for RXD signal */ 9936 9937 /* Bit 31 : Connection */ 9938 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9939 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9940 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 9941 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 9942 9943 /* Bits 4..0 : Pin number */ 9944 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 9945 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 9946 9947 /* Register: UARTE_BAUDRATE */ 9948 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 9949 9950 /* Bits 31..0 : Baud rate */ 9951 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 9952 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 9953 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 9954 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 9955 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 9956 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 9957 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ 9958 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 9959 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ 9960 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 9961 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ 9962 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 9963 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ 9964 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 9965 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ 9966 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ 9967 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 9968 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ 9969 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ 9970 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ 9971 9972 /* Register: UARTE_RXD_PTR */ 9973 /* Description: Data pointer */ 9974 9975 /* Bits 31..0 : Data pointer */ 9976 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9977 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9978 9979 /* Register: UARTE_RXD_MAXCNT */ 9980 /* Description: Maximum number of bytes in receive buffer */ 9981 9982 /* Bits 9..0 : Maximum number of bytes in receive buffer */ 9983 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 9984 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 9985 9986 /* Register: UARTE_RXD_AMOUNT */ 9987 /* Description: Number of bytes transferred in the last transaction */ 9988 9989 /* Bits 9..0 : Number of bytes transferred in the last transaction */ 9990 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 9991 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 9992 9993 /* Register: UARTE_TXD_PTR */ 9994 /* Description: Data pointer */ 9995 9996 /* Bits 31..0 : Data pointer */ 9997 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9998 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9999 10000 /* Register: UARTE_TXD_MAXCNT */ 10001 /* Description: Maximum number of bytes in transmit buffer */ 10002 10003 /* Bits 9..0 : Maximum number of bytes in transmit buffer */ 10004 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 10005 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 10006 10007 /* Register: UARTE_TXD_AMOUNT */ 10008 /* Description: Number of bytes transferred in the last transaction */ 10009 10010 /* Bits 9..0 : Number of bytes transferred in the last transaction */ 10011 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 10012 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 10013 10014 /* Register: UARTE_CONFIG */ 10015 /* Description: Configuration of parity and hardware flow control */ 10016 10017 /* Bit 4 : Stop bits */ 10018 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 10019 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 10020 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ 10021 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ 10022 10023 /* Bits 3..1 : Parity */ 10024 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 10025 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 10026 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 10027 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ 10028 10029 /* Bit 0 : Hardware flow control */ 10030 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 10031 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 10032 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 10033 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 10034 10035 10036 /* Peripheral: UICR */ 10037 /* Description: User information configuration registers */ 10038 10039 /* Register: UICR_NRFFW */ 10040 /* Description: Description collection[n]: Reserved for Nordic firmware design */ 10041 10042 /* Bits 31..0 : Reserved for Nordic firmware design */ 10043 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ 10044 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ 10045 10046 /* Register: UICR_NRFHW */ 10047 /* Description: Description collection[n]: Reserved for Nordic hardware design */ 10048 10049 /* Bits 31..0 : Reserved for Nordic hardware design */ 10050 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ 10051 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ 10052 10053 /* Register: UICR_CUSTOMER */ 10054 /* Description: Description collection[n]: Reserved for customer */ 10055 10056 /* Bits 31..0 : Reserved for customer */ 10057 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ 10058 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ 10059 10060 /* Register: UICR_PSELRESET */ 10061 /* Description: Description collection[n]: Mapping of the nRESET function (see POWER chapter for details) */ 10062 10063 /* Bit 31 : Connection */ 10064 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10065 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10066 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ 10067 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10068 10069 /* Bits 5..0 : GPIO number P0.n onto which reset is exposed */ 10070 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ 10071 #define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ 10072 10073 /* Register: UICR_APPROTECT */ 10074 /* Description: Access port protection */ 10075 10076 /* Bits 7..0 : Enable or disable access port protection. */ 10077 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 10078 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 10079 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ 10080 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ 10081 10082 10083 /* Peripheral: WDT */ 10084 /* Description: Watchdog Timer */ 10085 10086 /* Register: WDT_TASKS_START */ 10087 /* Description: Start the watchdog */ 10088 10089 /* Bit 0 : */ 10090 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 10091 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 10092 10093 /* Register: WDT_EVENTS_TIMEOUT */ 10094 /* Description: Watchdog timeout */ 10095 10096 /* Bit 0 : */ 10097 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ 10098 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ 10099 10100 /* Register: WDT_INTENSET */ 10101 /* Description: Enable interrupt */ 10102 10103 /* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ 10104 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 10105 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 10106 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 10107 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 10108 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ 10109 10110 /* Register: WDT_INTENCLR */ 10111 /* Description: Disable interrupt */ 10112 10113 /* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ 10114 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 10115 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 10116 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 10117 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 10118 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ 10119 10120 /* Register: WDT_RUNSTATUS */ 10121 /* Description: Run status */ 10122 10123 /* Bit 0 : Indicates whether or not the watchdog is running */ 10124 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ 10125 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ 10126 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ 10127 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ 10128 10129 /* Register: WDT_REQSTATUS */ 10130 /* Description: Request status */ 10131 10132 /* Bit 7 : Request status for RR[7] register */ 10133 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 10134 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 10135 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ 10136 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ 10137 10138 /* Bit 6 : Request status for RR[6] register */ 10139 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 10140 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 10141 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ 10142 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ 10143 10144 /* Bit 5 : Request status for RR[5] register */ 10145 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 10146 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 10147 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ 10148 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ 10149 10150 /* Bit 4 : Request status for RR[4] register */ 10151 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 10152 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 10153 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ 10154 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ 10155 10156 /* Bit 3 : Request status for RR[3] register */ 10157 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 10158 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 10159 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ 10160 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ 10161 10162 /* Bit 2 : Request status for RR[2] register */ 10163 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 10164 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 10165 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ 10166 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ 10167 10168 /* Bit 1 : Request status for RR[1] register */ 10169 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 10170 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 10171 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ 10172 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ 10173 10174 /* Bit 0 : Request status for RR[0] register */ 10175 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 10176 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 10177 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ 10178 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ 10179 10180 /* Register: WDT_CRV */ 10181 /* Description: Counter reload value */ 10182 10183 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ 10184 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ 10185 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ 10186 10187 /* Register: WDT_RREN */ 10188 /* Description: Enable register for reload request registers */ 10189 10190 /* Bit 7 : Enable or disable RR[7] register */ 10191 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 10192 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 10193 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ 10194 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ 10195 10196 /* Bit 6 : Enable or disable RR[6] register */ 10197 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 10198 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 10199 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ 10200 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ 10201 10202 /* Bit 5 : Enable or disable RR[5] register */ 10203 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 10204 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 10205 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ 10206 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ 10207 10208 /* Bit 4 : Enable or disable RR[4] register */ 10209 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 10210 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 10211 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ 10212 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ 10213 10214 /* Bit 3 : Enable or disable RR[3] register */ 10215 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 10216 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 10217 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ 10218 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ 10219 10220 /* Bit 2 : Enable or disable RR[2] register */ 10221 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 10222 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 10223 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ 10224 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ 10225 10226 /* Bit 1 : Enable or disable RR[1] register */ 10227 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 10228 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 10229 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ 10230 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ 10231 10232 /* Bit 0 : Enable or disable RR[0] register */ 10233 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 10234 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 10235 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ 10236 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ 10237 10238 /* Register: WDT_CONFIG */ 10239 /* Description: Configuration register */ 10240 10241 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ 10242 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 10243 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 10244 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ 10245 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ 10246 10247 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ 10248 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 10249 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 10250 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ 10251 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ 10252 10253 /* Register: WDT_RR */ 10254 /* Description: Description collection[n]: Reload request n */ 10255 10256 /* Bits 31..0 : Reload request register */ 10257 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 10258 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 10259 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ 10260 10261 10262 /*lint --flb "Leave library region" */ 10263 #endif 10264