1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf52810.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 03. December 2018 34 * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35 * from File 'nrf52810.svd', 36 * last modified on Monday, 03.12.2018 10:18:20 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf52810 47 * @{ 48 */ 49 50 51 #ifndef NRF52810_H 52 #define NRF52810_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83 /* ========================================== nrf52810 Specific Interrupt Numbers ========================================== */ 84 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85 RADIO_IRQn = 1, /*!< 1 RADIO */ 86 UARTE0_IRQn = 2, /*!< 2 UARTE0 */ 87 TWIM0_TWIS0_IRQn = 3, /*!< 3 TWIM0_TWIS0 */ 88 SPIM0_SPIS0_IRQn = 4, /*!< 4 SPIM0_SPIS0 */ 89 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 90 SAADC_IRQn = 7, /*!< 7 SAADC */ 91 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 92 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 93 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 94 RTC0_IRQn = 11, /*!< 11 RTC0 */ 95 TEMP_IRQn = 12, /*!< 12 TEMP */ 96 RNG_IRQn = 13, /*!< 13 RNG */ 97 ECB_IRQn = 14, /*!< 14 ECB */ 98 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 99 WDT_IRQn = 16, /*!< 16 WDT */ 100 RTC1_IRQn = 17, /*!< 17 RTC1 */ 101 QDEC_IRQn = 18, /*!< 18 QDEC */ 102 COMP_IRQn = 19, /*!< 19 COMP */ 103 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 104 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 105 SWI2_IRQn = 22, /*!< 22 SWI2 */ 106 SWI3_IRQn = 23, /*!< 23 SWI3 */ 107 SWI4_IRQn = 24, /*!< 24 SWI4 */ 108 SWI5_IRQn = 25, /*!< 25 SWI5 */ 109 PWM0_IRQn = 28, /*!< 28 PWM0 */ 110 PDM_IRQn = 29 /*!< 29 PDM */ 111 } IRQn_Type; 112 113 114 115 /* =========================================================================================================================== */ 116 /* ================ Processor and Core Peripheral Section ================ */ 117 /* =========================================================================================================================== */ 118 119 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 120 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 121 #define __DSP_PRESENT 0 /*!< DSP present or not */ 122 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 123 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 124 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 125 #define __MPU_PRESENT 1 /*!< MPU present or not */ 126 #define __FPU_PRESENT 0 /*!< FPU present or not */ 127 128 129 /** @} */ /* End of group Configuration_of_CMSIS */ 130 131 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 132 #include "system_nrf52810.h" /*!< nrf52810 System */ 133 134 #ifndef __IM /*!< Fallback for older CMSIS versions */ 135 #define __IM __I 136 #endif 137 #ifndef __OM /*!< Fallback for older CMSIS versions */ 138 #define __OM __O 139 #endif 140 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 141 #define __IOM __IO 142 #endif 143 144 145 /* ======================================== Start of section using anonymous unions ======================================== */ 146 #if defined (__CC_ARM) 147 #pragma push 148 #pragma anon_unions 149 #elif defined (__ICCARM__) 150 #pragma language=extended 151 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 152 #pragma clang diagnostic push 153 #pragma clang diagnostic ignored "-Wc11-extensions" 154 #pragma clang diagnostic ignored "-Wreserved-id-macro" 155 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 156 #pragma clang diagnostic ignored "-Wnested-anon-types" 157 #elif defined (__GNUC__) 158 /* anonymous unions are enabled by default */ 159 #elif defined (__TMS470__) 160 /* anonymous unions are enabled by default */ 161 #elif defined (__TASKING__) 162 #pragma warning 586 163 #elif defined (__CSMC__) 164 /* anonymous unions are enabled by default */ 165 #else 166 #warning Not supported compiler type 167 #endif 168 169 170 /* =========================================================================================================================== */ 171 /* ================ Device Specific Cluster Section ================ */ 172 /* =========================================================================================================================== */ 173 174 175 /** @addtogroup Device_Peripheral_clusters 176 * @{ 177 */ 178 179 180 /** 181 * @brief FICR_INFO [INFO] (Device info) 182 */ 183 typedef struct { 184 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 185 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production 186 configuration */ 187 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 188 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 189 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 190 __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ 191 } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 192 193 194 /** 195 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 196 */ 197 typedef struct { 198 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 199 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 200 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 201 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 202 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 203 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 204 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 205 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 206 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 207 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 208 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 209 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 210 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 211 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 212 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 213 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 214 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 215 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 216 217 218 /** 219 * @brief POWER_RAM [RAM] (Unspecified) 220 */ 221 typedef struct { 222 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register. 223 The RAM size will vary depending on product 224 variant, and the RAMn register will only 225 be present if the corresponding RAM AHB 226 slave is present on the device. */ 227 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set 228 register */ 229 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear 230 register */ 231 __IM uint32_t RESERVED; 232 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 233 234 235 /** 236 * @brief UARTE_PSEL [PSEL] (Unspecified) 237 */ 238 typedef struct { 239 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 240 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 241 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 242 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 243 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 244 245 246 /** 247 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 248 */ 249 typedef struct { 250 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 251 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 252 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 253 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 254 255 256 /** 257 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 258 */ 259 typedef struct { 260 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 261 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 262 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 263 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 264 265 266 /** 267 * @brief TWIM_PSEL [PSEL] (Unspecified) 268 */ 269 typedef struct { 270 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 271 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 272 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 273 274 275 /** 276 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 277 */ 278 typedef struct { 279 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 280 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 281 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 282 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 283 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 284 285 286 /** 287 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 288 */ 289 typedef struct { 290 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 291 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 292 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 293 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 294 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 295 296 297 /** 298 * @brief TWIS_PSEL [PSEL] (Unspecified) 299 */ 300 typedef struct { 301 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 302 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 303 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 304 305 306 /** 307 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 308 */ 309 typedef struct { 310 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 311 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 312 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 313 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 314 315 316 /** 317 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 318 */ 319 typedef struct { 320 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 321 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 322 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 323 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 324 325 326 /** 327 * @brief SPIM_PSEL [PSEL] (Unspecified) 328 */ 329 typedef struct { 330 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 331 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 332 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 333 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 334 335 336 /** 337 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 338 */ 339 typedef struct { 340 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 341 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 342 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 343 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 344 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 345 346 347 /** 348 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 349 */ 350 typedef struct { 351 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 352 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 353 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 354 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 355 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 356 357 358 /** 359 * @brief SPIS_PSEL [PSEL] (Unspecified) 360 */ 361 typedef struct { 362 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 363 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 364 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 365 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 366 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 367 368 369 /** 370 * @brief SPIS_RXD [RXD] (Unspecified) 371 */ 372 typedef struct { 373 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 374 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 375 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 376 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 377 378 379 /** 380 * @brief SPIS_TXD [TXD] (Unspecified) 381 */ 382 typedef struct { 383 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 384 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 385 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 386 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 387 388 389 /** 390 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 391 */ 392 typedef struct { 393 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last results is equal 394 or above CH[n].LIMIT.HIGH */ 395 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last results is equal 396 or below CH[n].LIMIT.LOW */ 397 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 398 399 400 /** 401 * @brief SAADC_CH [CH] (Unspecified) 402 */ 403 typedef struct { 404 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection 405 for CH[n] */ 406 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection 407 for CH[n] */ 408 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for 409 CH[n] */ 410 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event 411 monitoring a channel */ 412 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 413 414 415 /** 416 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 417 */ 418 typedef struct { 419 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 420 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 421 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 422 START */ 423 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 424 425 426 /** 427 * @brief QDEC_PSEL [PSEL] (Unspecified) 428 */ 429 typedef struct { 430 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 431 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 432 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 433 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 434 435 436 /** 437 * @brief PWM_SEQ [SEQ] (Unspecified) 438 */ 439 typedef struct { 440 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in 441 RAM of this sequence */ 442 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty 443 cycles) in this sequence */ 444 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional 445 PWM periods between samples loaded into 446 compare register */ 447 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the 448 sequence */ 449 __IM uint32_t RESERVED[4]; 450 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 451 452 453 /** 454 * @brief PWM_PSEL [PSEL] (Unspecified) 455 */ 456 typedef struct { 457 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select 458 for PWM channel n */ 459 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 460 461 462 /** 463 * @brief PDM_PSEL [PSEL] (Unspecified) 464 */ 465 typedef struct { 466 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 467 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 468 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 469 470 471 /** 472 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 473 */ 474 typedef struct { 475 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 476 EasyDMA */ 477 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 478 mode */ 479 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 480 481 482 /** 483 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 484 */ 485 typedef struct { 486 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group 487 n */ 488 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group 489 n */ 490 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 491 492 493 /** 494 * @brief PPI_CH [CH] (PPI Channel) 495 */ 496 typedef struct { 497 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ 498 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ 499 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 500 501 502 /** 503 * @brief PPI_FORK [FORK] (Fork) 504 */ 505 typedef struct { 506 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ 507 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 508 509 510 /** @} */ /* End of group Device_Peripheral_clusters */ 511 512 513 /* =========================================================================================================================== */ 514 /* ================ Device Specific Peripheral Section ================ */ 515 /* =========================================================================================================================== */ 516 517 518 /** @addtogroup Device_Peripheral_peripherals 519 * @{ 520 */ 521 522 523 524 /* =========================================================================================================================== */ 525 /* ================ FICR ================ */ 526 /* =========================================================================================================================== */ 527 528 529 /** 530 * @brief Factory information configuration registers (FICR) 531 */ 532 533 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 534 __IM uint32_t RESERVED[4]; 535 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 536 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 537 __IM uint32_t RESERVED1[18]; 538 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ 539 __IM uint32_t RESERVED2[6]; 540 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word 541 n */ 542 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity root, word 543 n */ 544 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 545 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ 546 __IM uint32_t RESERVED3[21]; 547 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 548 __IM uint32_t RESERVED4[185]; 549 __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 550 coefficients */ 551 } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 552 553 554 555 /* =========================================================================================================================== */ 556 /* ================ UICR ================ */ 557 /* =========================================================================================================================== */ 558 559 560 /** 561 * @brief User information configuration registers (UICR) 562 */ 563 564 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 565 __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 566 __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 567 __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 568 __IM uint32_t RESERVED; 569 __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 570 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic 571 firmware design */ 572 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic 573 hardware design */ 574 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ 575 __IM uint32_t RESERVED1[64]; 576 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET 577 function (see POWER chapter for details) */ 578 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 579 } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ 580 581 582 583 /* =========================================================================================================================== */ 584 /* ================ BPROT ================ */ 585 /* =========================================================================================================================== */ 586 587 588 /** 589 * @brief Block Protect (BPROT) 590 */ 591 592 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 593 __IM uint32_t RESERVED[384]; 594 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 595 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 596 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ 597 __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ 598 } NRF_BPROT_Type; /*!< Size = 1552 (0x610) */ 599 600 601 602 /* =========================================================================================================================== */ 603 /* ================ CLOCK ================ */ 604 /* =========================================================================================================================== */ 605 606 607 /** 608 * @brief Clock control (CLOCK) 609 */ 610 611 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 612 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 613 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 614 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 615 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 616 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 617 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 618 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 619 __IM uint32_t RESERVED[57]; 620 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 621 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 622 __IM uint32_t RESERVED1; 623 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 624 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 625 __IM uint32_t RESERVED2[124]; 626 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 627 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 628 __IM uint32_t RESERVED3[63]; 629 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 630 triggered */ 631 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 632 __IM uint32_t RESERVED4; 633 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 634 triggered */ 635 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 636 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 637 task was triggered */ 638 __IM uint32_t RESERVED5[62]; 639 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 640 __IM uint32_t RESERVED6[7]; 641 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 642 } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 643 644 645 646 /* =========================================================================================================================== */ 647 /* ================ POWER ================ */ 648 /* =========================================================================================================================== */ 649 650 651 /** 652 * @brief Power control (POWER) 653 */ 654 655 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 656 __IM uint32_t RESERVED[30]; 657 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 658 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 659 __IM uint32_t RESERVED1[34]; 660 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 661 __IM uint32_t RESERVED2[2]; 662 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 663 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 664 __IM uint32_t RESERVED3[122]; 665 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 666 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 667 __IM uint32_t RESERVED4[61]; 668 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 669 __IM uint32_t RESERVED5[63]; 670 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 671 __IM uint32_t RESERVED6[3]; 672 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 673 __IM uint32_t RESERVED7[2]; 674 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 675 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 676 __IM uint32_t RESERVED8[21]; 677 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 678 __IM uint32_t RESERVED9[225]; 679 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 680 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 681 682 683 684 /* =========================================================================================================================== */ 685 /* ================ RADIO ================ */ 686 /* =========================================================================================================================== */ 687 688 689 /** 690 * @brief 2.4 GHz Radio (RADIO) 691 */ 692 693 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 694 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 695 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 696 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 697 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 698 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 699 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 700 the receive signal strength. */ 701 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 702 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 703 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 704 __IM uint32_t RESERVED[55]; 705 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 706 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 707 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 708 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 709 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 710 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 711 packet */ 712 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 713 received packet */ 714 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 715 __IM uint32_t RESERVED1[2]; 716 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 717 __IM uint32_t RESERVED2; 718 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 719 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 720 __IM uint32_t RESERVED3[50]; 721 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 722 __IM uint32_t RESERVED4[64]; 723 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 724 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 725 __IM uint32_t RESERVED5[61]; 726 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 727 __IM uint32_t RESERVED6; 728 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 729 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 730 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 731 __IM uint32_t RESERVED7[60]; 732 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 733 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 734 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 735 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 736 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 737 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 738 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 739 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 740 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 741 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 742 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 743 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 744 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 745 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 746 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 747 __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ 748 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 749 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 750 __IM uint32_t RESERVED8; 751 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 752 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 753 __IM uint32_t RESERVED9[2]; 754 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 755 __IM uint32_t RESERVED10[39]; 756 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base 757 segment n */ 758 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix 759 n */ 760 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 761 __IM uint32_t RESERVED11[3]; 762 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 763 __IM uint32_t RESERVED12[618]; 764 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 765 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 766 767 768 769 /* =========================================================================================================================== */ 770 /* ================ UARTE0 ================ */ 771 /* =========================================================================================================================== */ 772 773 774 /** 775 * @brief UART with EasyDMA (UARTE0) 776 */ 777 778 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 779 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 780 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 781 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 782 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 783 __IM uint32_t RESERVED[7]; 784 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 785 __IM uint32_t RESERVED1[52]; 786 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 787 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 788 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 789 transferred to Data RAM) */ 790 __IM uint32_t RESERVED2; 791 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 792 __IM uint32_t RESERVED3[2]; 793 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 794 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 795 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 796 __IM uint32_t RESERVED4[7]; 797 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 798 __IM uint32_t RESERVED5; 799 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 800 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 801 __IM uint32_t RESERVED6; 802 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 803 __IM uint32_t RESERVED7[41]; 804 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 805 __IM uint32_t RESERVED8[63]; 806 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 807 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 808 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 809 __IM uint32_t RESERVED9[93]; 810 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 811 one to clear. */ 812 __IM uint32_t RESERVED10[31]; 813 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 814 __IM uint32_t RESERVED11; 815 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 816 __IM uint32_t RESERVED12[3]; 817 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 818 selected. */ 819 __IM uint32_t RESERVED13[3]; 820 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 821 __IM uint32_t RESERVED14; 822 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 823 __IM uint32_t RESERVED15[7]; 824 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 825 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 826 827 828 829 /* =========================================================================================================================== */ 830 /* ================ TWIM0 ================ */ 831 /* =========================================================================================================================== */ 832 833 834 /** 835 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) 836 */ 837 838 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 839 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 840 __IM uint32_t RESERVED; 841 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 842 __IM uint32_t RESERVED1[2]; 843 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 844 TWI master is not suspended. */ 845 __IM uint32_t RESERVED2; 846 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 847 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 848 __IM uint32_t RESERVED3[56]; 849 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 850 __IM uint32_t RESERVED4[7]; 851 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 852 __IM uint32_t RESERVED5[8]; 853 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 854 task has been issued, TWI traffic is now 855 suspended. */ 856 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 857 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 858 __IM uint32_t RESERVED6[2]; 859 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 860 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 861 byte */ 862 __IM uint32_t RESERVED7[39]; 863 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 864 __IM uint32_t RESERVED8[63]; 865 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 866 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 867 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 868 __IM uint32_t RESERVED9[110]; 869 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 870 __IM uint32_t RESERVED10[14]; 871 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 872 __IM uint32_t RESERVED11; 873 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 874 __IM uint32_t RESERVED12[5]; 875 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 876 source selected. */ 877 __IM uint32_t RESERVED13[3]; 878 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 879 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 880 __IM uint32_t RESERVED14[13]; 881 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 882 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 883 884 885 886 /* =========================================================================================================================== */ 887 /* ================ TWIS0 ================ */ 888 /* =========================================================================================================================== */ 889 890 891 /** 892 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) 893 */ 894 895 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 896 __IM uint32_t RESERVED[5]; 897 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 898 __IM uint32_t RESERVED1; 899 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 900 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 901 __IM uint32_t RESERVED2[3]; 902 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 903 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 904 __IM uint32_t RESERVED3[51]; 905 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 906 __IM uint32_t RESERVED4[7]; 907 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 908 __IM uint32_t RESERVED5[9]; 909 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 910 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 911 __IM uint32_t RESERVED6[4]; 912 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 913 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 914 __IM uint32_t RESERVED7[37]; 915 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 916 __IM uint32_t RESERVED8[63]; 917 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 918 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 919 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 920 __IM uint32_t RESERVED9[113]; 921 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 922 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 923 a match */ 924 __IM uint32_t RESERVED10[10]; 925 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 926 __IM uint32_t RESERVED11; 927 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 928 __IM uint32_t RESERVED12[9]; 929 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 930 __IM uint32_t RESERVED13; 931 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 932 __IM uint32_t RESERVED14[14]; 933 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address 934 n */ 935 __IM uint32_t RESERVED15; 936 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 937 mechanism */ 938 __IM uint32_t RESERVED16[10]; 939 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 940 of an over-read of the transmit buffer. */ 941 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 942 943 944 945 /* =========================================================================================================================== */ 946 /* ================ SPIM0 ================ */ 947 /* =========================================================================================================================== */ 948 949 950 /** 951 * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0) 952 */ 953 954 typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */ 955 __IM uint32_t RESERVED[4]; 956 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 957 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 958 __IM uint32_t RESERVED1; 959 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 960 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 961 __IM uint32_t RESERVED2[56]; 962 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 963 __IM uint32_t RESERVED3[2]; 964 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 965 __IM uint32_t RESERVED4; 966 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 967 __IM uint32_t RESERVED5; 968 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 969 __IM uint32_t RESERVED6[10]; 970 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 971 __IM uint32_t RESERVED7[44]; 972 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 973 __IM uint32_t RESERVED8[64]; 974 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 975 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 976 __IM uint32_t RESERVED9[125]; 977 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 978 __IM uint32_t RESERVED10; 979 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 980 __IM uint32_t RESERVED11[4]; 981 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 982 source selected. */ 983 __IM uint32_t RESERVED12[3]; 984 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 985 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 986 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 987 __IM uint32_t RESERVED13[26]; 988 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 989 case and over-read of the TXD buffer. */ 990 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 991 992 993 994 /* =========================================================================================================================== */ 995 /* ================ SPIS0 ================ */ 996 /* =========================================================================================================================== */ 997 998 999 /** 1000 * @brief SPI Slave (SPIS0) 1001 */ 1002 1003 typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */ 1004 __IM uint32_t RESERVED[9]; 1005 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1006 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1007 to acquire it */ 1008 __IM uint32_t RESERVED1[54]; 1009 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1010 __IM uint32_t RESERVED2[2]; 1011 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1012 __IM uint32_t RESERVED3[5]; 1013 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1014 __IM uint32_t RESERVED4[53]; 1015 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1016 __IM uint32_t RESERVED5[64]; 1017 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1018 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1019 __IM uint32_t RESERVED6[61]; 1020 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1021 __IM uint32_t RESERVED7[15]; 1022 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1023 __IM uint32_t RESERVED8[47]; 1024 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1025 __IM uint32_t RESERVED9; 1026 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1027 __IM uint32_t RESERVED10[7]; 1028 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1029 __IM uint32_t RESERVED11; 1030 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1031 __IM uint32_t RESERVED12; 1032 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1033 __IM uint32_t RESERVED13; 1034 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1035 of an ignored transaction. */ 1036 __IM uint32_t RESERVED14[24]; 1037 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1038 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1039 1040 1041 1042 /* =========================================================================================================================== */ 1043 /* ================ GPIOTE ================ */ 1044 /* =========================================================================================================================== */ 1045 1046 1047 /** 1048 * @brief GPIO Tasks and Events (GPIOTE) 1049 */ 1050 1051 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1052 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to 1053 pin specified in CONFIG[n].PSEL. Action 1054 on pin is configured in CONFIG[n].POLARITY. */ 1055 __IM uint32_t RESERVED[4]; 1056 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to 1057 pin specified in CONFIG[n].PSEL. Action 1058 on pin is to set it high. */ 1059 __IM uint32_t RESERVED1[4]; 1060 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to 1061 pin specified in CONFIG[n].PSEL. Action 1062 on pin is to set it low. */ 1063 __IM uint32_t RESERVED2[32]; 1064 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from 1065 pin specified in CONFIG[n].PSEL */ 1066 __IM uint32_t RESERVED3[23]; 1067 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1068 with SENSE mechanism enabled */ 1069 __IM uint32_t RESERVED4[97]; 1070 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1071 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1072 __IM uint32_t RESERVED5[129]; 1073 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for 1074 OUT[n], SET[n] and CLR[n] tasks and IN[n] 1075 event */ 1076 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1077 1078 1079 1080 /* =========================================================================================================================== */ 1081 /* ================ SAADC ================ */ 1082 /* =========================================================================================================================== */ 1083 1084 1085 /** 1086 * @brief Analog to Digital Converter (SAADC) 1087 */ 1088 1089 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1090 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1091 RAM */ 1092 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1093 are sampled */ 1094 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1095 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1096 __IM uint32_t RESERVED[60]; 1097 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1098 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1099 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1100 on the mode, multiple conversions might 1101 be needed for a result to be transferred 1102 to RAM. */ 1103 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1104 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1105 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1106 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1107 __IM uint32_t RESERVED1[106]; 1108 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1109 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1110 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1111 __IM uint32_t RESERVED2[61]; 1112 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1113 __IM uint32_t RESERVED3[63]; 1114 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1115 __IM uint32_t RESERVED4[3]; 1116 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1117 __IM uint32_t RESERVED5[24]; 1118 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1119 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1120 not be combined with SCAN. The RESOLUTION 1121 is applied before averaging, thus for high 1122 OVERSAMPLE a higher RESOLUTION should be 1123 used. */ 1124 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1125 __IM uint32_t RESERVED6[12]; 1126 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1127 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1128 1129 1130 1131 /* =========================================================================================================================== */ 1132 /* ================ TIMER0 ================ */ 1133 /* =========================================================================================================================== */ 1134 1135 1136 /** 1137 * @brief Timer/Counter 0 (TIMER0) 1138 */ 1139 1140 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1141 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1142 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1143 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1144 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1145 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1146 __IM uint32_t RESERVED[11]; 1147 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value 1148 to CC[n] register */ 1149 __IM uint32_t RESERVED1[58]; 1150 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1151 match */ 1152 __IM uint32_t RESERVED2[42]; 1153 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1154 __IM uint32_t RESERVED3[64]; 1155 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1156 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1157 __IM uint32_t RESERVED4[126]; 1158 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1159 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1160 __IM uint32_t RESERVED5; 1161 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1162 __IM uint32_t RESERVED6[11]; 1163 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register 1164 n */ 1165 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1166 1167 1168 1169 /* =========================================================================================================================== */ 1170 /* ================ RTC0 ================ */ 1171 /* =========================================================================================================================== */ 1172 1173 1174 /** 1175 * @brief Real time counter 0 (RTC0) 1176 */ 1177 1178 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1179 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1180 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1181 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1182 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1183 __IM uint32_t RESERVED[60]; 1184 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1185 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1186 __IM uint32_t RESERVED1[14]; 1187 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1188 match */ 1189 __IM uint32_t RESERVED2[109]; 1190 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1191 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1192 __IM uint32_t RESERVED3[13]; 1193 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1194 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1195 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1196 __IM uint32_t RESERVED4[110]; 1197 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1198 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1199 t be written when RTC is stopped */ 1200 __IM uint32_t RESERVED5[13]; 1201 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ 1202 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1203 1204 1205 1206 /* =========================================================================================================================== */ 1207 /* ================ TEMP ================ */ 1208 /* =========================================================================================================================== */ 1209 1210 1211 /** 1212 * @brief Temperature Sensor (TEMP) 1213 */ 1214 1215 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1216 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1217 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1218 __IM uint32_t RESERVED[62]; 1219 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1220 __IM uint32_t RESERVED1[128]; 1221 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1222 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1223 __IM uint32_t RESERVED2[127]; 1224 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1225 __IM uint32_t RESERVED3[5]; 1226 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1227 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1228 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1229 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1230 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1231 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1232 __IM uint32_t RESERVED4[2]; 1233 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1234 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1235 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1236 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1237 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1238 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1239 __IM uint32_t RESERVED5[2]; 1240 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1241 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1242 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1243 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1244 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1245 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1246 1247 1248 1249 /* =========================================================================================================================== */ 1250 /* ================ RNG ================ */ 1251 /* =========================================================================================================================== */ 1252 1253 1254 /** 1255 * @brief Random Number Generator (RNG) 1256 */ 1257 1258 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1259 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1260 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1261 __IM uint32_t RESERVED[62]; 1262 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1263 written to the VALUE register */ 1264 __IM uint32_t RESERVED1[63]; 1265 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1266 __IM uint32_t RESERVED2[64]; 1267 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1268 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1269 __IM uint32_t RESERVED3[126]; 1270 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1271 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1272 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1273 1274 1275 1276 /* =========================================================================================================================== */ 1277 /* ================ ECB ================ */ 1278 /* =========================================================================================================================== */ 1279 1280 1281 /** 1282 * @brief AES ECB Mode Encryption (ECB) 1283 */ 1284 1285 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1286 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1287 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1288 __IM uint32_t RESERVED[62]; 1289 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1290 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1291 task or due to an error */ 1292 __IM uint32_t RESERVED1[127]; 1293 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1294 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1295 __IM uint32_t RESERVED2[126]; 1296 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1297 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1298 1299 1300 1301 /* =========================================================================================================================== */ 1302 /* ================ AAR ================ */ 1303 /* =========================================================================================================================== */ 1304 1305 1306 /** 1307 * @brief Accelerated Address Resolver (AAR) 1308 */ 1309 1310 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1311 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1312 in the IRK data structure */ 1313 __IM uint32_t RESERVED; 1314 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1315 __IM uint32_t RESERVED1[61]; 1316 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1317 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1318 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1319 __IM uint32_t RESERVED2[126]; 1320 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1321 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1322 __IM uint32_t RESERVED3[61]; 1323 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1324 __IM uint32_t RESERVED4[63]; 1325 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1326 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1327 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1328 __IM uint32_t RESERVED5; 1329 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1330 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1331 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1332 1333 1334 1335 /* =========================================================================================================================== */ 1336 /* ================ CCM ================ */ 1337 /* =========================================================================================================================== */ 1338 1339 1340 /** 1341 * @brief AES CCM Mode Encryption (CCM) 1342 */ 1343 1344 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1345 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1346 will stop by itself when completed. */ 1347 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1348 stop by itself when completed. */ 1349 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1350 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1351 the contents of the RATEOVERRIDE register 1352 for any ongoing encryption/decryption */ 1353 __IM uint32_t RESERVED[60]; 1354 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1355 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1356 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1357 __IM uint32_t RESERVED1[61]; 1358 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1359 __IM uint32_t RESERVED2[64]; 1360 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1361 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1362 __IM uint32_t RESERVED3[61]; 1363 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1364 __IM uint32_t RESERVED4[63]; 1365 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1366 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1367 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1368 NONCE vector */ 1369 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1370 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1371 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1372 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH 1373 = Extended. */ 1374 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1375 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 1376 1377 1378 1379 /* =========================================================================================================================== */ 1380 /* ================ WDT ================ */ 1381 /* =========================================================================================================================== */ 1382 1383 1384 /** 1385 * @brief Watchdog Timer (WDT) 1386 */ 1387 1388 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1389 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1390 __IM uint32_t RESERVED[63]; 1391 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1392 __IM uint32_t RESERVED1[128]; 1393 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1394 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1395 __IM uint32_t RESERVED2[61]; 1396 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1397 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1398 __IM uint32_t RESERVED3[63]; 1399 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1400 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1401 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1402 __IM uint32_t RESERVED4[60]; 1403 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ 1404 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1405 1406 1407 1408 /* =========================================================================================================================== */ 1409 /* ================ QDEC ================ */ 1410 /* =========================================================================================================================== */ 1411 1412 1413 /** 1414 * @brief Quadrature Decoder (QDEC) 1415 */ 1416 1417 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1418 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1419 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1420 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1421 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1422 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1423 __IM uint32_t RESERVED[59]; 1424 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1425 written to the SAMPLE register */ 1426 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1427 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1428 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1429 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1430 __IM uint32_t RESERVED1[59]; 1431 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1432 __IM uint32_t RESERVED2[64]; 1433 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1434 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1435 __IM uint32_t RESERVED3[125]; 1436 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1437 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1438 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1439 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1440 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1441 and DBLRDY events can be generated */ 1442 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1443 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1444 READCLRACC or RDCLRACC task */ 1445 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1446 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1447 __IM uint32_t RESERVED4[5]; 1448 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1449 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1450 double transitions */ 1451 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1452 or RDCLRDBL task */ 1453 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1454 1455 1456 1457 /* =========================================================================================================================== */ 1458 /* ================ COMP ================ */ 1459 /* =========================================================================================================================== */ 1460 1461 1462 /** 1463 * @brief Comparator (COMP) 1464 */ 1465 1466 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1467 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1468 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1469 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1470 __IM uint32_t RESERVED[61]; 1471 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1472 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1473 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1474 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1475 __IM uint32_t RESERVED1[60]; 1476 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1477 __IM uint32_t RESERVED2[63]; 1478 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1479 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1480 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1481 __IM uint32_t RESERVED3[61]; 1482 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1483 __IM uint32_t RESERVED4[63]; 1484 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1485 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1486 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1487 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1488 __IM uint32_t RESERVED5[8]; 1489 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1490 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1491 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1492 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 1493 1494 1495 1496 /* =========================================================================================================================== */ 1497 /* ================ EGU0 ================ */ 1498 /* =========================================================================================================================== */ 1499 1500 1501 /** 1502 * @brief Event Generator Unit 0 (EGU0) 1503 */ 1504 1505 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1506 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering 1507 the corresponding TRIGGERED[n] event */ 1508 __IM uint32_t RESERVED[48]; 1509 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated 1510 by triggering the corresponding TRIGGER[n] 1511 task */ 1512 __IM uint32_t RESERVED1[112]; 1513 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1514 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1515 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1516 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1517 1518 1519 1520 /* =========================================================================================================================== */ 1521 /* ================ SWI0 ================ */ 1522 /* =========================================================================================================================== */ 1523 1524 1525 /** 1526 * @brief Software interrupt 0 (SWI0) 1527 */ 1528 1529 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1530 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1531 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1532 1533 1534 1535 /* =========================================================================================================================== */ 1536 /* ================ PWM0 ================ */ 1537 /* =========================================================================================================================== */ 1538 1539 1540 /** 1541 * @brief Pulse width modulation unit (PWM0) 1542 */ 1543 1544 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1545 __IM uint32_t RESERVED; 1546 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1547 the end of current PWM period, and stops 1548 sequence playback */ 1549 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM 1550 value on all enabled channels from sequence 1551 n, and starts playing that sequence at the 1552 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1553 Causes PWM generation to start if not running. */ 1554 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1555 all enabled channels if DECODER.MODE=NextStep. 1556 Does not cause PWM generation to start if 1557 not running. */ 1558 __IM uint32_t RESERVED1[60]; 1559 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1560 are no longer generated */ 1561 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started 1562 on sequence n */ 1563 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of 1564 every sequence n, when last value from RAM 1565 has been applied to wave counter */ 1566 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1567 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1568 of times defined in LOOP.CNT */ 1569 __IM uint32_t RESERVED2[56]; 1570 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1571 __IM uint32_t RESERVED3[63]; 1572 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1573 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1574 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1575 __IM uint32_t RESERVED4[125]; 1576 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1577 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1578 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1579 counts */ 1580 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1581 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1582 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1583 __IM uint32_t RESERVED5[2]; 1584 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1585 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1586 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1587 1588 1589 1590 /* =========================================================================================================================== */ 1591 /* ================ PDM ================ */ 1592 /* =========================================================================================================================== */ 1593 1594 1595 /** 1596 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 1597 */ 1598 1599 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 1600 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1601 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1602 __IM uint32_t RESERVED[62]; 1603 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1604 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1605 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1606 by SAMPLE.MAXCNT (or the last sample after 1607 a STOP task has been received) to Data RAM */ 1608 __IM uint32_t RESERVED1[125]; 1609 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1610 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1611 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1612 __IM uint32_t RESERVED2[125]; 1613 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1614 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1615 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1616 signals */ 1617 __IM uint32_t RESERVED3[3]; 1618 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1619 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1620 __IM uint32_t RESERVED4[8]; 1621 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1622 __IM uint32_t RESERVED5[6]; 1623 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1624 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1625 1626 1627 1628 /* =========================================================================================================================== */ 1629 /* ================ NVMC ================ */ 1630 /* =========================================================================================================================== */ 1631 1632 1633 /** 1634 * @brief Non-volatile memory controller (NVMC) 1635 */ 1636 1637 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1638 __IM uint32_t RESERVED[256]; 1639 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1640 __IM uint32_t RESERVED1[64]; 1641 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1642 1643 union { 1644 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1645 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1646 page in code area. Equivalent to ERASEPAGE. */ 1647 }; 1648 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1649 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1650 page in code area. Equivalent to ERASEPAGE. */ 1651 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1652 registers */ 1653 __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1654 area */ 1655 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1656 } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1657 1658 1659 1660 /* =========================================================================================================================== */ 1661 /* ================ PPI ================ */ 1662 /* =========================================================================================================================== */ 1663 1664 1665 /** 1666 * @brief Programmable Peripheral Interconnect (PPI) 1667 */ 1668 1669 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1670 __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1671 __IM uint32_t RESERVED[308]; 1672 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1673 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1674 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1675 __IM uint32_t RESERVED1; 1676 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 1677 __IM uint32_t RESERVED2[148]; 1678 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ 1679 __IM uint32_t RESERVED3[62]; 1680 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1681 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1682 1683 1684 1685 /* =========================================================================================================================== */ 1686 /* ================ P0 ================ */ 1687 /* =========================================================================================================================== */ 1688 1689 1690 /** 1691 * @brief GPIO Port (P0) 1692 */ 1693 1694 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 1695 __IM uint32_t RESERVED[321]; 1696 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 1697 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 1698 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 1699 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 1700 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 1701 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 1702 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 1703 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 1704 have met the criteria set in the PIN_CNF[n].SENSE 1705 registers */ 1706 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 1707 and LDETECT mode */ 1708 __IM uint32_t RESERVED1[118]; 1709 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO 1710 pins */ 1711 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1712 1713 1714 /** @} */ /* End of group Device_Peripheral_peripherals */ 1715 1716 1717 /* =========================================================================================================================== */ 1718 /* ================ Device Specific Peripheral Address Map ================ */ 1719 /* =========================================================================================================================== */ 1720 1721 1722 /** @addtogroup Device_Peripheral_peripheralAddr 1723 * @{ 1724 */ 1725 1726 #define NRF_FICR_BASE 0x10000000UL 1727 #define NRF_UICR_BASE 0x10001000UL 1728 #define NRF_BPROT_BASE 0x40000000UL 1729 #define NRF_CLOCK_BASE 0x40000000UL 1730 #define NRF_POWER_BASE 0x40000000UL 1731 #define NRF_RADIO_BASE 0x40001000UL 1732 #define NRF_UARTE0_BASE 0x40002000UL 1733 #define NRF_TWIM0_BASE 0x40003000UL 1734 #define NRF_TWIS0_BASE 0x40003000UL 1735 #define NRF_SPIM0_BASE 0x40004000UL 1736 #define NRF_SPIS0_BASE 0x40004000UL 1737 #define NRF_GPIOTE_BASE 0x40006000UL 1738 #define NRF_SAADC_BASE 0x40007000UL 1739 #define NRF_TIMER0_BASE 0x40008000UL 1740 #define NRF_TIMER1_BASE 0x40009000UL 1741 #define NRF_TIMER2_BASE 0x4000A000UL 1742 #define NRF_RTC0_BASE 0x4000B000UL 1743 #define NRF_TEMP_BASE 0x4000C000UL 1744 #define NRF_RNG_BASE 0x4000D000UL 1745 #define NRF_ECB_BASE 0x4000E000UL 1746 #define NRF_AAR_BASE 0x4000F000UL 1747 #define NRF_CCM_BASE 0x4000F000UL 1748 #define NRF_WDT_BASE 0x40010000UL 1749 #define NRF_RTC1_BASE 0x40011000UL 1750 #define NRF_QDEC_BASE 0x40012000UL 1751 #define NRF_COMP_BASE 0x40013000UL 1752 #define NRF_EGU0_BASE 0x40014000UL 1753 #define NRF_SWI0_BASE 0x40014000UL 1754 #define NRF_EGU1_BASE 0x40015000UL 1755 #define NRF_SWI1_BASE 0x40015000UL 1756 #define NRF_SWI2_BASE 0x40016000UL 1757 #define NRF_SWI3_BASE 0x40017000UL 1758 #define NRF_SWI4_BASE 0x40018000UL 1759 #define NRF_SWI5_BASE 0x40019000UL 1760 #define NRF_PWM0_BASE 0x4001C000UL 1761 #define NRF_PDM_BASE 0x4001D000UL 1762 #define NRF_NVMC_BASE 0x4001E000UL 1763 #define NRF_PPI_BASE 0x4001F000UL 1764 #define NRF_P0_BASE 0x50000000UL 1765 1766 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1767 1768 1769 /* =========================================================================================================================== */ 1770 /* ================ Peripheral declaration ================ */ 1771 /* =========================================================================================================================== */ 1772 1773 1774 /** @addtogroup Device_Peripheral_declaration 1775 * @{ 1776 */ 1777 1778 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1779 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1780 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 1781 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1782 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1783 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1784 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 1785 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 1786 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 1787 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 1788 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 1789 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1790 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 1791 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1792 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1793 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1794 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1795 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1796 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1797 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1798 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1799 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1800 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1801 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1802 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1803 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 1804 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 1805 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 1806 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 1807 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 1808 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 1809 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 1810 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 1811 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 1812 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 1813 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 1814 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1815 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1816 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 1817 1818 /** @} */ /* End of group Device_Peripheral_declaration */ 1819 1820 1821 /* ========================================= End of section using anonymous unions ========================================= */ 1822 #if defined (__CC_ARM) 1823 #pragma pop 1824 #elif defined (__ICCARM__) 1825 /* leave anonymous unions enabled */ 1826 #elif (__ARMCC_VERSION >= 6010050) 1827 #pragma clang diagnostic pop 1828 #elif defined (__GNUC__) 1829 /* anonymous unions are enabled by default */ 1830 #elif defined (__TMS470__) 1831 /* anonymous unions are enabled by default */ 1832 #elif defined (__TASKING__) 1833 #pragma warning restore 1834 #elif defined (__CSMC__) 1835 /* anonymous unions are enabled by default */ 1836 #endif 1837 1838 1839 #ifdef __cplusplus 1840 } 1841 #endif 1842 1843 #endif /* NRF52810_H */ 1844 1845 1846 /** @} */ /* End of group nrf52810 */ 1847 1848 /** @} */ /* End of group Nordic Semiconductor */ 1849