1*150812a8SEvalZero /* 2*150812a8SEvalZero * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3*150812a8SEvalZero * 4*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without 5*150812a8SEvalZero * modification, are permitted provided that the following conditions are met: 6*150812a8SEvalZero * 7*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this 8*150812a8SEvalZero * list of conditions and the following disclaimer. 9*150812a8SEvalZero * 10*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright 11*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the 12*150812a8SEvalZero * documentation and/or other materials provided with the distribution. 13*150812a8SEvalZero * 14*150812a8SEvalZero * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this 16*150812a8SEvalZero * software without specific prior written permission. 17*150812a8SEvalZero * 18*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE. 29*150812a8SEvalZero * 30*150812a8SEvalZero * @file nrf52810.h 31*150812a8SEvalZero * @brief CMSIS HeaderFile 32*150812a8SEvalZero * @version 1 33*150812a8SEvalZero * @date 03. December 2018 34*150812a8SEvalZero * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35*150812a8SEvalZero * from File 'nrf52810.svd', 36*150812a8SEvalZero * last modified on Monday, 03.12.2018 10:18:20 37*150812a8SEvalZero */ 38*150812a8SEvalZero 39*150812a8SEvalZero 40*150812a8SEvalZero 41*150812a8SEvalZero /** @addtogroup Nordic Semiconductor 42*150812a8SEvalZero * @{ 43*150812a8SEvalZero */ 44*150812a8SEvalZero 45*150812a8SEvalZero 46*150812a8SEvalZero /** @addtogroup nrf52810 47*150812a8SEvalZero * @{ 48*150812a8SEvalZero */ 49*150812a8SEvalZero 50*150812a8SEvalZero 51*150812a8SEvalZero #ifndef NRF52810_H 52*150812a8SEvalZero #define NRF52810_H 53*150812a8SEvalZero 54*150812a8SEvalZero #ifdef __cplusplus 55*150812a8SEvalZero extern "C" { 56*150812a8SEvalZero #endif 57*150812a8SEvalZero 58*150812a8SEvalZero 59*150812a8SEvalZero /** @addtogroup Configuration_of_CMSIS 60*150812a8SEvalZero * @{ 61*150812a8SEvalZero */ 62*150812a8SEvalZero 63*150812a8SEvalZero 64*150812a8SEvalZero 65*150812a8SEvalZero /* =========================================================================================================================== */ 66*150812a8SEvalZero /* ================ Interrupt Number Definition ================ */ 67*150812a8SEvalZero /* =========================================================================================================================== */ 68*150812a8SEvalZero 69*150812a8SEvalZero typedef enum { 70*150812a8SEvalZero /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71*150812a8SEvalZero Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72*150812a8SEvalZero NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73*150812a8SEvalZero HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74*150812a8SEvalZero MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75*150812a8SEvalZero and No Match */ 76*150812a8SEvalZero BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77*150812a8SEvalZero related Fault */ 78*150812a8SEvalZero UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79*150812a8SEvalZero SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80*150812a8SEvalZero DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81*150812a8SEvalZero PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82*150812a8SEvalZero SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83*150812a8SEvalZero /* ========================================== nrf52810 Specific Interrupt Numbers ========================================== */ 84*150812a8SEvalZero POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85*150812a8SEvalZero RADIO_IRQn = 1, /*!< 1 RADIO */ 86*150812a8SEvalZero UARTE0_IRQn = 2, /*!< 2 UARTE0 */ 87*150812a8SEvalZero TWIM0_TWIS0_IRQn = 3, /*!< 3 TWIM0_TWIS0 */ 88*150812a8SEvalZero SPIM0_SPIS0_IRQn = 4, /*!< 4 SPIM0_SPIS0 */ 89*150812a8SEvalZero GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 90*150812a8SEvalZero SAADC_IRQn = 7, /*!< 7 SAADC */ 91*150812a8SEvalZero TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 92*150812a8SEvalZero TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 93*150812a8SEvalZero TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 94*150812a8SEvalZero RTC0_IRQn = 11, /*!< 11 RTC0 */ 95*150812a8SEvalZero TEMP_IRQn = 12, /*!< 12 TEMP */ 96*150812a8SEvalZero RNG_IRQn = 13, /*!< 13 RNG */ 97*150812a8SEvalZero ECB_IRQn = 14, /*!< 14 ECB */ 98*150812a8SEvalZero CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 99*150812a8SEvalZero WDT_IRQn = 16, /*!< 16 WDT */ 100*150812a8SEvalZero RTC1_IRQn = 17, /*!< 17 RTC1 */ 101*150812a8SEvalZero QDEC_IRQn = 18, /*!< 18 QDEC */ 102*150812a8SEvalZero COMP_IRQn = 19, /*!< 19 COMP */ 103*150812a8SEvalZero SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 104*150812a8SEvalZero SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 105*150812a8SEvalZero SWI2_IRQn = 22, /*!< 22 SWI2 */ 106*150812a8SEvalZero SWI3_IRQn = 23, /*!< 23 SWI3 */ 107*150812a8SEvalZero SWI4_IRQn = 24, /*!< 24 SWI4 */ 108*150812a8SEvalZero SWI5_IRQn = 25, /*!< 25 SWI5 */ 109*150812a8SEvalZero PWM0_IRQn = 28, /*!< 28 PWM0 */ 110*150812a8SEvalZero PDM_IRQn = 29 /*!< 29 PDM */ 111*150812a8SEvalZero } IRQn_Type; 112*150812a8SEvalZero 113*150812a8SEvalZero 114*150812a8SEvalZero 115*150812a8SEvalZero /* =========================================================================================================================== */ 116*150812a8SEvalZero /* ================ Processor and Core Peripheral Section ================ */ 117*150812a8SEvalZero /* =========================================================================================================================== */ 118*150812a8SEvalZero 119*150812a8SEvalZero /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 120*150812a8SEvalZero #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 121*150812a8SEvalZero #define __DSP_PRESENT 0 /*!< DSP present or not */ 122*150812a8SEvalZero #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 123*150812a8SEvalZero #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 124*150812a8SEvalZero #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 125*150812a8SEvalZero #define __MPU_PRESENT 1 /*!< MPU present or not */ 126*150812a8SEvalZero #define __FPU_PRESENT 0 /*!< FPU present or not */ 127*150812a8SEvalZero 128*150812a8SEvalZero 129*150812a8SEvalZero /** @} */ /* End of group Configuration_of_CMSIS */ 130*150812a8SEvalZero 131*150812a8SEvalZero #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 132*150812a8SEvalZero #include "system_nrf52810.h" /*!< nrf52810 System */ 133*150812a8SEvalZero 134*150812a8SEvalZero #ifndef __IM /*!< Fallback for older CMSIS versions */ 135*150812a8SEvalZero #define __IM __I 136*150812a8SEvalZero #endif 137*150812a8SEvalZero #ifndef __OM /*!< Fallback for older CMSIS versions */ 138*150812a8SEvalZero #define __OM __O 139*150812a8SEvalZero #endif 140*150812a8SEvalZero #ifndef __IOM /*!< Fallback for older CMSIS versions */ 141*150812a8SEvalZero #define __IOM __IO 142*150812a8SEvalZero #endif 143*150812a8SEvalZero 144*150812a8SEvalZero 145*150812a8SEvalZero /* ======================================== Start of section using anonymous unions ======================================== */ 146*150812a8SEvalZero #if defined (__CC_ARM) 147*150812a8SEvalZero #pragma push 148*150812a8SEvalZero #pragma anon_unions 149*150812a8SEvalZero #elif defined (__ICCARM__) 150*150812a8SEvalZero #pragma language=extended 151*150812a8SEvalZero #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 152*150812a8SEvalZero #pragma clang diagnostic push 153*150812a8SEvalZero #pragma clang diagnostic ignored "-Wc11-extensions" 154*150812a8SEvalZero #pragma clang diagnostic ignored "-Wreserved-id-macro" 155*150812a8SEvalZero #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 156*150812a8SEvalZero #pragma clang diagnostic ignored "-Wnested-anon-types" 157*150812a8SEvalZero #elif defined (__GNUC__) 158*150812a8SEvalZero /* anonymous unions are enabled by default */ 159*150812a8SEvalZero #elif defined (__TMS470__) 160*150812a8SEvalZero /* anonymous unions are enabled by default */ 161*150812a8SEvalZero #elif defined (__TASKING__) 162*150812a8SEvalZero #pragma warning 586 163*150812a8SEvalZero #elif defined (__CSMC__) 164*150812a8SEvalZero /* anonymous unions are enabled by default */ 165*150812a8SEvalZero #else 166*150812a8SEvalZero #warning Not supported compiler type 167*150812a8SEvalZero #endif 168*150812a8SEvalZero 169*150812a8SEvalZero 170*150812a8SEvalZero /* =========================================================================================================================== */ 171*150812a8SEvalZero /* ================ Device Specific Cluster Section ================ */ 172*150812a8SEvalZero /* =========================================================================================================================== */ 173*150812a8SEvalZero 174*150812a8SEvalZero 175*150812a8SEvalZero /** @addtogroup Device_Peripheral_clusters 176*150812a8SEvalZero * @{ 177*150812a8SEvalZero */ 178*150812a8SEvalZero 179*150812a8SEvalZero 180*150812a8SEvalZero /** 181*150812a8SEvalZero * @brief FICR_INFO [INFO] (Device info) 182*150812a8SEvalZero */ 183*150812a8SEvalZero typedef struct { 184*150812a8SEvalZero __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 185*150812a8SEvalZero __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production 186*150812a8SEvalZero configuration */ 187*150812a8SEvalZero __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 188*150812a8SEvalZero __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 189*150812a8SEvalZero __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 190*150812a8SEvalZero __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ 191*150812a8SEvalZero } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 192*150812a8SEvalZero 193*150812a8SEvalZero 194*150812a8SEvalZero /** 195*150812a8SEvalZero * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 196*150812a8SEvalZero */ 197*150812a8SEvalZero typedef struct { 198*150812a8SEvalZero __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 199*150812a8SEvalZero __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 200*150812a8SEvalZero __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 201*150812a8SEvalZero __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 202*150812a8SEvalZero __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 203*150812a8SEvalZero __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 204*150812a8SEvalZero __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 205*150812a8SEvalZero __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 206*150812a8SEvalZero __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 207*150812a8SEvalZero __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 208*150812a8SEvalZero __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 209*150812a8SEvalZero __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 210*150812a8SEvalZero __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 211*150812a8SEvalZero __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 212*150812a8SEvalZero __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 213*150812a8SEvalZero __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 214*150812a8SEvalZero __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 215*150812a8SEvalZero } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 216*150812a8SEvalZero 217*150812a8SEvalZero 218*150812a8SEvalZero /** 219*150812a8SEvalZero * @brief POWER_RAM [RAM] (Unspecified) 220*150812a8SEvalZero */ 221*150812a8SEvalZero typedef struct { 222*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register. 223*150812a8SEvalZero The RAM size will vary depending on product 224*150812a8SEvalZero variant, and the RAMn register will only 225*150812a8SEvalZero be present if the corresponding RAM AHB 226*150812a8SEvalZero slave is present on the device. */ 227*150812a8SEvalZero __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set 228*150812a8SEvalZero register */ 229*150812a8SEvalZero __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear 230*150812a8SEvalZero register */ 231*150812a8SEvalZero __IM uint32_t RESERVED; 232*150812a8SEvalZero } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 233*150812a8SEvalZero 234*150812a8SEvalZero 235*150812a8SEvalZero /** 236*150812a8SEvalZero * @brief UARTE_PSEL [PSEL] (Unspecified) 237*150812a8SEvalZero */ 238*150812a8SEvalZero typedef struct { 239*150812a8SEvalZero __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 240*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 241*150812a8SEvalZero __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 242*150812a8SEvalZero __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 243*150812a8SEvalZero } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 244*150812a8SEvalZero 245*150812a8SEvalZero 246*150812a8SEvalZero /** 247*150812a8SEvalZero * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 248*150812a8SEvalZero */ 249*150812a8SEvalZero typedef struct { 250*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 251*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 252*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 253*150812a8SEvalZero } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 254*150812a8SEvalZero 255*150812a8SEvalZero 256*150812a8SEvalZero /** 257*150812a8SEvalZero * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 258*150812a8SEvalZero */ 259*150812a8SEvalZero typedef struct { 260*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 261*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 262*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 263*150812a8SEvalZero } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 264*150812a8SEvalZero 265*150812a8SEvalZero 266*150812a8SEvalZero /** 267*150812a8SEvalZero * @brief TWIM_PSEL [PSEL] (Unspecified) 268*150812a8SEvalZero */ 269*150812a8SEvalZero typedef struct { 270*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 271*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 272*150812a8SEvalZero } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 273*150812a8SEvalZero 274*150812a8SEvalZero 275*150812a8SEvalZero /** 276*150812a8SEvalZero * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 277*150812a8SEvalZero */ 278*150812a8SEvalZero typedef struct { 279*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 280*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 281*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 282*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 283*150812a8SEvalZero } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 284*150812a8SEvalZero 285*150812a8SEvalZero 286*150812a8SEvalZero /** 287*150812a8SEvalZero * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 288*150812a8SEvalZero */ 289*150812a8SEvalZero typedef struct { 290*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 291*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 292*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 293*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 294*150812a8SEvalZero } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 295*150812a8SEvalZero 296*150812a8SEvalZero 297*150812a8SEvalZero /** 298*150812a8SEvalZero * @brief TWIS_PSEL [PSEL] (Unspecified) 299*150812a8SEvalZero */ 300*150812a8SEvalZero typedef struct { 301*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 302*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 303*150812a8SEvalZero } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 304*150812a8SEvalZero 305*150812a8SEvalZero 306*150812a8SEvalZero /** 307*150812a8SEvalZero * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 308*150812a8SEvalZero */ 309*150812a8SEvalZero typedef struct { 310*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 311*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 312*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 313*150812a8SEvalZero } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 314*150812a8SEvalZero 315*150812a8SEvalZero 316*150812a8SEvalZero /** 317*150812a8SEvalZero * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 318*150812a8SEvalZero */ 319*150812a8SEvalZero typedef struct { 320*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 321*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 322*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 323*150812a8SEvalZero } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 324*150812a8SEvalZero 325*150812a8SEvalZero 326*150812a8SEvalZero /** 327*150812a8SEvalZero * @brief SPIM_PSEL [PSEL] (Unspecified) 328*150812a8SEvalZero */ 329*150812a8SEvalZero typedef struct { 330*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 331*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 332*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 333*150812a8SEvalZero } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 334*150812a8SEvalZero 335*150812a8SEvalZero 336*150812a8SEvalZero /** 337*150812a8SEvalZero * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 338*150812a8SEvalZero */ 339*150812a8SEvalZero typedef struct { 340*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 341*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 342*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 343*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 344*150812a8SEvalZero } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 345*150812a8SEvalZero 346*150812a8SEvalZero 347*150812a8SEvalZero /** 348*150812a8SEvalZero * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 349*150812a8SEvalZero */ 350*150812a8SEvalZero typedef struct { 351*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 352*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 353*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 354*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 355*150812a8SEvalZero } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 356*150812a8SEvalZero 357*150812a8SEvalZero 358*150812a8SEvalZero /** 359*150812a8SEvalZero * @brief SPIS_PSEL [PSEL] (Unspecified) 360*150812a8SEvalZero */ 361*150812a8SEvalZero typedef struct { 362*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 363*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 364*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 365*150812a8SEvalZero __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 366*150812a8SEvalZero } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 367*150812a8SEvalZero 368*150812a8SEvalZero 369*150812a8SEvalZero /** 370*150812a8SEvalZero * @brief SPIS_RXD [RXD] (Unspecified) 371*150812a8SEvalZero */ 372*150812a8SEvalZero typedef struct { 373*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 374*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 375*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 376*150812a8SEvalZero } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 377*150812a8SEvalZero 378*150812a8SEvalZero 379*150812a8SEvalZero /** 380*150812a8SEvalZero * @brief SPIS_TXD [TXD] (Unspecified) 381*150812a8SEvalZero */ 382*150812a8SEvalZero typedef struct { 383*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 384*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 385*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 386*150812a8SEvalZero } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 387*150812a8SEvalZero 388*150812a8SEvalZero 389*150812a8SEvalZero /** 390*150812a8SEvalZero * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 391*150812a8SEvalZero */ 392*150812a8SEvalZero typedef struct { 393*150812a8SEvalZero __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last results is equal 394*150812a8SEvalZero or above CH[n].LIMIT.HIGH */ 395*150812a8SEvalZero __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last results is equal 396*150812a8SEvalZero or below CH[n].LIMIT.LOW */ 397*150812a8SEvalZero } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 398*150812a8SEvalZero 399*150812a8SEvalZero 400*150812a8SEvalZero /** 401*150812a8SEvalZero * @brief SAADC_CH [CH] (Unspecified) 402*150812a8SEvalZero */ 403*150812a8SEvalZero typedef struct { 404*150812a8SEvalZero __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection 405*150812a8SEvalZero for CH[n] */ 406*150812a8SEvalZero __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection 407*150812a8SEvalZero for CH[n] */ 408*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for 409*150812a8SEvalZero CH[n] */ 410*150812a8SEvalZero __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event 411*150812a8SEvalZero monitoring a channel */ 412*150812a8SEvalZero } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 413*150812a8SEvalZero 414*150812a8SEvalZero 415*150812a8SEvalZero /** 416*150812a8SEvalZero * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 417*150812a8SEvalZero */ 418*150812a8SEvalZero typedef struct { 419*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 420*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 421*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 422*150812a8SEvalZero START */ 423*150812a8SEvalZero } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 424*150812a8SEvalZero 425*150812a8SEvalZero 426*150812a8SEvalZero /** 427*150812a8SEvalZero * @brief QDEC_PSEL [PSEL] (Unspecified) 428*150812a8SEvalZero */ 429*150812a8SEvalZero typedef struct { 430*150812a8SEvalZero __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 431*150812a8SEvalZero __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 432*150812a8SEvalZero __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 433*150812a8SEvalZero } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 434*150812a8SEvalZero 435*150812a8SEvalZero 436*150812a8SEvalZero /** 437*150812a8SEvalZero * @brief PWM_SEQ [SEQ] (Unspecified) 438*150812a8SEvalZero */ 439*150812a8SEvalZero typedef struct { 440*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in 441*150812a8SEvalZero RAM of this sequence */ 442*150812a8SEvalZero __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty 443*150812a8SEvalZero cycles) in this sequence */ 444*150812a8SEvalZero __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional 445*150812a8SEvalZero PWM periods between samples loaded into 446*150812a8SEvalZero compare register */ 447*150812a8SEvalZero __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the 448*150812a8SEvalZero sequence */ 449*150812a8SEvalZero __IM uint32_t RESERVED[4]; 450*150812a8SEvalZero } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 451*150812a8SEvalZero 452*150812a8SEvalZero 453*150812a8SEvalZero /** 454*150812a8SEvalZero * @brief PWM_PSEL [PSEL] (Unspecified) 455*150812a8SEvalZero */ 456*150812a8SEvalZero typedef struct { 457*150812a8SEvalZero __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select 458*150812a8SEvalZero for PWM channel n */ 459*150812a8SEvalZero } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 460*150812a8SEvalZero 461*150812a8SEvalZero 462*150812a8SEvalZero /** 463*150812a8SEvalZero * @brief PDM_PSEL [PSEL] (Unspecified) 464*150812a8SEvalZero */ 465*150812a8SEvalZero typedef struct { 466*150812a8SEvalZero __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 467*150812a8SEvalZero __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 468*150812a8SEvalZero } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 469*150812a8SEvalZero 470*150812a8SEvalZero 471*150812a8SEvalZero /** 472*150812a8SEvalZero * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 473*150812a8SEvalZero */ 474*150812a8SEvalZero typedef struct { 475*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 476*150812a8SEvalZero EasyDMA */ 477*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 478*150812a8SEvalZero mode */ 479*150812a8SEvalZero } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 480*150812a8SEvalZero 481*150812a8SEvalZero 482*150812a8SEvalZero /** 483*150812a8SEvalZero * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 484*150812a8SEvalZero */ 485*150812a8SEvalZero typedef struct { 486*150812a8SEvalZero __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group 487*150812a8SEvalZero n */ 488*150812a8SEvalZero __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group 489*150812a8SEvalZero n */ 490*150812a8SEvalZero } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 491*150812a8SEvalZero 492*150812a8SEvalZero 493*150812a8SEvalZero /** 494*150812a8SEvalZero * @brief PPI_CH [CH] (PPI Channel) 495*150812a8SEvalZero */ 496*150812a8SEvalZero typedef struct { 497*150812a8SEvalZero __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ 498*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ 499*150812a8SEvalZero } PPI_CH_Type; /*!< Size = 8 (0x8) */ 500*150812a8SEvalZero 501*150812a8SEvalZero 502*150812a8SEvalZero /** 503*150812a8SEvalZero * @brief PPI_FORK [FORK] (Fork) 504*150812a8SEvalZero */ 505*150812a8SEvalZero typedef struct { 506*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ 507*150812a8SEvalZero } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 508*150812a8SEvalZero 509*150812a8SEvalZero 510*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_clusters */ 511*150812a8SEvalZero 512*150812a8SEvalZero 513*150812a8SEvalZero /* =========================================================================================================================== */ 514*150812a8SEvalZero /* ================ Device Specific Peripheral Section ================ */ 515*150812a8SEvalZero /* =========================================================================================================================== */ 516*150812a8SEvalZero 517*150812a8SEvalZero 518*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripherals 519*150812a8SEvalZero * @{ 520*150812a8SEvalZero */ 521*150812a8SEvalZero 522*150812a8SEvalZero 523*150812a8SEvalZero 524*150812a8SEvalZero /* =========================================================================================================================== */ 525*150812a8SEvalZero /* ================ FICR ================ */ 526*150812a8SEvalZero /* =========================================================================================================================== */ 527*150812a8SEvalZero 528*150812a8SEvalZero 529*150812a8SEvalZero /** 530*150812a8SEvalZero * @brief Factory information configuration registers (FICR) 531*150812a8SEvalZero */ 532*150812a8SEvalZero 533*150812a8SEvalZero typedef struct { /*!< (@ 0x10000000) FICR Structure */ 534*150812a8SEvalZero __IM uint32_t RESERVED[4]; 535*150812a8SEvalZero __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 536*150812a8SEvalZero __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 537*150812a8SEvalZero __IM uint32_t RESERVED1[18]; 538*150812a8SEvalZero __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ 539*150812a8SEvalZero __IM uint32_t RESERVED2[6]; 540*150812a8SEvalZero __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word 541*150812a8SEvalZero n */ 542*150812a8SEvalZero __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity root, word 543*150812a8SEvalZero n */ 544*150812a8SEvalZero __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 545*150812a8SEvalZero __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ 546*150812a8SEvalZero __IM uint32_t RESERVED3[21]; 547*150812a8SEvalZero __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 548*150812a8SEvalZero __IM uint32_t RESERVED4[185]; 549*150812a8SEvalZero __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 550*150812a8SEvalZero coefficients */ 551*150812a8SEvalZero } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 552*150812a8SEvalZero 553*150812a8SEvalZero 554*150812a8SEvalZero 555*150812a8SEvalZero /* =========================================================================================================================== */ 556*150812a8SEvalZero /* ================ UICR ================ */ 557*150812a8SEvalZero /* =========================================================================================================================== */ 558*150812a8SEvalZero 559*150812a8SEvalZero 560*150812a8SEvalZero /** 561*150812a8SEvalZero * @brief User information configuration registers (UICR) 562*150812a8SEvalZero */ 563*150812a8SEvalZero 564*150812a8SEvalZero typedef struct { /*!< (@ 0x10001000) UICR Structure */ 565*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 566*150812a8SEvalZero __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 567*150812a8SEvalZero __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 568*150812a8SEvalZero __IM uint32_t RESERVED; 569*150812a8SEvalZero __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 570*150812a8SEvalZero __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic 571*150812a8SEvalZero firmware design */ 572*150812a8SEvalZero __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic 573*150812a8SEvalZero hardware design */ 574*150812a8SEvalZero __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ 575*150812a8SEvalZero __IM uint32_t RESERVED1[64]; 576*150812a8SEvalZero __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET 577*150812a8SEvalZero function (see POWER chapter for details) */ 578*150812a8SEvalZero __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 579*150812a8SEvalZero } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ 580*150812a8SEvalZero 581*150812a8SEvalZero 582*150812a8SEvalZero 583*150812a8SEvalZero /* =========================================================================================================================== */ 584*150812a8SEvalZero /* ================ BPROT ================ */ 585*150812a8SEvalZero /* =========================================================================================================================== */ 586*150812a8SEvalZero 587*150812a8SEvalZero 588*150812a8SEvalZero /** 589*150812a8SEvalZero * @brief Block Protect (BPROT) 590*150812a8SEvalZero */ 591*150812a8SEvalZero 592*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 593*150812a8SEvalZero __IM uint32_t RESERVED[384]; 594*150812a8SEvalZero __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 595*150812a8SEvalZero __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 596*150812a8SEvalZero __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ 597*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ 598*150812a8SEvalZero } NRF_BPROT_Type; /*!< Size = 1552 (0x610) */ 599*150812a8SEvalZero 600*150812a8SEvalZero 601*150812a8SEvalZero 602*150812a8SEvalZero /* =========================================================================================================================== */ 603*150812a8SEvalZero /* ================ CLOCK ================ */ 604*150812a8SEvalZero /* =========================================================================================================================== */ 605*150812a8SEvalZero 606*150812a8SEvalZero 607*150812a8SEvalZero /** 608*150812a8SEvalZero * @brief Clock control (CLOCK) 609*150812a8SEvalZero */ 610*150812a8SEvalZero 611*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 612*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 613*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 614*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 615*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 616*150812a8SEvalZero __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 617*150812a8SEvalZero __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 618*150812a8SEvalZero __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 619*150812a8SEvalZero __IM uint32_t RESERVED[57]; 620*150812a8SEvalZero __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 621*150812a8SEvalZero __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 622*150812a8SEvalZero __IM uint32_t RESERVED1; 623*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 624*150812a8SEvalZero __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 625*150812a8SEvalZero __IM uint32_t RESERVED2[124]; 626*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 627*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 628*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 629*150812a8SEvalZero __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 630*150812a8SEvalZero triggered */ 631*150812a8SEvalZero __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 632*150812a8SEvalZero __IM uint32_t RESERVED4; 633*150812a8SEvalZero __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 634*150812a8SEvalZero triggered */ 635*150812a8SEvalZero __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 636*150812a8SEvalZero __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 637*150812a8SEvalZero task was triggered */ 638*150812a8SEvalZero __IM uint32_t RESERVED5[62]; 639*150812a8SEvalZero __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 640*150812a8SEvalZero __IM uint32_t RESERVED6[7]; 641*150812a8SEvalZero __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 642*150812a8SEvalZero } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 643*150812a8SEvalZero 644*150812a8SEvalZero 645*150812a8SEvalZero 646*150812a8SEvalZero /* =========================================================================================================================== */ 647*150812a8SEvalZero /* ================ POWER ================ */ 648*150812a8SEvalZero /* =========================================================================================================================== */ 649*150812a8SEvalZero 650*150812a8SEvalZero 651*150812a8SEvalZero /** 652*150812a8SEvalZero * @brief Power control (POWER) 653*150812a8SEvalZero */ 654*150812a8SEvalZero 655*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) POWER Structure */ 656*150812a8SEvalZero __IM uint32_t RESERVED[30]; 657*150812a8SEvalZero __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 658*150812a8SEvalZero __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 659*150812a8SEvalZero __IM uint32_t RESERVED1[34]; 660*150812a8SEvalZero __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 661*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 662*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 663*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 664*150812a8SEvalZero __IM uint32_t RESERVED3[122]; 665*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 666*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 667*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 668*150812a8SEvalZero __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 669*150812a8SEvalZero __IM uint32_t RESERVED5[63]; 670*150812a8SEvalZero __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 671*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 672*150812a8SEvalZero __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 673*150812a8SEvalZero __IM uint32_t RESERVED7[2]; 674*150812a8SEvalZero __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 675*150812a8SEvalZero __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 676*150812a8SEvalZero __IM uint32_t RESERVED8[21]; 677*150812a8SEvalZero __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 678*150812a8SEvalZero __IM uint32_t RESERVED9[225]; 679*150812a8SEvalZero __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 680*150812a8SEvalZero } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 681*150812a8SEvalZero 682*150812a8SEvalZero 683*150812a8SEvalZero 684*150812a8SEvalZero /* =========================================================================================================================== */ 685*150812a8SEvalZero /* ================ RADIO ================ */ 686*150812a8SEvalZero /* =========================================================================================================================== */ 687*150812a8SEvalZero 688*150812a8SEvalZero 689*150812a8SEvalZero /** 690*150812a8SEvalZero * @brief 2.4 GHz Radio (RADIO) 691*150812a8SEvalZero */ 692*150812a8SEvalZero 693*150812a8SEvalZero typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 694*150812a8SEvalZero __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 695*150812a8SEvalZero __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 696*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 697*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 698*150812a8SEvalZero __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 699*150812a8SEvalZero __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 700*150812a8SEvalZero the receive signal strength. */ 701*150812a8SEvalZero __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 702*150812a8SEvalZero __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 703*150812a8SEvalZero __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 704*150812a8SEvalZero __IM uint32_t RESERVED[55]; 705*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 706*150812a8SEvalZero __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 707*150812a8SEvalZero __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 708*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 709*150812a8SEvalZero __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 710*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 711*150812a8SEvalZero packet */ 712*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 713*150812a8SEvalZero received packet */ 714*150812a8SEvalZero __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 715*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 716*150812a8SEvalZero __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 717*150812a8SEvalZero __IM uint32_t RESERVED2; 718*150812a8SEvalZero __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 719*150812a8SEvalZero __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 720*150812a8SEvalZero __IM uint32_t RESERVED3[50]; 721*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 722*150812a8SEvalZero __IM uint32_t RESERVED4[64]; 723*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 724*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 725*150812a8SEvalZero __IM uint32_t RESERVED5[61]; 726*150812a8SEvalZero __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 727*150812a8SEvalZero __IM uint32_t RESERVED6; 728*150812a8SEvalZero __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 729*150812a8SEvalZero __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 730*150812a8SEvalZero __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 731*150812a8SEvalZero __IM uint32_t RESERVED7[60]; 732*150812a8SEvalZero __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 733*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 734*150812a8SEvalZero __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 735*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 736*150812a8SEvalZero __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 737*150812a8SEvalZero __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 738*150812a8SEvalZero __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 739*150812a8SEvalZero __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 740*150812a8SEvalZero __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 741*150812a8SEvalZero __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 742*150812a8SEvalZero __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 743*150812a8SEvalZero __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 744*150812a8SEvalZero __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 745*150812a8SEvalZero __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 746*150812a8SEvalZero __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 747*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ 748*150812a8SEvalZero __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 749*150812a8SEvalZero __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 750*150812a8SEvalZero __IM uint32_t RESERVED8; 751*150812a8SEvalZero __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 752*150812a8SEvalZero __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 753*150812a8SEvalZero __IM uint32_t RESERVED9[2]; 754*150812a8SEvalZero __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 755*150812a8SEvalZero __IM uint32_t RESERVED10[39]; 756*150812a8SEvalZero __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base 757*150812a8SEvalZero segment n */ 758*150812a8SEvalZero __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix 759*150812a8SEvalZero n */ 760*150812a8SEvalZero __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 761*150812a8SEvalZero __IM uint32_t RESERVED11[3]; 762*150812a8SEvalZero __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 763*150812a8SEvalZero __IM uint32_t RESERVED12[618]; 764*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 765*150812a8SEvalZero } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 766*150812a8SEvalZero 767*150812a8SEvalZero 768*150812a8SEvalZero 769*150812a8SEvalZero /* =========================================================================================================================== */ 770*150812a8SEvalZero /* ================ UARTE0 ================ */ 771*150812a8SEvalZero /* =========================================================================================================================== */ 772*150812a8SEvalZero 773*150812a8SEvalZero 774*150812a8SEvalZero /** 775*150812a8SEvalZero * @brief UART with EasyDMA (UARTE0) 776*150812a8SEvalZero */ 777*150812a8SEvalZero 778*150812a8SEvalZero typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 779*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 780*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 781*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 782*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 783*150812a8SEvalZero __IM uint32_t RESERVED[7]; 784*150812a8SEvalZero __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 785*150812a8SEvalZero __IM uint32_t RESERVED1[52]; 786*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 787*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 788*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 789*150812a8SEvalZero transferred to Data RAM) */ 790*150812a8SEvalZero __IM uint32_t RESERVED2; 791*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 792*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 793*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 794*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 795*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 796*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 797*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 798*150812a8SEvalZero __IM uint32_t RESERVED5; 799*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 800*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 801*150812a8SEvalZero __IM uint32_t RESERVED6; 802*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 803*150812a8SEvalZero __IM uint32_t RESERVED7[41]; 804*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 805*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 806*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 807*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 808*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 809*150812a8SEvalZero __IM uint32_t RESERVED9[93]; 810*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 811*150812a8SEvalZero one to clear. */ 812*150812a8SEvalZero __IM uint32_t RESERVED10[31]; 813*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 814*150812a8SEvalZero __IM uint32_t RESERVED11; 815*150812a8SEvalZero __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 816*150812a8SEvalZero __IM uint32_t RESERVED12[3]; 817*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 818*150812a8SEvalZero selected. */ 819*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 820*150812a8SEvalZero __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 821*150812a8SEvalZero __IM uint32_t RESERVED14; 822*150812a8SEvalZero __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 823*150812a8SEvalZero __IM uint32_t RESERVED15[7]; 824*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 825*150812a8SEvalZero } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 826*150812a8SEvalZero 827*150812a8SEvalZero 828*150812a8SEvalZero 829*150812a8SEvalZero /* =========================================================================================================================== */ 830*150812a8SEvalZero /* ================ TWIM0 ================ */ 831*150812a8SEvalZero /* =========================================================================================================================== */ 832*150812a8SEvalZero 833*150812a8SEvalZero 834*150812a8SEvalZero /** 835*150812a8SEvalZero * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) 836*150812a8SEvalZero */ 837*150812a8SEvalZero 838*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 839*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 840*150812a8SEvalZero __IM uint32_t RESERVED; 841*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 842*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 843*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 844*150812a8SEvalZero TWI master is not suspended. */ 845*150812a8SEvalZero __IM uint32_t RESERVED2; 846*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 847*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 848*150812a8SEvalZero __IM uint32_t RESERVED3[56]; 849*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 850*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 851*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 852*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 853*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 854*150812a8SEvalZero task has been issued, TWI traffic is now 855*150812a8SEvalZero suspended. */ 856*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 857*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 858*150812a8SEvalZero __IM uint32_t RESERVED6[2]; 859*150812a8SEvalZero __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 860*150812a8SEvalZero __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 861*150812a8SEvalZero byte */ 862*150812a8SEvalZero __IM uint32_t RESERVED7[39]; 863*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 864*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 865*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 866*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 867*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 868*150812a8SEvalZero __IM uint32_t RESERVED9[110]; 869*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 870*150812a8SEvalZero __IM uint32_t RESERVED10[14]; 871*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 872*150812a8SEvalZero __IM uint32_t RESERVED11; 873*150812a8SEvalZero __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 874*150812a8SEvalZero __IM uint32_t RESERVED12[5]; 875*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 876*150812a8SEvalZero source selected. */ 877*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 878*150812a8SEvalZero __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 879*150812a8SEvalZero __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 880*150812a8SEvalZero __IM uint32_t RESERVED14[13]; 881*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 882*150812a8SEvalZero } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 883*150812a8SEvalZero 884*150812a8SEvalZero 885*150812a8SEvalZero 886*150812a8SEvalZero /* =========================================================================================================================== */ 887*150812a8SEvalZero /* ================ TWIS0 ================ */ 888*150812a8SEvalZero /* =========================================================================================================================== */ 889*150812a8SEvalZero 890*150812a8SEvalZero 891*150812a8SEvalZero /** 892*150812a8SEvalZero * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) 893*150812a8SEvalZero */ 894*150812a8SEvalZero 895*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 896*150812a8SEvalZero __IM uint32_t RESERVED[5]; 897*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 898*150812a8SEvalZero __IM uint32_t RESERVED1; 899*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 900*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 901*150812a8SEvalZero __IM uint32_t RESERVED2[3]; 902*150812a8SEvalZero __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 903*150812a8SEvalZero __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 904*150812a8SEvalZero __IM uint32_t RESERVED3[51]; 905*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 906*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 907*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 908*150812a8SEvalZero __IM uint32_t RESERVED5[9]; 909*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 910*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 911*150812a8SEvalZero __IM uint32_t RESERVED6[4]; 912*150812a8SEvalZero __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 913*150812a8SEvalZero __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 914*150812a8SEvalZero __IM uint32_t RESERVED7[37]; 915*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 916*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 917*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 918*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 919*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 920*150812a8SEvalZero __IM uint32_t RESERVED9[113]; 921*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 922*150812a8SEvalZero __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 923*150812a8SEvalZero a match */ 924*150812a8SEvalZero __IM uint32_t RESERVED10[10]; 925*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 926*150812a8SEvalZero __IM uint32_t RESERVED11; 927*150812a8SEvalZero __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 928*150812a8SEvalZero __IM uint32_t RESERVED12[9]; 929*150812a8SEvalZero __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 930*150812a8SEvalZero __IM uint32_t RESERVED13; 931*150812a8SEvalZero __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 932*150812a8SEvalZero __IM uint32_t RESERVED14[14]; 933*150812a8SEvalZero __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address 934*150812a8SEvalZero n */ 935*150812a8SEvalZero __IM uint32_t RESERVED15; 936*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 937*150812a8SEvalZero mechanism */ 938*150812a8SEvalZero __IM uint32_t RESERVED16[10]; 939*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 940*150812a8SEvalZero of an over-read of the transmit buffer. */ 941*150812a8SEvalZero } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 942*150812a8SEvalZero 943*150812a8SEvalZero 944*150812a8SEvalZero 945*150812a8SEvalZero /* =========================================================================================================================== */ 946*150812a8SEvalZero /* ================ SPIM0 ================ */ 947*150812a8SEvalZero /* =========================================================================================================================== */ 948*150812a8SEvalZero 949*150812a8SEvalZero 950*150812a8SEvalZero /** 951*150812a8SEvalZero * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0) 952*150812a8SEvalZero */ 953*150812a8SEvalZero 954*150812a8SEvalZero typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */ 955*150812a8SEvalZero __IM uint32_t RESERVED[4]; 956*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 957*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 958*150812a8SEvalZero __IM uint32_t RESERVED1; 959*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 960*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 961*150812a8SEvalZero __IM uint32_t RESERVED2[56]; 962*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 963*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 964*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 965*150812a8SEvalZero __IM uint32_t RESERVED4; 966*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 967*150812a8SEvalZero __IM uint32_t RESERVED5; 968*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 969*150812a8SEvalZero __IM uint32_t RESERVED6[10]; 970*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 971*150812a8SEvalZero __IM uint32_t RESERVED7[44]; 972*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 973*150812a8SEvalZero __IM uint32_t RESERVED8[64]; 974*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 975*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 976*150812a8SEvalZero __IM uint32_t RESERVED9[125]; 977*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 978*150812a8SEvalZero __IM uint32_t RESERVED10; 979*150812a8SEvalZero __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 980*150812a8SEvalZero __IM uint32_t RESERVED11[4]; 981*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 982*150812a8SEvalZero source selected. */ 983*150812a8SEvalZero __IM uint32_t RESERVED12[3]; 984*150812a8SEvalZero __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 985*150812a8SEvalZero __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 986*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 987*150812a8SEvalZero __IM uint32_t RESERVED13[26]; 988*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 989*150812a8SEvalZero case and over-read of the TXD buffer. */ 990*150812a8SEvalZero } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 991*150812a8SEvalZero 992*150812a8SEvalZero 993*150812a8SEvalZero 994*150812a8SEvalZero /* =========================================================================================================================== */ 995*150812a8SEvalZero /* ================ SPIS0 ================ */ 996*150812a8SEvalZero /* =========================================================================================================================== */ 997*150812a8SEvalZero 998*150812a8SEvalZero 999*150812a8SEvalZero /** 1000*150812a8SEvalZero * @brief SPI Slave (SPIS0) 1001*150812a8SEvalZero */ 1002*150812a8SEvalZero 1003*150812a8SEvalZero typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */ 1004*150812a8SEvalZero __IM uint32_t RESERVED[9]; 1005*150812a8SEvalZero __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1006*150812a8SEvalZero __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1007*150812a8SEvalZero to acquire it */ 1008*150812a8SEvalZero __IM uint32_t RESERVED1[54]; 1009*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1010*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 1011*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1012*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1013*150812a8SEvalZero __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1014*150812a8SEvalZero __IM uint32_t RESERVED4[53]; 1015*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1016*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 1017*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1018*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1019*150812a8SEvalZero __IM uint32_t RESERVED6[61]; 1020*150812a8SEvalZero __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1021*150812a8SEvalZero __IM uint32_t RESERVED7[15]; 1022*150812a8SEvalZero __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1023*150812a8SEvalZero __IM uint32_t RESERVED8[47]; 1024*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1025*150812a8SEvalZero __IM uint32_t RESERVED9; 1026*150812a8SEvalZero __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1027*150812a8SEvalZero __IM uint32_t RESERVED10[7]; 1028*150812a8SEvalZero __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1029*150812a8SEvalZero __IM uint32_t RESERVED11; 1030*150812a8SEvalZero __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1031*150812a8SEvalZero __IM uint32_t RESERVED12; 1032*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1033*150812a8SEvalZero __IM uint32_t RESERVED13; 1034*150812a8SEvalZero __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1035*150812a8SEvalZero of an ignored transaction. */ 1036*150812a8SEvalZero __IM uint32_t RESERVED14[24]; 1037*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1038*150812a8SEvalZero } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1039*150812a8SEvalZero 1040*150812a8SEvalZero 1041*150812a8SEvalZero 1042*150812a8SEvalZero /* =========================================================================================================================== */ 1043*150812a8SEvalZero /* ================ GPIOTE ================ */ 1044*150812a8SEvalZero /* =========================================================================================================================== */ 1045*150812a8SEvalZero 1046*150812a8SEvalZero 1047*150812a8SEvalZero /** 1048*150812a8SEvalZero * @brief GPIO Tasks and Events (GPIOTE) 1049*150812a8SEvalZero */ 1050*150812a8SEvalZero 1051*150812a8SEvalZero typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1052*150812a8SEvalZero __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to 1053*150812a8SEvalZero pin specified in CONFIG[n].PSEL. Action 1054*150812a8SEvalZero on pin is configured in CONFIG[n].POLARITY. */ 1055*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1056*150812a8SEvalZero __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to 1057*150812a8SEvalZero pin specified in CONFIG[n].PSEL. Action 1058*150812a8SEvalZero on pin is to set it high. */ 1059*150812a8SEvalZero __IM uint32_t RESERVED1[4]; 1060*150812a8SEvalZero __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to 1061*150812a8SEvalZero pin specified in CONFIG[n].PSEL. Action 1062*150812a8SEvalZero on pin is to set it low. */ 1063*150812a8SEvalZero __IM uint32_t RESERVED2[32]; 1064*150812a8SEvalZero __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from 1065*150812a8SEvalZero pin specified in CONFIG[n].PSEL */ 1066*150812a8SEvalZero __IM uint32_t RESERVED3[23]; 1067*150812a8SEvalZero __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1068*150812a8SEvalZero with SENSE mechanism enabled */ 1069*150812a8SEvalZero __IM uint32_t RESERVED4[97]; 1070*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1071*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1072*150812a8SEvalZero __IM uint32_t RESERVED5[129]; 1073*150812a8SEvalZero __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for 1074*150812a8SEvalZero OUT[n], SET[n] and CLR[n] tasks and IN[n] 1075*150812a8SEvalZero event */ 1076*150812a8SEvalZero } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1077*150812a8SEvalZero 1078*150812a8SEvalZero 1079*150812a8SEvalZero 1080*150812a8SEvalZero /* =========================================================================================================================== */ 1081*150812a8SEvalZero /* ================ SAADC ================ */ 1082*150812a8SEvalZero /* =========================================================================================================================== */ 1083*150812a8SEvalZero 1084*150812a8SEvalZero 1085*150812a8SEvalZero /** 1086*150812a8SEvalZero * @brief Analog to Digital Converter (SAADC) 1087*150812a8SEvalZero */ 1088*150812a8SEvalZero 1089*150812a8SEvalZero typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1090*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1091*150812a8SEvalZero RAM */ 1092*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1093*150812a8SEvalZero are sampled */ 1094*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1095*150812a8SEvalZero __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1096*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1097*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1098*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1099*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1100*150812a8SEvalZero on the mode, multiple conversions might 1101*150812a8SEvalZero be needed for a result to be transferred 1102*150812a8SEvalZero to RAM. */ 1103*150812a8SEvalZero __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1104*150812a8SEvalZero __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1105*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1106*150812a8SEvalZero __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1107*150812a8SEvalZero __IM uint32_t RESERVED1[106]; 1108*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1109*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1110*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1111*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 1112*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1113*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 1114*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1115*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 1116*150812a8SEvalZero __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1117*150812a8SEvalZero __IM uint32_t RESERVED5[24]; 1118*150812a8SEvalZero __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1119*150812a8SEvalZero __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1120*150812a8SEvalZero not be combined with SCAN. The RESOLUTION 1121*150812a8SEvalZero is applied before averaging, thus for high 1122*150812a8SEvalZero OVERSAMPLE a higher RESOLUTION should be 1123*150812a8SEvalZero used. */ 1124*150812a8SEvalZero __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1125*150812a8SEvalZero __IM uint32_t RESERVED6[12]; 1126*150812a8SEvalZero __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1127*150812a8SEvalZero } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1128*150812a8SEvalZero 1129*150812a8SEvalZero 1130*150812a8SEvalZero 1131*150812a8SEvalZero /* =========================================================================================================================== */ 1132*150812a8SEvalZero /* ================ TIMER0 ================ */ 1133*150812a8SEvalZero /* =========================================================================================================================== */ 1134*150812a8SEvalZero 1135*150812a8SEvalZero 1136*150812a8SEvalZero /** 1137*150812a8SEvalZero * @brief Timer/Counter 0 (TIMER0) 1138*150812a8SEvalZero */ 1139*150812a8SEvalZero 1140*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1141*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1142*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1143*150812a8SEvalZero __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1144*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1145*150812a8SEvalZero __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1146*150812a8SEvalZero __IM uint32_t RESERVED[11]; 1147*150812a8SEvalZero __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value 1148*150812a8SEvalZero to CC[n] register */ 1149*150812a8SEvalZero __IM uint32_t RESERVED1[58]; 1150*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1151*150812a8SEvalZero match */ 1152*150812a8SEvalZero __IM uint32_t RESERVED2[42]; 1153*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1154*150812a8SEvalZero __IM uint32_t RESERVED3[64]; 1155*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1156*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1157*150812a8SEvalZero __IM uint32_t RESERVED4[126]; 1158*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1159*150812a8SEvalZero __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1160*150812a8SEvalZero __IM uint32_t RESERVED5; 1161*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1162*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 1163*150812a8SEvalZero __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register 1164*150812a8SEvalZero n */ 1165*150812a8SEvalZero } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1166*150812a8SEvalZero 1167*150812a8SEvalZero 1168*150812a8SEvalZero 1169*150812a8SEvalZero /* =========================================================================================================================== */ 1170*150812a8SEvalZero /* ================ RTC0 ================ */ 1171*150812a8SEvalZero /* =========================================================================================================================== */ 1172*150812a8SEvalZero 1173*150812a8SEvalZero 1174*150812a8SEvalZero /** 1175*150812a8SEvalZero * @brief Real time counter 0 (RTC0) 1176*150812a8SEvalZero */ 1177*150812a8SEvalZero 1178*150812a8SEvalZero typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1179*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1180*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1181*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1182*150812a8SEvalZero __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1183*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1184*150812a8SEvalZero __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1185*150812a8SEvalZero __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1186*150812a8SEvalZero __IM uint32_t RESERVED1[14]; 1187*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1188*150812a8SEvalZero match */ 1189*150812a8SEvalZero __IM uint32_t RESERVED2[109]; 1190*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1191*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1192*150812a8SEvalZero __IM uint32_t RESERVED3[13]; 1193*150812a8SEvalZero __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1194*150812a8SEvalZero __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1195*150812a8SEvalZero __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1196*150812a8SEvalZero __IM uint32_t RESERVED4[110]; 1197*150812a8SEvalZero __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1198*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1199*150812a8SEvalZero t be written when RTC is stopped */ 1200*150812a8SEvalZero __IM uint32_t RESERVED5[13]; 1201*150812a8SEvalZero __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ 1202*150812a8SEvalZero } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1203*150812a8SEvalZero 1204*150812a8SEvalZero 1205*150812a8SEvalZero 1206*150812a8SEvalZero /* =========================================================================================================================== */ 1207*150812a8SEvalZero /* ================ TEMP ================ */ 1208*150812a8SEvalZero /* =========================================================================================================================== */ 1209*150812a8SEvalZero 1210*150812a8SEvalZero 1211*150812a8SEvalZero /** 1212*150812a8SEvalZero * @brief Temperature Sensor (TEMP) 1213*150812a8SEvalZero */ 1214*150812a8SEvalZero 1215*150812a8SEvalZero typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1216*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1217*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1218*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1219*150812a8SEvalZero __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1220*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 1221*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1222*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1223*150812a8SEvalZero __IM uint32_t RESERVED2[127]; 1224*150812a8SEvalZero __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1225*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1226*150812a8SEvalZero __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1227*150812a8SEvalZero __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1228*150812a8SEvalZero __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1229*150812a8SEvalZero __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1230*150812a8SEvalZero __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1231*150812a8SEvalZero __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1232*150812a8SEvalZero __IM uint32_t RESERVED4[2]; 1233*150812a8SEvalZero __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1234*150812a8SEvalZero __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1235*150812a8SEvalZero __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1236*150812a8SEvalZero __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1237*150812a8SEvalZero __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1238*150812a8SEvalZero __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1239*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 1240*150812a8SEvalZero __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1241*150812a8SEvalZero __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1242*150812a8SEvalZero __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1243*150812a8SEvalZero __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1244*150812a8SEvalZero __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1245*150812a8SEvalZero } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1246*150812a8SEvalZero 1247*150812a8SEvalZero 1248*150812a8SEvalZero 1249*150812a8SEvalZero /* =========================================================================================================================== */ 1250*150812a8SEvalZero /* ================ RNG ================ */ 1251*150812a8SEvalZero /* =========================================================================================================================== */ 1252*150812a8SEvalZero 1253*150812a8SEvalZero 1254*150812a8SEvalZero /** 1255*150812a8SEvalZero * @brief Random Number Generator (RNG) 1256*150812a8SEvalZero */ 1257*150812a8SEvalZero 1258*150812a8SEvalZero typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1259*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1260*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1261*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1262*150812a8SEvalZero __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1263*150812a8SEvalZero written to the VALUE register */ 1264*150812a8SEvalZero __IM uint32_t RESERVED1[63]; 1265*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1266*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1267*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1268*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1269*150812a8SEvalZero __IM uint32_t RESERVED3[126]; 1270*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1271*150812a8SEvalZero __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1272*150812a8SEvalZero } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1273*150812a8SEvalZero 1274*150812a8SEvalZero 1275*150812a8SEvalZero 1276*150812a8SEvalZero /* =========================================================================================================================== */ 1277*150812a8SEvalZero /* ================ ECB ================ */ 1278*150812a8SEvalZero /* =========================================================================================================================== */ 1279*150812a8SEvalZero 1280*150812a8SEvalZero 1281*150812a8SEvalZero /** 1282*150812a8SEvalZero * @brief AES ECB Mode Encryption (ECB) 1283*150812a8SEvalZero */ 1284*150812a8SEvalZero 1285*150812a8SEvalZero typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1286*150812a8SEvalZero __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1287*150812a8SEvalZero __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1288*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1289*150812a8SEvalZero __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1290*150812a8SEvalZero __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1291*150812a8SEvalZero task or due to an error */ 1292*150812a8SEvalZero __IM uint32_t RESERVED1[127]; 1293*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1294*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1295*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 1296*150812a8SEvalZero __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1297*150812a8SEvalZero } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1298*150812a8SEvalZero 1299*150812a8SEvalZero 1300*150812a8SEvalZero 1301*150812a8SEvalZero /* =========================================================================================================================== */ 1302*150812a8SEvalZero /* ================ AAR ================ */ 1303*150812a8SEvalZero /* =========================================================================================================================== */ 1304*150812a8SEvalZero 1305*150812a8SEvalZero 1306*150812a8SEvalZero /** 1307*150812a8SEvalZero * @brief Accelerated Address Resolver (AAR) 1308*150812a8SEvalZero */ 1309*150812a8SEvalZero 1310*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1311*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1312*150812a8SEvalZero in the IRK data structure */ 1313*150812a8SEvalZero __IM uint32_t RESERVED; 1314*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1315*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 1316*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1317*150812a8SEvalZero __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1318*150812a8SEvalZero __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1319*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 1320*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1321*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1322*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1323*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1324*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1325*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1326*150812a8SEvalZero __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1327*150812a8SEvalZero __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1328*150812a8SEvalZero __IM uint32_t RESERVED5; 1329*150812a8SEvalZero __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1330*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1331*150812a8SEvalZero } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1332*150812a8SEvalZero 1333*150812a8SEvalZero 1334*150812a8SEvalZero 1335*150812a8SEvalZero /* =========================================================================================================================== */ 1336*150812a8SEvalZero /* ================ CCM ================ */ 1337*150812a8SEvalZero /* =========================================================================================================================== */ 1338*150812a8SEvalZero 1339*150812a8SEvalZero 1340*150812a8SEvalZero /** 1341*150812a8SEvalZero * @brief AES CCM Mode Encryption (CCM) 1342*150812a8SEvalZero */ 1343*150812a8SEvalZero 1344*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1345*150812a8SEvalZero __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1346*150812a8SEvalZero will stop by itself when completed. */ 1347*150812a8SEvalZero __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1348*150812a8SEvalZero stop by itself when completed. */ 1349*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1350*150812a8SEvalZero __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1351*150812a8SEvalZero the contents of the RATEOVERRIDE register 1352*150812a8SEvalZero for any ongoing encryption/decryption */ 1353*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1354*150812a8SEvalZero __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1355*150812a8SEvalZero __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1356*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1357*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 1358*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1359*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1360*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1361*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1362*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1363*150812a8SEvalZero __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1364*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1365*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1366*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1367*150812a8SEvalZero __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1368*150812a8SEvalZero NONCE vector */ 1369*150812a8SEvalZero __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1370*150812a8SEvalZero __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1371*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1372*150812a8SEvalZero __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH 1373*150812a8SEvalZero = Extended. */ 1374*150812a8SEvalZero __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1375*150812a8SEvalZero } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 1376*150812a8SEvalZero 1377*150812a8SEvalZero 1378*150812a8SEvalZero 1379*150812a8SEvalZero /* =========================================================================================================================== */ 1380*150812a8SEvalZero /* ================ WDT ================ */ 1381*150812a8SEvalZero /* =========================================================================================================================== */ 1382*150812a8SEvalZero 1383*150812a8SEvalZero 1384*150812a8SEvalZero /** 1385*150812a8SEvalZero * @brief Watchdog Timer (WDT) 1386*150812a8SEvalZero */ 1387*150812a8SEvalZero 1388*150812a8SEvalZero typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1389*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1390*150812a8SEvalZero __IM uint32_t RESERVED[63]; 1391*150812a8SEvalZero __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1392*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 1393*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1394*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1395*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 1396*150812a8SEvalZero __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1397*150812a8SEvalZero __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1398*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 1399*150812a8SEvalZero __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1400*150812a8SEvalZero __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1401*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1402*150812a8SEvalZero __IM uint32_t RESERVED4[60]; 1403*150812a8SEvalZero __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ 1404*150812a8SEvalZero } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1405*150812a8SEvalZero 1406*150812a8SEvalZero 1407*150812a8SEvalZero 1408*150812a8SEvalZero /* =========================================================================================================================== */ 1409*150812a8SEvalZero /* ================ QDEC ================ */ 1410*150812a8SEvalZero /* =========================================================================================================================== */ 1411*150812a8SEvalZero 1412*150812a8SEvalZero 1413*150812a8SEvalZero /** 1414*150812a8SEvalZero * @brief Quadrature Decoder (QDEC) 1415*150812a8SEvalZero */ 1416*150812a8SEvalZero 1417*150812a8SEvalZero typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1418*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1419*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1420*150812a8SEvalZero __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1421*150812a8SEvalZero __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1422*150812a8SEvalZero __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1423*150812a8SEvalZero __IM uint32_t RESERVED[59]; 1424*150812a8SEvalZero __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1425*150812a8SEvalZero written to the SAMPLE register */ 1426*150812a8SEvalZero __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1427*150812a8SEvalZero __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1428*150812a8SEvalZero __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1429*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1430*150812a8SEvalZero __IM uint32_t RESERVED1[59]; 1431*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1432*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1433*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1434*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1435*150812a8SEvalZero __IM uint32_t RESERVED3[125]; 1436*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1437*150812a8SEvalZero __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1438*150812a8SEvalZero __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1439*150812a8SEvalZero __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1440*150812a8SEvalZero __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1441*150812a8SEvalZero and DBLRDY events can be generated */ 1442*150812a8SEvalZero __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1443*150812a8SEvalZero __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1444*150812a8SEvalZero READCLRACC or RDCLRACC task */ 1445*150812a8SEvalZero __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1446*150812a8SEvalZero __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1447*150812a8SEvalZero __IM uint32_t RESERVED4[5]; 1448*150812a8SEvalZero __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1449*150812a8SEvalZero __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1450*150812a8SEvalZero double transitions */ 1451*150812a8SEvalZero __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1452*150812a8SEvalZero or RDCLRDBL task */ 1453*150812a8SEvalZero } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1454*150812a8SEvalZero 1455*150812a8SEvalZero 1456*150812a8SEvalZero 1457*150812a8SEvalZero /* =========================================================================================================================== */ 1458*150812a8SEvalZero /* ================ COMP ================ */ 1459*150812a8SEvalZero /* =========================================================================================================================== */ 1460*150812a8SEvalZero 1461*150812a8SEvalZero 1462*150812a8SEvalZero /** 1463*150812a8SEvalZero * @brief Comparator (COMP) 1464*150812a8SEvalZero */ 1465*150812a8SEvalZero 1466*150812a8SEvalZero typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1467*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1468*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1469*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1470*150812a8SEvalZero __IM uint32_t RESERVED[61]; 1471*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1472*150812a8SEvalZero __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1473*150812a8SEvalZero __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1474*150812a8SEvalZero __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1475*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 1476*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1477*150812a8SEvalZero __IM uint32_t RESERVED2[63]; 1478*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1479*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1480*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1481*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1482*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1483*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1484*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1485*150812a8SEvalZero __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1486*150812a8SEvalZero __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1487*150812a8SEvalZero __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1488*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 1489*150812a8SEvalZero __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1490*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1491*150812a8SEvalZero __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1492*150812a8SEvalZero } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 1493*150812a8SEvalZero 1494*150812a8SEvalZero 1495*150812a8SEvalZero 1496*150812a8SEvalZero /* =========================================================================================================================== */ 1497*150812a8SEvalZero /* ================ EGU0 ================ */ 1498*150812a8SEvalZero /* =========================================================================================================================== */ 1499*150812a8SEvalZero 1500*150812a8SEvalZero 1501*150812a8SEvalZero /** 1502*150812a8SEvalZero * @brief Event Generator Unit 0 (EGU0) 1503*150812a8SEvalZero */ 1504*150812a8SEvalZero 1505*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1506*150812a8SEvalZero __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering 1507*150812a8SEvalZero the corresponding TRIGGERED[n] event */ 1508*150812a8SEvalZero __IM uint32_t RESERVED[48]; 1509*150812a8SEvalZero __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated 1510*150812a8SEvalZero by triggering the corresponding TRIGGER[n] 1511*150812a8SEvalZero task */ 1512*150812a8SEvalZero __IM uint32_t RESERVED1[112]; 1513*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1514*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1515*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1516*150812a8SEvalZero } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1517*150812a8SEvalZero 1518*150812a8SEvalZero 1519*150812a8SEvalZero 1520*150812a8SEvalZero /* =========================================================================================================================== */ 1521*150812a8SEvalZero /* ================ SWI0 ================ */ 1522*150812a8SEvalZero /* =========================================================================================================================== */ 1523*150812a8SEvalZero 1524*150812a8SEvalZero 1525*150812a8SEvalZero /** 1526*150812a8SEvalZero * @brief Software interrupt 0 (SWI0) 1527*150812a8SEvalZero */ 1528*150812a8SEvalZero 1529*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1530*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1531*150812a8SEvalZero } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1532*150812a8SEvalZero 1533*150812a8SEvalZero 1534*150812a8SEvalZero 1535*150812a8SEvalZero /* =========================================================================================================================== */ 1536*150812a8SEvalZero /* ================ PWM0 ================ */ 1537*150812a8SEvalZero /* =========================================================================================================================== */ 1538*150812a8SEvalZero 1539*150812a8SEvalZero 1540*150812a8SEvalZero /** 1541*150812a8SEvalZero * @brief Pulse width modulation unit (PWM0) 1542*150812a8SEvalZero */ 1543*150812a8SEvalZero 1544*150812a8SEvalZero typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1545*150812a8SEvalZero __IM uint32_t RESERVED; 1546*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1547*150812a8SEvalZero the end of current PWM period, and stops 1548*150812a8SEvalZero sequence playback */ 1549*150812a8SEvalZero __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM 1550*150812a8SEvalZero value on all enabled channels from sequence 1551*150812a8SEvalZero n, and starts playing that sequence at the 1552*150812a8SEvalZero rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1553*150812a8SEvalZero Causes PWM generation to start if not running. */ 1554*150812a8SEvalZero __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1555*150812a8SEvalZero all enabled channels if DECODER.MODE=NextStep. 1556*150812a8SEvalZero Does not cause PWM generation to start if 1557*150812a8SEvalZero not running. */ 1558*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 1559*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1560*150812a8SEvalZero are no longer generated */ 1561*150812a8SEvalZero __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started 1562*150812a8SEvalZero on sequence n */ 1563*150812a8SEvalZero __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of 1564*150812a8SEvalZero every sequence n, when last value from RAM 1565*150812a8SEvalZero has been applied to wave counter */ 1566*150812a8SEvalZero __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1567*150812a8SEvalZero __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1568*150812a8SEvalZero of times defined in LOOP.CNT */ 1569*150812a8SEvalZero __IM uint32_t RESERVED2[56]; 1570*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1571*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 1572*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1573*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1574*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1575*150812a8SEvalZero __IM uint32_t RESERVED4[125]; 1576*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1577*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1578*150812a8SEvalZero __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1579*150812a8SEvalZero counts */ 1580*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1581*150812a8SEvalZero __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1582*150812a8SEvalZero __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1583*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 1584*150812a8SEvalZero __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1585*150812a8SEvalZero __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1586*150812a8SEvalZero } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1587*150812a8SEvalZero 1588*150812a8SEvalZero 1589*150812a8SEvalZero 1590*150812a8SEvalZero /* =========================================================================================================================== */ 1591*150812a8SEvalZero /* ================ PDM ================ */ 1592*150812a8SEvalZero /* =========================================================================================================================== */ 1593*150812a8SEvalZero 1594*150812a8SEvalZero 1595*150812a8SEvalZero /** 1596*150812a8SEvalZero * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 1597*150812a8SEvalZero */ 1598*150812a8SEvalZero 1599*150812a8SEvalZero typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 1600*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1601*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1602*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1603*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1604*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1605*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1606*150812a8SEvalZero by SAMPLE.MAXCNT (or the last sample after 1607*150812a8SEvalZero a STOP task has been received) to Data RAM */ 1608*150812a8SEvalZero __IM uint32_t RESERVED1[125]; 1609*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1610*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1611*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1612*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 1613*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1614*150812a8SEvalZero __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1615*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1616*150812a8SEvalZero signals */ 1617*150812a8SEvalZero __IM uint32_t RESERVED3[3]; 1618*150812a8SEvalZero __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1619*150812a8SEvalZero __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1620*150812a8SEvalZero __IM uint32_t RESERVED4[8]; 1621*150812a8SEvalZero __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1622*150812a8SEvalZero __IM uint32_t RESERVED5[6]; 1623*150812a8SEvalZero __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1624*150812a8SEvalZero } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1625*150812a8SEvalZero 1626*150812a8SEvalZero 1627*150812a8SEvalZero 1628*150812a8SEvalZero /* =========================================================================================================================== */ 1629*150812a8SEvalZero /* ================ NVMC ================ */ 1630*150812a8SEvalZero /* =========================================================================================================================== */ 1631*150812a8SEvalZero 1632*150812a8SEvalZero 1633*150812a8SEvalZero /** 1634*150812a8SEvalZero * @brief Non-volatile memory controller (NVMC) 1635*150812a8SEvalZero */ 1636*150812a8SEvalZero 1637*150812a8SEvalZero typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1638*150812a8SEvalZero __IM uint32_t RESERVED[256]; 1639*150812a8SEvalZero __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1640*150812a8SEvalZero __IM uint32_t RESERVED1[64]; 1641*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1642*150812a8SEvalZero 1643*150812a8SEvalZero union { 1644*150812a8SEvalZero __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1645*150812a8SEvalZero __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1646*150812a8SEvalZero page in code area. Equivalent to ERASEPAGE. */ 1647*150812a8SEvalZero }; 1648*150812a8SEvalZero __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1649*150812a8SEvalZero __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1650*150812a8SEvalZero page in code area. Equivalent to ERASEPAGE. */ 1651*150812a8SEvalZero __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1652*150812a8SEvalZero registers */ 1653*150812a8SEvalZero __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1654*150812a8SEvalZero area */ 1655*150812a8SEvalZero __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1656*150812a8SEvalZero } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1657*150812a8SEvalZero 1658*150812a8SEvalZero 1659*150812a8SEvalZero 1660*150812a8SEvalZero /* =========================================================================================================================== */ 1661*150812a8SEvalZero /* ================ PPI ================ */ 1662*150812a8SEvalZero /* =========================================================================================================================== */ 1663*150812a8SEvalZero 1664*150812a8SEvalZero 1665*150812a8SEvalZero /** 1666*150812a8SEvalZero * @brief Programmable Peripheral Interconnect (PPI) 1667*150812a8SEvalZero */ 1668*150812a8SEvalZero 1669*150812a8SEvalZero typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1670*150812a8SEvalZero __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1671*150812a8SEvalZero __IM uint32_t RESERVED[308]; 1672*150812a8SEvalZero __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1673*150812a8SEvalZero __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1674*150812a8SEvalZero __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1675*150812a8SEvalZero __IM uint32_t RESERVED1; 1676*150812a8SEvalZero __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 1677*150812a8SEvalZero __IM uint32_t RESERVED2[148]; 1678*150812a8SEvalZero __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ 1679*150812a8SEvalZero __IM uint32_t RESERVED3[62]; 1680*150812a8SEvalZero __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1681*150812a8SEvalZero } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1682*150812a8SEvalZero 1683*150812a8SEvalZero 1684*150812a8SEvalZero 1685*150812a8SEvalZero /* =========================================================================================================================== */ 1686*150812a8SEvalZero /* ================ P0 ================ */ 1687*150812a8SEvalZero /* =========================================================================================================================== */ 1688*150812a8SEvalZero 1689*150812a8SEvalZero 1690*150812a8SEvalZero /** 1691*150812a8SEvalZero * @brief GPIO Port (P0) 1692*150812a8SEvalZero */ 1693*150812a8SEvalZero 1694*150812a8SEvalZero typedef struct { /*!< (@ 0x50000000) P0 Structure */ 1695*150812a8SEvalZero __IM uint32_t RESERVED[321]; 1696*150812a8SEvalZero __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 1697*150812a8SEvalZero __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 1698*150812a8SEvalZero __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 1699*150812a8SEvalZero __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 1700*150812a8SEvalZero __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 1701*150812a8SEvalZero __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 1702*150812a8SEvalZero __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 1703*150812a8SEvalZero __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 1704*150812a8SEvalZero have met the criteria set in the PIN_CNF[n].SENSE 1705*150812a8SEvalZero registers */ 1706*150812a8SEvalZero __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 1707*150812a8SEvalZero and LDETECT mode */ 1708*150812a8SEvalZero __IM uint32_t RESERVED1[118]; 1709*150812a8SEvalZero __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO 1710*150812a8SEvalZero pins */ 1711*150812a8SEvalZero } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1712*150812a8SEvalZero 1713*150812a8SEvalZero 1714*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripherals */ 1715*150812a8SEvalZero 1716*150812a8SEvalZero 1717*150812a8SEvalZero /* =========================================================================================================================== */ 1718*150812a8SEvalZero /* ================ Device Specific Peripheral Address Map ================ */ 1719*150812a8SEvalZero /* =========================================================================================================================== */ 1720*150812a8SEvalZero 1721*150812a8SEvalZero 1722*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripheralAddr 1723*150812a8SEvalZero * @{ 1724*150812a8SEvalZero */ 1725*150812a8SEvalZero 1726*150812a8SEvalZero #define NRF_FICR_BASE 0x10000000UL 1727*150812a8SEvalZero #define NRF_UICR_BASE 0x10001000UL 1728*150812a8SEvalZero #define NRF_BPROT_BASE 0x40000000UL 1729*150812a8SEvalZero #define NRF_CLOCK_BASE 0x40000000UL 1730*150812a8SEvalZero #define NRF_POWER_BASE 0x40000000UL 1731*150812a8SEvalZero #define NRF_RADIO_BASE 0x40001000UL 1732*150812a8SEvalZero #define NRF_UARTE0_BASE 0x40002000UL 1733*150812a8SEvalZero #define NRF_TWIM0_BASE 0x40003000UL 1734*150812a8SEvalZero #define NRF_TWIS0_BASE 0x40003000UL 1735*150812a8SEvalZero #define NRF_SPIM0_BASE 0x40004000UL 1736*150812a8SEvalZero #define NRF_SPIS0_BASE 0x40004000UL 1737*150812a8SEvalZero #define NRF_GPIOTE_BASE 0x40006000UL 1738*150812a8SEvalZero #define NRF_SAADC_BASE 0x40007000UL 1739*150812a8SEvalZero #define NRF_TIMER0_BASE 0x40008000UL 1740*150812a8SEvalZero #define NRF_TIMER1_BASE 0x40009000UL 1741*150812a8SEvalZero #define NRF_TIMER2_BASE 0x4000A000UL 1742*150812a8SEvalZero #define NRF_RTC0_BASE 0x4000B000UL 1743*150812a8SEvalZero #define NRF_TEMP_BASE 0x4000C000UL 1744*150812a8SEvalZero #define NRF_RNG_BASE 0x4000D000UL 1745*150812a8SEvalZero #define NRF_ECB_BASE 0x4000E000UL 1746*150812a8SEvalZero #define NRF_AAR_BASE 0x4000F000UL 1747*150812a8SEvalZero #define NRF_CCM_BASE 0x4000F000UL 1748*150812a8SEvalZero #define NRF_WDT_BASE 0x40010000UL 1749*150812a8SEvalZero #define NRF_RTC1_BASE 0x40011000UL 1750*150812a8SEvalZero #define NRF_QDEC_BASE 0x40012000UL 1751*150812a8SEvalZero #define NRF_COMP_BASE 0x40013000UL 1752*150812a8SEvalZero #define NRF_EGU0_BASE 0x40014000UL 1753*150812a8SEvalZero #define NRF_SWI0_BASE 0x40014000UL 1754*150812a8SEvalZero #define NRF_EGU1_BASE 0x40015000UL 1755*150812a8SEvalZero #define NRF_SWI1_BASE 0x40015000UL 1756*150812a8SEvalZero #define NRF_SWI2_BASE 0x40016000UL 1757*150812a8SEvalZero #define NRF_SWI3_BASE 0x40017000UL 1758*150812a8SEvalZero #define NRF_SWI4_BASE 0x40018000UL 1759*150812a8SEvalZero #define NRF_SWI5_BASE 0x40019000UL 1760*150812a8SEvalZero #define NRF_PWM0_BASE 0x4001C000UL 1761*150812a8SEvalZero #define NRF_PDM_BASE 0x4001D000UL 1762*150812a8SEvalZero #define NRF_NVMC_BASE 0x4001E000UL 1763*150812a8SEvalZero #define NRF_PPI_BASE 0x4001F000UL 1764*150812a8SEvalZero #define NRF_P0_BASE 0x50000000UL 1765*150812a8SEvalZero 1766*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1767*150812a8SEvalZero 1768*150812a8SEvalZero 1769*150812a8SEvalZero /* =========================================================================================================================== */ 1770*150812a8SEvalZero /* ================ Peripheral declaration ================ */ 1771*150812a8SEvalZero /* =========================================================================================================================== */ 1772*150812a8SEvalZero 1773*150812a8SEvalZero 1774*150812a8SEvalZero /** @addtogroup Device_Peripheral_declaration 1775*150812a8SEvalZero * @{ 1776*150812a8SEvalZero */ 1777*150812a8SEvalZero 1778*150812a8SEvalZero #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1779*150812a8SEvalZero #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1780*150812a8SEvalZero #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 1781*150812a8SEvalZero #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1782*150812a8SEvalZero #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1783*150812a8SEvalZero #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1784*150812a8SEvalZero #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 1785*150812a8SEvalZero #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 1786*150812a8SEvalZero #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 1787*150812a8SEvalZero #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 1788*150812a8SEvalZero #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 1789*150812a8SEvalZero #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1790*150812a8SEvalZero #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 1791*150812a8SEvalZero #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1792*150812a8SEvalZero #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1793*150812a8SEvalZero #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1794*150812a8SEvalZero #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1795*150812a8SEvalZero #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1796*150812a8SEvalZero #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1797*150812a8SEvalZero #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1798*150812a8SEvalZero #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1799*150812a8SEvalZero #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1800*150812a8SEvalZero #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1801*150812a8SEvalZero #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1802*150812a8SEvalZero #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1803*150812a8SEvalZero #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 1804*150812a8SEvalZero #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 1805*150812a8SEvalZero #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 1806*150812a8SEvalZero #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 1807*150812a8SEvalZero #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 1808*150812a8SEvalZero #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 1809*150812a8SEvalZero #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 1810*150812a8SEvalZero #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 1811*150812a8SEvalZero #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 1812*150812a8SEvalZero #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 1813*150812a8SEvalZero #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 1814*150812a8SEvalZero #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1815*150812a8SEvalZero #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1816*150812a8SEvalZero #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 1817*150812a8SEvalZero 1818*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_declaration */ 1819*150812a8SEvalZero 1820*150812a8SEvalZero 1821*150812a8SEvalZero /* ========================================= End of section using anonymous unions ========================================= */ 1822*150812a8SEvalZero #if defined (__CC_ARM) 1823*150812a8SEvalZero #pragma pop 1824*150812a8SEvalZero #elif defined (__ICCARM__) 1825*150812a8SEvalZero /* leave anonymous unions enabled */ 1826*150812a8SEvalZero #elif (__ARMCC_VERSION >= 6010050) 1827*150812a8SEvalZero #pragma clang diagnostic pop 1828*150812a8SEvalZero #elif defined (__GNUC__) 1829*150812a8SEvalZero /* anonymous unions are enabled by default */ 1830*150812a8SEvalZero #elif defined (__TMS470__) 1831*150812a8SEvalZero /* anonymous unions are enabled by default */ 1832*150812a8SEvalZero #elif defined (__TASKING__) 1833*150812a8SEvalZero #pragma warning restore 1834*150812a8SEvalZero #elif defined (__CSMC__) 1835*150812a8SEvalZero /* anonymous unions are enabled by default */ 1836*150812a8SEvalZero #endif 1837*150812a8SEvalZero 1838*150812a8SEvalZero 1839*150812a8SEvalZero #ifdef __cplusplus 1840*150812a8SEvalZero } 1841*150812a8SEvalZero #endif 1842*150812a8SEvalZero 1843*150812a8SEvalZero #endif /* NRF52810_H */ 1844*150812a8SEvalZero 1845*150812a8SEvalZero 1846*150812a8SEvalZero /** @} */ /* End of group nrf52810 */ 1847*150812a8SEvalZero 1848*150812a8SEvalZero /** @} */ /* End of group Nordic Semiconductor */ 1849