1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf52.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 03. December 2018 34 * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35 * from File 'nrf52.svd', 36 * last modified on Monday, 03.12.2018 10:18:20 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf52 47 * @{ 48 */ 49 50 51 #ifndef NRF52_H 52 #define NRF52_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83 /* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ 84 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85 RADIO_IRQn = 1, /*!< 1 RADIO */ 86 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 88 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 89 NFCT_IRQn = 5, /*!< 5 NFCT */ 90 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 91 SAADC_IRQn = 7, /*!< 7 SAADC */ 92 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95 RTC0_IRQn = 11, /*!< 11 RTC0 */ 96 TEMP_IRQn = 12, /*!< 12 TEMP */ 97 RNG_IRQn = 13, /*!< 13 RNG */ 98 ECB_IRQn = 14, /*!< 14 ECB */ 99 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100 WDT_IRQn = 16, /*!< 16 WDT */ 101 RTC1_IRQn = 17, /*!< 17 RTC1 */ 102 QDEC_IRQn = 18, /*!< 18 QDEC */ 103 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 104 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 112 PWM0_IRQn = 28, /*!< 28 PWM0 */ 113 PDM_IRQn = 29, /*!< 29 PDM */ 114 MWU_IRQn = 32, /*!< 32 MWU */ 115 PWM1_IRQn = 33, /*!< 33 PWM1 */ 116 PWM2_IRQn = 34, /*!< 34 PWM2 */ 117 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 118 RTC2_IRQn = 36, /*!< 36 RTC2 */ 119 I2S_IRQn = 37, /*!< 37 I2S */ 120 FPU_IRQn = 38 /*!< 38 FPU */ 121 } IRQn_Type; 122 123 124 125 /* =========================================================================================================================== */ 126 /* ================ Processor and Core Peripheral Section ================ */ 127 /* =========================================================================================================================== */ 128 129 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 130 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 131 #define __DSP_PRESENT 0 /*!< DSP present or not */ 132 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 133 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 134 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 135 #define __MPU_PRESENT 1 /*!< MPU present or not */ 136 #define __FPU_PRESENT 1 /*!< FPU present or not */ 137 138 139 /** @} */ /* End of group Configuration_of_CMSIS */ 140 141 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 142 #include "system_nrf52.h" /*!< nrf52 System */ 143 144 #ifndef __IM /*!< Fallback for older CMSIS versions */ 145 #define __IM __I 146 #endif 147 #ifndef __OM /*!< Fallback for older CMSIS versions */ 148 #define __OM __O 149 #endif 150 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 151 #define __IOM __IO 152 #endif 153 154 155 /* ======================================== Start of section using anonymous unions ======================================== */ 156 #if defined (__CC_ARM) 157 #pragma push 158 #pragma anon_unions 159 #elif defined (__ICCARM__) 160 #pragma language=extended 161 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 162 #pragma clang diagnostic push 163 #pragma clang diagnostic ignored "-Wc11-extensions" 164 #pragma clang diagnostic ignored "-Wreserved-id-macro" 165 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 166 #pragma clang diagnostic ignored "-Wnested-anon-types" 167 #elif defined (__GNUC__) 168 /* anonymous unions are enabled by default */ 169 #elif defined (__TMS470__) 170 /* anonymous unions are enabled by default */ 171 #elif defined (__TASKING__) 172 #pragma warning 586 173 #elif defined (__CSMC__) 174 /* anonymous unions are enabled by default */ 175 #else 176 #warning Not supported compiler type 177 #endif 178 179 180 /* =========================================================================================================================== */ 181 /* ================ Device Specific Cluster Section ================ */ 182 /* =========================================================================================================================== */ 183 184 185 /** @addtogroup Device_Peripheral_clusters 186 * @{ 187 */ 188 189 190 /** 191 * @brief FICR_INFO [INFO] (Device info) 192 */ 193 typedef struct { 194 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 195 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production 196 configuration */ 197 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 198 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 199 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 200 __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ 201 } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 202 203 204 /** 205 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 206 */ 207 typedef struct { 208 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ 209 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ 210 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ 211 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ 212 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ 213 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ 214 __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ 215 __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ 216 __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ 217 __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ 218 __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ 219 __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ 220 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ 221 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ 222 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ 223 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ 224 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ 225 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 226 227 228 /** 229 * @brief FICR_NFC [NFC] (Unspecified) 230 */ 231 typedef struct { 232 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 233 these values to populate NFCID1_3RD_LAST, 234 NFCID1_2ND_LAST and NFCID1_LAST. */ 235 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 236 these values to populate NFCID1_3RD_LAST, 237 NFCID1_2ND_LAST and NFCID1_LAST. */ 238 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 239 these values to populate NFCID1_3RD_LAST, 240 NFCID1_2ND_LAST and NFCID1_LAST. */ 241 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 242 these values to populate NFCID1_3RD_LAST, 243 NFCID1_2ND_LAST and NFCID1_LAST. */ 244 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 245 246 247 /** 248 * @brief POWER_RAM [RAM] (Unspecified) 249 */ 250 typedef struct { 251 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ 252 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set 253 register */ 254 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear 255 register */ 256 __IM uint32_t RESERVED; 257 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 258 259 260 /** 261 * @brief UARTE_PSEL [PSEL] (Unspecified) 262 */ 263 typedef struct { 264 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 265 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 266 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 267 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 268 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 269 270 271 /** 272 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 273 */ 274 typedef struct { 275 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 276 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 277 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 278 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 279 280 281 /** 282 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 283 */ 284 typedef struct { 285 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 286 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 287 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 288 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 289 290 291 /** 292 * @brief SPIM_PSEL [PSEL] (Unspecified) 293 */ 294 typedef struct { 295 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 296 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 297 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 298 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 299 300 301 /** 302 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 303 */ 304 typedef struct { 305 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 306 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 307 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 308 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 309 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 310 311 312 /** 313 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 314 */ 315 typedef struct { 316 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 317 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 318 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 319 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 320 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 321 322 323 /** 324 * @brief SPIS_PSEL [PSEL] (Unspecified) 325 */ 326 typedef struct { 327 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 328 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 329 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 330 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 331 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 332 333 334 /** 335 * @brief SPIS_RXD [RXD] (Unspecified) 336 */ 337 typedef struct { 338 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 339 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 340 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 341 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 342 343 344 /** 345 * @brief SPIS_TXD [TXD] (Unspecified) 346 */ 347 typedef struct { 348 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 349 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 350 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 351 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 352 353 354 /** 355 * @brief TWIM_PSEL [PSEL] (Unspecified) 356 */ 357 typedef struct { 358 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 359 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 360 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 361 362 363 /** 364 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 365 */ 366 typedef struct { 367 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 368 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 369 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 370 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 371 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 372 373 374 /** 375 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 376 */ 377 typedef struct { 378 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 379 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 380 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 381 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 382 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 383 384 385 /** 386 * @brief TWIS_PSEL [PSEL] (Unspecified) 387 */ 388 typedef struct { 389 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 390 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 391 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 392 393 394 /** 395 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 396 */ 397 typedef struct { 398 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 399 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 400 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 401 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 402 403 404 /** 405 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 406 */ 407 typedef struct { 408 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 409 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 410 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 411 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 412 413 414 /** 415 * @brief SPI_PSEL [PSEL] (Unspecified) 416 */ 417 typedef struct { 418 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 419 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ 420 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ 421 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 422 423 424 /** 425 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 426 */ 427 typedef struct { 428 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ 429 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 430 431 432 /** 433 * @brief NFCT_TXD [TXD] (Unspecified) 434 */ 435 typedef struct { 436 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 437 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 438 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 439 440 441 /** 442 * @brief NFCT_RXD [RXD] (Unspecified) 443 */ 444 typedef struct { 445 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 446 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 447 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 448 449 450 /** 451 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 452 */ 453 typedef struct { 454 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal 455 or above CH[0].LIMIT.HIGH */ 456 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal 457 or below CH[0].LIMIT.LOW */ 458 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 459 460 461 /** 462 * @brief SAADC_CH [CH] (Unspecified) 463 */ 464 typedef struct { 465 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection 466 for CH[0] */ 467 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection 468 for CH[0] */ 469 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for 470 CH[0] */ 471 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event 472 monitoring a channel */ 473 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 474 475 476 /** 477 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 478 */ 479 typedef struct { 480 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 481 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 482 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 483 START */ 484 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 485 486 487 /** 488 * @brief QDEC_PSEL [PSEL] (Unspecified) 489 */ 490 typedef struct { 491 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 492 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 493 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 494 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 495 496 497 /** 498 * @brief PWM_SEQ [SEQ] (Unspecified) 499 */ 500 typedef struct { 501 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in 502 Data RAM of this sequence */ 503 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty 504 cycles) in this sequence */ 505 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional 506 PWM periods between samples loaded into 507 compare register */ 508 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the 509 sequence */ 510 __IM uint32_t RESERVED[4]; 511 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 512 513 514 /** 515 * @brief PWM_PSEL [PSEL] (Unspecified) 516 */ 517 typedef struct { 518 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select 519 for PWM channel 0 */ 520 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 521 522 523 /** 524 * @brief PDM_PSEL [PSEL] (Unspecified) 525 */ 526 typedef struct { 527 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 528 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 529 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 530 531 532 /** 533 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 534 */ 535 typedef struct { 536 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 537 EasyDMA */ 538 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 539 mode */ 540 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 541 542 543 /** 544 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 545 */ 546 typedef struct { 547 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group 548 0 */ 549 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group 550 0 */ 551 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 552 553 554 /** 555 * @brief PPI_CH [CH] (PPI Channel) 556 */ 557 typedef struct { 558 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ 559 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ 560 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 561 562 563 /** 564 * @brief PPI_FORK [FORK] (Fork) 565 */ 566 typedef struct { 567 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ 568 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 569 570 571 /** 572 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) 573 */ 574 typedef struct { 575 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region 576 0 detected */ 577 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region 578 0 detected */ 579 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 580 581 582 /** 583 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) 584 */ 585 typedef struct { 586 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral 587 region 0 detected */ 588 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral 589 region 0 detected */ 590 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 591 592 593 /** 594 * @brief MWU_PERREGION [PERREGION] (Unspecified) 595 */ 596 typedef struct { 597 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt 598 in region 0, write access detected while 599 corresponding subregion was enabled for 600 watching */ 601 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt 602 in region 0, read access detected while 603 corresponding subregion was enabled for 604 watching */ 605 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 606 607 608 /** 609 * @brief MWU_REGION [REGION] (Unspecified) 610 */ 611 typedef struct { 612 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region 613 0 */ 614 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region 615 0 */ 616 __IM uint32_t RESERVED[2]; 617 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 618 619 620 /** 621 * @brief MWU_PREGION [PREGION] (Unspecified) 622 */ 623 typedef struct { 624 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ 625 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ 626 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region 627 0 */ 628 __IM uint32_t RESERVED; 629 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 630 631 632 /** 633 * @brief I2S_CONFIG [CONFIG] (Unspecified) 634 */ 635 typedef struct { 636 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 637 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 638 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 639 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 640 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 641 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 642 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 643 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 644 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 645 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 646 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 647 648 649 /** 650 * @brief I2S_RXD [RXD] (Unspecified) 651 */ 652 typedef struct { 653 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 654 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 655 656 657 /** 658 * @brief I2S_TXD [TXD] (Unspecified) 659 */ 660 typedef struct { 661 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 662 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 663 664 665 /** 666 * @brief I2S_RXTXD [RXTXD] (Unspecified) 667 */ 668 typedef struct { 669 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 670 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 671 672 673 /** 674 * @brief I2S_PSEL [PSEL] (Unspecified) 675 */ 676 typedef struct { 677 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 678 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 679 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 680 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 681 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 682 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 683 684 685 /** @} */ /* End of group Device_Peripheral_clusters */ 686 687 688 /* =========================================================================================================================== */ 689 /* ================ Device Specific Peripheral Section ================ */ 690 /* =========================================================================================================================== */ 691 692 693 /** @addtogroup Device_Peripheral_peripherals 694 * @{ 695 */ 696 697 698 699 /* =========================================================================================================================== */ 700 /* ================ FICR ================ */ 701 /* =========================================================================================================================== */ 702 703 704 /** 705 * @brief Factory Information Configuration Registers (FICR) 706 */ 707 708 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 709 __IM uint32_t RESERVED[4]; 710 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 711 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 712 __IM uint32_t RESERVED1[18]; 713 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ 714 __IM uint32_t RESERVED2[6]; 715 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word 716 0 */ 717 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word 718 0 */ 719 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 720 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ 721 __IM uint32_t RESERVED3[21]; 722 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 723 __IM uint32_t RESERVED4[185]; 724 __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 725 coefficients */ 726 __IM uint32_t RESERVED5[2]; 727 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 728 } NRF_FICR_Type; /*!< Size = 1120 (0x460) */ 729 730 731 732 /* =========================================================================================================================== */ 733 /* ================ UICR ================ */ 734 /* =========================================================================================================================== */ 735 736 737 /** 738 * @brief User Information Configuration Registers (UICR) 739 */ 740 741 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 742 __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 743 __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 744 __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 745 __IM uint32_t RESERVED; 746 __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 747 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic 748 firmware design */ 749 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic 750 hardware design */ 751 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ 752 __IM uint32_t RESERVED1[64]; 753 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET 754 function (see POWER chapter for details) */ 755 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ 756 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 757 NFC antenna or GPIO */ 758 } NRF_UICR_Type; /*!< Size = 528 (0x210) */ 759 760 761 762 /* =========================================================================================================================== */ 763 /* ================ BPROT ================ */ 764 /* =========================================================================================================================== */ 765 766 767 /** 768 * @brief Block Protect (BPROT) 769 */ 770 771 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 772 __IM uint32_t RESERVED[384]; 773 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 774 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 775 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface 776 mode */ 777 __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ 778 __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ 779 __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ 780 } NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ 781 782 783 784 /* =========================================================================================================================== */ 785 /* ================ POWER ================ */ 786 /* =========================================================================================================================== */ 787 788 789 /** 790 * @brief Power control (POWER) 791 */ 792 793 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 794 __IM uint32_t RESERVED[30]; 795 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 796 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 797 __IM uint32_t RESERVED1[34]; 798 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 799 __IM uint32_t RESERVED2[2]; 800 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 801 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 802 __IM uint32_t RESERVED3[122]; 803 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 804 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 805 __IM uint32_t RESERVED4[61]; 806 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 807 __IM uint32_t RESERVED5[9]; 808 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 809 __IM uint32_t RESERVED6[53]; 810 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 811 __IM uint32_t RESERVED7[3]; 812 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 813 __IM uint32_t RESERVED8[2]; 814 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 815 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 816 __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this 817 register is retained) */ 818 __IM uint32_t RESERVED9[11]; 819 __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this 820 register is retained) */ 821 __IM uint32_t RESERVED10[8]; 822 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 823 __IM uint32_t RESERVED11[225]; 824 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 825 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 826 827 828 829 /* =========================================================================================================================== */ 830 /* ================ CLOCK ================ */ 831 /* =========================================================================================================================== */ 832 833 834 /** 835 * @brief Clock control (CLOCK) 836 */ 837 838 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 839 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 840 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 841 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 842 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 843 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 844 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 845 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 846 __IM uint32_t RESERVED[57]; 847 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 848 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 849 __IM uint32_t RESERVED1; 850 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 851 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 852 __IM uint32_t RESERVED2[124]; 853 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 854 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 855 __IM uint32_t RESERVED3[63]; 856 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 857 triggered */ 858 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 859 __IM uint32_t RESERVED4; 860 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 861 triggered */ 862 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 863 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 864 task was triggered */ 865 __IM uint32_t RESERVED5[62]; 866 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 867 __IM uint32_t RESERVED6[7]; 868 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 869 __IM uint32_t RESERVED7[8]; 870 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ 871 } NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ 872 873 874 875 /* =========================================================================================================================== */ 876 /* ================ RADIO ================ */ 877 /* =========================================================================================================================== */ 878 879 880 /** 881 * @brief 2.4 GHz Radio (RADIO) 882 */ 883 884 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 885 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 886 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 887 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 888 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 889 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 890 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 891 the receive signal strength. */ 892 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 893 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 894 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 895 __IM uint32_t RESERVED[55]; 896 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 897 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 898 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 899 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 900 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 901 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 902 packet */ 903 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 904 received packet */ 905 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 906 __IM uint32_t RESERVED1[2]; 907 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 908 __IM uint32_t RESERVED2; 909 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 910 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 911 __IM uint32_t RESERVED3[50]; 912 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 913 __IM uint32_t RESERVED4[64]; 914 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 915 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 916 __IM uint32_t RESERVED5[61]; 917 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 918 __IM uint32_t RESERVED6; 919 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 920 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 921 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 922 __IM uint32_t RESERVED7[60]; 923 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 924 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 925 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 926 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 927 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 928 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 929 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 930 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 931 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 932 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 933 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 934 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 935 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 936 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 937 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 938 __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ 939 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 940 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 941 __IM uint32_t RESERVED8; 942 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 943 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 944 __IM uint32_t RESERVED9[2]; 945 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 946 __IM uint32_t RESERVED10[39]; 947 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base 948 segment 0 */ 949 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix 950 0 */ 951 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 952 __IM uint32_t RESERVED11[3]; 953 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 954 __IM uint32_t RESERVED12[618]; 955 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 956 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 957 958 959 960 /* =========================================================================================================================== */ 961 /* ================ UARTE0 ================ */ 962 /* =========================================================================================================================== */ 963 964 965 /** 966 * @brief UART with EasyDMA (UARTE0) 967 */ 968 969 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 970 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 971 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 972 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 973 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 974 __IM uint32_t RESERVED[7]; 975 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 976 __IM uint32_t RESERVED1[52]; 977 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 978 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 979 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 980 transferred to Data RAM) */ 981 __IM uint32_t RESERVED2; 982 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 983 __IM uint32_t RESERVED3[2]; 984 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 985 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 986 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 987 __IM uint32_t RESERVED4[7]; 988 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 989 __IM uint32_t RESERVED5; 990 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 991 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 992 __IM uint32_t RESERVED6; 993 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 994 __IM uint32_t RESERVED7[41]; 995 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 996 __IM uint32_t RESERVED8[63]; 997 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 998 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 999 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1000 __IM uint32_t RESERVED9[93]; 1001 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1002 __IM uint32_t RESERVED10[31]; 1003 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1004 __IM uint32_t RESERVED11; 1005 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1006 __IM uint32_t RESERVED12[3]; 1007 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1008 selected. */ 1009 __IM uint32_t RESERVED13[3]; 1010 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1011 __IM uint32_t RESERVED14; 1012 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1013 __IM uint32_t RESERVED15[7]; 1014 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1015 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1016 1017 1018 1019 /* =========================================================================================================================== */ 1020 /* ================ UART0 ================ */ 1021 /* =========================================================================================================================== */ 1022 1023 1024 /** 1025 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1026 */ 1027 1028 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1029 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1030 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1031 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1032 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1033 __IM uint32_t RESERVED[3]; 1034 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1035 __IM uint32_t RESERVED1[56]; 1036 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1037 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1038 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1039 __IM uint32_t RESERVED2[4]; 1040 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1041 __IM uint32_t RESERVED3; 1042 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1043 __IM uint32_t RESERVED4[7]; 1044 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1045 __IM uint32_t RESERVED5[46]; 1046 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1047 __IM uint32_t RESERVED6[64]; 1048 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1049 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1050 __IM uint32_t RESERVED7[93]; 1051 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1052 __IM uint32_t RESERVED8[31]; 1053 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1054 __IM uint32_t RESERVED9; 1055 __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ 1056 __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ 1057 __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ 1058 __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ 1059 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1060 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1061 __IM uint32_t RESERVED10; 1062 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ 1063 __IM uint32_t RESERVED11[17]; 1064 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1065 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1066 1067 1068 1069 /* =========================================================================================================================== */ 1070 /* ================ SPIM0 ================ */ 1071 /* =========================================================================================================================== */ 1072 1073 1074 /** 1075 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1076 */ 1077 1078 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1079 __IM uint32_t RESERVED[4]; 1080 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1081 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1082 __IM uint32_t RESERVED1; 1083 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1084 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1085 __IM uint32_t RESERVED2[56]; 1086 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1087 __IM uint32_t RESERVED3[2]; 1088 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1089 __IM uint32_t RESERVED4; 1090 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1091 __IM uint32_t RESERVED5; 1092 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1093 __IM uint32_t RESERVED6[10]; 1094 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1095 __IM uint32_t RESERVED7[44]; 1096 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1097 __IM uint32_t RESERVED8[64]; 1098 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1099 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1100 __IM uint32_t RESERVED9[125]; 1101 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1102 __IM uint32_t RESERVED10; 1103 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1104 __IM uint32_t RESERVED11[4]; 1105 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1106 source selected. */ 1107 __IM uint32_t RESERVED12[3]; 1108 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1109 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1110 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1111 __IM uint32_t RESERVED13[26]; 1112 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1113 case and over-read of the TXD buffer. */ 1114 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1115 1116 1117 1118 /* =========================================================================================================================== */ 1119 /* ================ SPIS0 ================ */ 1120 /* =========================================================================================================================== */ 1121 1122 1123 /** 1124 * @brief SPI Slave 0 (SPIS0) 1125 */ 1126 1127 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1128 __IM uint32_t RESERVED[9]; 1129 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1130 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1131 to acquire it */ 1132 __IM uint32_t RESERVED1[54]; 1133 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1134 __IM uint32_t RESERVED2[2]; 1135 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1136 __IM uint32_t RESERVED3[5]; 1137 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1138 __IM uint32_t RESERVED4[53]; 1139 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1140 __IM uint32_t RESERVED5[64]; 1141 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1142 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1143 __IM uint32_t RESERVED6[61]; 1144 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1145 __IM uint32_t RESERVED7[15]; 1146 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1147 __IM uint32_t RESERVED8[47]; 1148 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1149 __IM uint32_t RESERVED9; 1150 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1151 __IM uint32_t RESERVED10[7]; 1152 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1153 __IM uint32_t RESERVED11; 1154 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1155 __IM uint32_t RESERVED12; 1156 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1157 __IM uint32_t RESERVED13; 1158 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1159 of an ignored transaction. */ 1160 __IM uint32_t RESERVED14[24]; 1161 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1162 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1163 1164 1165 1166 /* =========================================================================================================================== */ 1167 /* ================ TWIM0 ================ */ 1168 /* =========================================================================================================================== */ 1169 1170 1171 /** 1172 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1173 */ 1174 1175 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1176 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1177 __IM uint32_t RESERVED; 1178 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1179 __IM uint32_t RESERVED1[2]; 1180 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1181 TWI master is not suspended. */ 1182 __IM uint32_t RESERVED2; 1183 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1184 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1185 __IM uint32_t RESERVED3[56]; 1186 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1187 __IM uint32_t RESERVED4[7]; 1188 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1189 __IM uint32_t RESERVED5[8]; 1190 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1191 task has been issued, TWI traffic is now 1192 suspended. */ 1193 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1194 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1195 __IM uint32_t RESERVED6[2]; 1196 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1197 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1198 byte */ 1199 __IM uint32_t RESERVED7[39]; 1200 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1201 __IM uint32_t RESERVED8[63]; 1202 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1203 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1204 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1205 __IM uint32_t RESERVED9[110]; 1206 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1207 __IM uint32_t RESERVED10[14]; 1208 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1209 __IM uint32_t RESERVED11; 1210 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1211 __IM uint32_t RESERVED12[5]; 1212 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1213 __IM uint32_t RESERVED13[3]; 1214 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1215 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1216 __IM uint32_t RESERVED14[13]; 1217 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1218 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1219 1220 1221 1222 /* =========================================================================================================================== */ 1223 /* ================ TWIS0 ================ */ 1224 /* =========================================================================================================================== */ 1225 1226 1227 /** 1228 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1229 */ 1230 1231 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1232 __IM uint32_t RESERVED[5]; 1233 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1234 __IM uint32_t RESERVED1; 1235 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1236 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1237 __IM uint32_t RESERVED2[3]; 1238 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1239 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1240 __IM uint32_t RESERVED3[51]; 1241 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1242 __IM uint32_t RESERVED4[7]; 1243 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1244 __IM uint32_t RESERVED5[9]; 1245 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1246 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1247 __IM uint32_t RESERVED6[4]; 1248 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1249 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1250 __IM uint32_t RESERVED7[37]; 1251 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1252 __IM uint32_t RESERVED8[63]; 1253 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1254 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1255 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1256 __IM uint32_t RESERVED9[113]; 1257 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1258 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1259 a match */ 1260 __IM uint32_t RESERVED10[10]; 1261 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1262 __IM uint32_t RESERVED11; 1263 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1264 __IM uint32_t RESERVED12[9]; 1265 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1266 __IM uint32_t RESERVED13; 1267 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1268 __IM uint32_t RESERVED14[14]; 1269 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address 1270 0 */ 1271 __IM uint32_t RESERVED15; 1272 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1273 mechanism */ 1274 __IM uint32_t RESERVED16[10]; 1275 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1276 of an over-read of the transmit buffer. */ 1277 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1278 1279 1280 1281 /* =========================================================================================================================== */ 1282 /* ================ SPI0 ================ */ 1283 /* =========================================================================================================================== */ 1284 1285 1286 /** 1287 * @brief Serial Peripheral Interface 0 (SPI0) 1288 */ 1289 1290 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1291 __IM uint32_t RESERVED[66]; 1292 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1293 __IM uint32_t RESERVED1[126]; 1294 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1295 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1296 __IM uint32_t RESERVED2[125]; 1297 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1298 __IM uint32_t RESERVED3; 1299 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1300 __IM uint32_t RESERVED4; 1301 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1302 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1303 __IM uint32_t RESERVED5; 1304 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 1305 __IM uint32_t RESERVED6[11]; 1306 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1307 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1308 1309 1310 1311 /* =========================================================================================================================== */ 1312 /* ================ TWI0 ================ */ 1313 /* =========================================================================================================================== */ 1314 1315 1316 /** 1317 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1318 */ 1319 1320 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1321 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1322 __IM uint32_t RESERVED; 1323 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1324 __IM uint32_t RESERVED1[2]; 1325 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1326 __IM uint32_t RESERVED2; 1327 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1328 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1329 __IM uint32_t RESERVED3[56]; 1330 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1331 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1332 __IM uint32_t RESERVED4[4]; 1333 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1334 __IM uint32_t RESERVED5; 1335 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1336 __IM uint32_t RESERVED6[4]; 1337 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1338 that is sent or received */ 1339 __IM uint32_t RESERVED7[3]; 1340 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1341 __IM uint32_t RESERVED8[45]; 1342 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1343 __IM uint32_t RESERVED9[64]; 1344 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1345 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1346 __IM uint32_t RESERVED10[110]; 1347 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1348 __IM uint32_t RESERVED11[14]; 1349 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1350 __IM uint32_t RESERVED12; 1351 __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ 1352 __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ 1353 __IM uint32_t RESERVED13[2]; 1354 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1355 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1356 __IM uint32_t RESERVED14; 1357 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1358 __IM uint32_t RESERVED15[24]; 1359 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1360 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1361 1362 1363 1364 /* =========================================================================================================================== */ 1365 /* ================ NFCT ================ */ 1366 /* =========================================================================================================================== */ 1367 1368 1369 /** 1370 * @brief NFC-A compatible radio (NFCT) 1371 */ 1372 1373 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1374 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing 1375 frames, change state to activated */ 1376 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ 1377 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1378 sense mode */ 1379 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change 1380 state to transmit */ 1381 __IM uint32_t RESERVED[3]; 1382 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1383 __IM uint32_t RESERVED1; 1384 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1385 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1386 __IM uint32_t RESERVED2[53]; 1387 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send 1388 frames */ 1389 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1390 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1391 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1392 frame */ 1393 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1394 symbol of a frame */ 1395 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1396 frame */ 1397 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) 1398 and transferred to RAM, and EasyDMA has 1399 ended accessing the RX buffer */ 1400 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1401 contains details on the source of the error. */ 1402 __IM uint32_t RESERVED3[2]; 1403 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1404 register contains details on the source 1405 of the error. */ 1406 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1407 in Data RAM full. */ 1408 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1409 has ended accessing the TX buffer */ 1410 __IM uint32_t RESERVED4; 1411 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1412 __IM uint32_t RESERVED5[3]; 1413 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ 1414 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ 1415 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1416 __IM uint32_t RESERVED6[43]; 1417 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1418 __IM uint32_t RESERVED7[63]; 1419 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1420 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1421 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1422 __IM uint32_t RESERVED8[62]; 1423 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1424 __IM uint32_t RESERVED9; 1425 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1426 __IM uint32_t RESERVED10[8]; 1427 __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ 1428 __IM uint32_t RESERVED11[2]; 1429 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1430 __IM uint32_t RESERVED12[49]; 1431 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1432 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1433 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1434 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1435 Data RAM */ 1436 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage 1437 buffer in Data RAM */ 1438 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1439 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1440 __IM uint32_t RESERVED13[26]; 1441 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1442 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1443 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1444 __IM uint32_t RESERVED14; 1445 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1446 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1447 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1448 1449 1450 1451 /* =========================================================================================================================== */ 1452 /* ================ GPIOTE ================ */ 1453 /* =========================================================================================================================== */ 1454 1455 1456 /** 1457 * @brief GPIO Tasks and Events (GPIOTE) 1458 */ 1459 1460 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1461 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to 1462 pin specified in CONFIG[0].PSEL. Action 1463 on pin is configured in CONFIG[0].POLARITY. */ 1464 __IM uint32_t RESERVED[4]; 1465 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to 1466 pin specified in CONFIG[0].PSEL. Action 1467 on pin is to set it high. */ 1468 __IM uint32_t RESERVED1[4]; 1469 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to 1470 pin specified in CONFIG[0].PSEL. Action 1471 on pin is to set it low. */ 1472 __IM uint32_t RESERVED2[32]; 1473 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from 1474 pin specified in CONFIG[0].PSEL */ 1475 __IM uint32_t RESERVED3[23]; 1476 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1477 with SENSE mechanism enabled */ 1478 __IM uint32_t RESERVED4[97]; 1479 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1480 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1481 __IM uint32_t RESERVED5[129]; 1482 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for 1483 OUT[n], SET[n] and CLR[n] tasks and IN[n] 1484 event */ 1485 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1486 1487 1488 1489 /* =========================================================================================================================== */ 1490 /* ================ SAADC ================ */ 1491 /* =========================================================================================================================== */ 1492 1493 1494 /** 1495 * @brief Analog to Digital Converter (SAADC) 1496 */ 1497 1498 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1499 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1500 RAM */ 1501 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1502 are sampled */ 1503 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1504 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1505 __IM uint32_t RESERVED[60]; 1506 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1507 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1508 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1509 on the mode, multiple conversions might 1510 be needed for a result to be transferred 1511 to RAM. */ 1512 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1513 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1514 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1515 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1516 __IM uint32_t RESERVED1[106]; 1517 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1518 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1519 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1520 __IM uint32_t RESERVED2[61]; 1521 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1522 __IM uint32_t RESERVED3[63]; 1523 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1524 __IM uint32_t RESERVED4[3]; 1525 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1526 __IM uint32_t RESERVED5[24]; 1527 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1528 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1529 not be combined with SCAN. The RESOLUTION 1530 is applied before averaging, thus for high 1531 OVERSAMPLE a higher RESOLUTION should be 1532 used. */ 1533 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1534 __IM uint32_t RESERVED6[12]; 1535 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1536 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1537 1538 1539 1540 /* =========================================================================================================================== */ 1541 /* ================ TIMER0 ================ */ 1542 /* =========================================================================================================================== */ 1543 1544 1545 /** 1546 * @brief Timer/Counter 0 (TIMER0) 1547 */ 1548 1549 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1550 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1551 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1552 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1553 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1554 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1555 __IM uint32_t RESERVED[11]; 1556 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value 1557 to CC[0] register */ 1558 __IM uint32_t RESERVED1[58]; 1559 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] 1560 match */ 1561 __IM uint32_t RESERVED2[42]; 1562 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1563 __IM uint32_t RESERVED3[64]; 1564 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1565 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1566 __IM uint32_t RESERVED4[126]; 1567 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1568 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1569 __IM uint32_t RESERVED5; 1570 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1571 __IM uint32_t RESERVED6[11]; 1572 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register 1573 0 */ 1574 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1575 1576 1577 1578 /* =========================================================================================================================== */ 1579 /* ================ RTC0 ================ */ 1580 /* =========================================================================================================================== */ 1581 1582 1583 /** 1584 * @brief Real time counter 0 (RTC0) 1585 */ 1586 1587 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1588 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1589 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1590 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1591 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1592 __IM uint32_t RESERVED[60]; 1593 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1594 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1595 __IM uint32_t RESERVED1[14]; 1596 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] 1597 match */ 1598 __IM uint32_t RESERVED2[109]; 1599 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1600 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1601 __IM uint32_t RESERVED3[13]; 1602 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1603 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1604 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1605 __IM uint32_t RESERVED4[110]; 1606 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1607 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1608 t be written when RTC is stopped */ 1609 __IM uint32_t RESERVED5[13]; 1610 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ 1611 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1612 1613 1614 1615 /* =========================================================================================================================== */ 1616 /* ================ TEMP ================ */ 1617 /* =========================================================================================================================== */ 1618 1619 1620 /** 1621 * @brief Temperature Sensor (TEMP) 1622 */ 1623 1624 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1625 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1626 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1627 __IM uint32_t RESERVED[62]; 1628 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1629 __IM uint32_t RESERVED1[128]; 1630 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1631 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1632 __IM uint32_t RESERVED2[127]; 1633 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1634 __IM uint32_t RESERVED3[5]; 1635 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1636 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1637 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1638 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1639 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1640 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1641 __IM uint32_t RESERVED4[2]; 1642 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1643 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1644 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1645 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1646 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1647 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1648 __IM uint32_t RESERVED5[2]; 1649 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1650 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1651 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1652 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1653 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1654 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1655 1656 1657 1658 /* =========================================================================================================================== */ 1659 /* ================ RNG ================ */ 1660 /* =========================================================================================================================== */ 1661 1662 1663 /** 1664 * @brief Random Number Generator (RNG) 1665 */ 1666 1667 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1668 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1669 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1670 __IM uint32_t RESERVED[62]; 1671 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1672 written to the VALUE register */ 1673 __IM uint32_t RESERVED1[63]; 1674 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1675 __IM uint32_t RESERVED2[64]; 1676 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1677 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1678 __IM uint32_t RESERVED3[126]; 1679 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1680 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1681 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1682 1683 1684 1685 /* =========================================================================================================================== */ 1686 /* ================ ECB ================ */ 1687 /* =========================================================================================================================== */ 1688 1689 1690 /** 1691 * @brief AES ECB Mode Encryption (ECB) 1692 */ 1693 1694 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1695 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1696 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1697 __IM uint32_t RESERVED[62]; 1698 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1699 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1700 task or due to an error */ 1701 __IM uint32_t RESERVED1[127]; 1702 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1703 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1704 __IM uint32_t RESERVED2[126]; 1705 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1706 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1707 1708 1709 1710 /* =========================================================================================================================== */ 1711 /* ================ CCM ================ */ 1712 /* =========================================================================================================================== */ 1713 1714 1715 /** 1716 * @brief AES CCM Mode Encryption (CCM) 1717 */ 1718 1719 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1720 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1721 will stop by itself when completed. */ 1722 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1723 stop by itself when completed. */ 1724 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1725 __IM uint32_t RESERVED[61]; 1726 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1727 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1728 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ 1729 __IM uint32_t RESERVED1[61]; 1730 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1731 __IM uint32_t RESERVED2[64]; 1732 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1733 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1734 __IM uint32_t RESERVED3[61]; 1735 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1736 __IM uint32_t RESERVED4[63]; 1737 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1738 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1739 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1740 NONCE vector */ 1741 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1742 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1743 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1744 } NRF_CCM_Type; /*!< Size = 1304 (0x518) */ 1745 1746 1747 1748 /* =========================================================================================================================== */ 1749 /* ================ AAR ================ */ 1750 /* =========================================================================================================================== */ 1751 1752 1753 /** 1754 * @brief Accelerated Address Resolver (AAR) 1755 */ 1756 1757 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1758 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1759 in the IRK data structure */ 1760 __IM uint32_t RESERVED; 1761 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1762 __IM uint32_t RESERVED1[61]; 1763 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1764 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1765 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1766 __IM uint32_t RESERVED2[126]; 1767 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1768 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1769 __IM uint32_t RESERVED3[61]; 1770 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1771 __IM uint32_t RESERVED4[63]; 1772 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1773 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1774 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1775 __IM uint32_t RESERVED5; 1776 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1777 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1778 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1779 1780 1781 1782 /* =========================================================================================================================== */ 1783 /* ================ WDT ================ */ 1784 /* =========================================================================================================================== */ 1785 1786 1787 /** 1788 * @brief Watchdog Timer (WDT) 1789 */ 1790 1791 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1792 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1793 __IM uint32_t RESERVED[63]; 1794 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1795 __IM uint32_t RESERVED1[128]; 1796 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1797 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1798 __IM uint32_t RESERVED2[61]; 1799 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1800 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1801 __IM uint32_t RESERVED3[63]; 1802 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1803 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1804 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1805 __IM uint32_t RESERVED4[60]; 1806 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ 1807 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1808 1809 1810 1811 /* =========================================================================================================================== */ 1812 /* ================ QDEC ================ */ 1813 /* =========================================================================================================================== */ 1814 1815 1816 /** 1817 * @brief Quadrature Decoder (QDEC) 1818 */ 1819 1820 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1821 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1822 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1823 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1824 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1825 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1826 __IM uint32_t RESERVED[59]; 1827 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1828 written to the SAMPLE register */ 1829 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1830 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1831 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1832 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1833 __IM uint32_t RESERVED1[59]; 1834 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1835 __IM uint32_t RESERVED2[64]; 1836 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1837 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1838 __IM uint32_t RESERVED3[125]; 1839 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1840 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1841 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1842 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1843 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1844 and DBLRDY events can be generated */ 1845 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1846 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1847 READCLRACC or RDCLRACC task */ 1848 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1849 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1850 __IM uint32_t RESERVED4[5]; 1851 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1852 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1853 double transitions */ 1854 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1855 or RDCLRDBL task */ 1856 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1857 1858 1859 1860 /* =========================================================================================================================== */ 1861 /* ================ COMP ================ */ 1862 /* =========================================================================================================================== */ 1863 1864 1865 /** 1866 * @brief Comparator (COMP) 1867 */ 1868 1869 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1870 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1871 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1872 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1873 __IM uint32_t RESERVED[61]; 1874 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1875 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1876 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1877 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1878 __IM uint32_t RESERVED1[60]; 1879 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1880 __IM uint32_t RESERVED2[63]; 1881 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1882 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1883 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1884 __IM uint32_t RESERVED3[61]; 1885 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1886 __IM uint32_t RESERVED4[63]; 1887 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1888 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1889 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1890 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1891 __IM uint32_t RESERVED5[8]; 1892 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1893 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1894 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1895 __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ 1896 } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ 1897 1898 1899 1900 /* =========================================================================================================================== */ 1901 /* ================ LPCOMP ================ */ 1902 /* =========================================================================================================================== */ 1903 1904 1905 /** 1906 * @brief Low Power Comparator (LPCOMP) 1907 */ 1908 1909 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 1910 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1911 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1912 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1913 __IM uint32_t RESERVED[61]; 1914 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 1915 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1916 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1917 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1918 __IM uint32_t RESERVED1[60]; 1919 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1920 __IM uint32_t RESERVED2[64]; 1921 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1922 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1923 __IM uint32_t RESERVED3[61]; 1924 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1925 __IM uint32_t RESERVED4[63]; 1926 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 1927 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 1928 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 1929 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1930 __IM uint32_t RESERVED5[4]; 1931 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 1932 __IM uint32_t RESERVED6[5]; 1933 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1934 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 1935 1936 1937 1938 /* =========================================================================================================================== */ 1939 /* ================ SWI0 ================ */ 1940 /* =========================================================================================================================== */ 1941 1942 1943 /** 1944 * @brief Software interrupt 0 (SWI0) 1945 */ 1946 1947 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1948 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1949 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1950 1951 1952 1953 /* =========================================================================================================================== */ 1954 /* ================ EGU0 ================ */ 1955 /* =========================================================================================================================== */ 1956 1957 1958 /** 1959 * @brief Event Generator Unit 0 (EGU0) 1960 */ 1961 1962 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1963 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering 1964 the corresponding TRIGGERED[0] event */ 1965 __IM uint32_t RESERVED[48]; 1966 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated 1967 by triggering the corresponding TRIGGER[0] 1968 task */ 1969 __IM uint32_t RESERVED1[112]; 1970 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1971 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1972 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1973 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1974 1975 1976 1977 /* =========================================================================================================================== */ 1978 /* ================ PWM0 ================ */ 1979 /* =========================================================================================================================== */ 1980 1981 1982 /** 1983 * @brief Pulse Width Modulation Unit 0 (PWM0) 1984 */ 1985 1986 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1987 __IM uint32_t RESERVED; 1988 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1989 the end of current PWM period, and stops 1990 sequence playback */ 1991 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM 1992 value on all enabled channels from sequence 1993 0, and starts playing that sequence at the 1994 rate defined in SEQ[0]REFRESH and/or DECODER.MODE. 1995 Causes PWM generation to start it was not 1996 running. */ 1997 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1998 all enabled channels if DECODER.MODE=NextStep. 1999 Does not cause PWM generation to start it 2000 was not running. */ 2001 __IM uint32_t RESERVED1[60]; 2002 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2003 are no longer generated */ 2004 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started 2005 on sequence 0 */ 2006 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of 2007 every sequence 0, when last value from RAM 2008 has been applied to wave counter */ 2009 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2010 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2011 of times defined in LOOP.CNT */ 2012 __IM uint32_t RESERVED2[56]; 2013 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2014 __IM uint32_t RESERVED3[63]; 2015 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2016 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2017 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2018 __IM uint32_t RESERVED4[125]; 2019 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2020 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2021 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2022 counts */ 2023 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2024 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2025 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ 2026 __IM uint32_t RESERVED5[2]; 2027 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2028 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2029 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2030 2031 2032 2033 /* =========================================================================================================================== */ 2034 /* ================ PDM ================ */ 2035 /* =========================================================================================================================== */ 2036 2037 2038 /** 2039 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2040 */ 2041 2042 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2043 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2044 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2045 __IM uint32_t RESERVED[62]; 2046 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2047 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2048 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2049 by SAMPLE.MAXCNT (or the last sample after 2050 a STOP task has been received) to Data RAM */ 2051 __IM uint32_t RESERVED1[125]; 2052 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2053 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2054 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2055 __IM uint32_t RESERVED2[125]; 2056 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2057 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2058 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2059 signals */ 2060 __IM uint32_t RESERVED3[3]; 2061 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2062 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2063 __IM uint32_t RESERVED4[8]; 2064 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2065 __IM uint32_t RESERVED5[6]; 2066 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2067 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2068 2069 2070 2071 /* =========================================================================================================================== */ 2072 /* ================ NVMC ================ */ 2073 /* =========================================================================================================================== */ 2074 2075 2076 /** 2077 * @brief Non Volatile Memory Controller (NVMC) 2078 */ 2079 2080 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2081 __IM uint32_t RESERVED[256]; 2082 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2083 __IM uint32_t RESERVED1[64]; 2084 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2085 2086 union { 2087 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ 2088 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2089 page in Code area. Equivalent to ERASEPAGE. */ 2090 }; 2091 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2092 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2093 page in Code area. Equivalent to ERASEPAGE. */ 2094 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration 2095 Registers */ 2096 __IM uint32_t RESERVED2[10]; 2097 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ 2098 __IM uint32_t RESERVED3; 2099 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ 2100 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ 2101 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2102 2103 2104 2105 /* =========================================================================================================================== */ 2106 /* ================ PPI ================ */ 2107 /* =========================================================================================================================== */ 2108 2109 2110 /** 2111 * @brief Programmable Peripheral Interconnect (PPI) 2112 */ 2113 2114 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2115 __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2116 __IM uint32_t RESERVED[308]; 2117 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2118 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2119 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2120 __IM uint32_t RESERVED1; 2121 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2122 __IM uint32_t RESERVED2[148]; 2123 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ 2124 __IM uint32_t RESERVED3[62]; 2125 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2126 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2127 2128 2129 2130 /* =========================================================================================================================== */ 2131 /* ================ MWU ================ */ 2132 /* =========================================================================================================================== */ 2133 2134 2135 /** 2136 * @brief Memory Watch Unit (MWU) 2137 */ 2138 2139 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2140 __IM uint32_t RESERVED[64]; 2141 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ 2142 __IM uint32_t RESERVED1[16]; 2143 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ 2144 __IM uint32_t RESERVED2[100]; 2145 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2146 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2147 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2148 __IM uint32_t RESERVED3[5]; 2149 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ 2150 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ 2151 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ 2152 __IM uint32_t RESERVED4[53]; 2153 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2154 __IM uint32_t RESERVED5[64]; 2155 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2156 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2157 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2158 __IM uint32_t RESERVED6[57]; 2159 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2160 __IM uint32_t RESERVED7[32]; 2161 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2162 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2163 2164 2165 2166 /* =========================================================================================================================== */ 2167 /* ================ I2S ================ */ 2168 /* =========================================================================================================================== */ 2169 2170 2171 /** 2172 * @brief Inter-IC Sound (I2S) 2173 */ 2174 2175 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2176 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2177 generator when this is enabled. */ 2178 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2179 Triggering this task will cause the {event:STOPPED} 2180 event to be generated. */ 2181 __IM uint32_t RESERVED[63]; 2182 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2183 double-buffers. When the I2S module is started 2184 and RX is enabled, this event will be generated 2185 for every RXTXD.MAXCNT words that are received 2186 on the SDIN pin. */ 2187 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2188 __IM uint32_t RESERVED1[2]; 2189 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2190 double-buffers. When the I2S module is started 2191 and TX is enabled, this event will be generated 2192 for every RXTXD.MAXCNT words that are sent 2193 on the SDOUT pin. */ 2194 __IM uint32_t RESERVED2[122]; 2195 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2196 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2197 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2198 __IM uint32_t RESERVED3[125]; 2199 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2200 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2201 __IM uint32_t RESERVED4[3]; 2202 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2203 __IM uint32_t RESERVED5; 2204 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2205 __IM uint32_t RESERVED6[3]; 2206 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2207 __IM uint32_t RESERVED7[3]; 2208 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2209 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2210 2211 2212 2213 /* =========================================================================================================================== */ 2214 /* ================ FPU ================ */ 2215 /* =========================================================================================================================== */ 2216 2217 2218 /** 2219 * @brief FPU (FPU) 2220 */ 2221 2222 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2223 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2224 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2225 2226 2227 2228 /* =========================================================================================================================== */ 2229 /* ================ P0 ================ */ 2230 /* =========================================================================================================================== */ 2231 2232 2233 /** 2234 * @brief GPIO Port 1 (P0) 2235 */ 2236 2237 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 2238 __IM uint32_t RESERVED[321]; 2239 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 2240 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 2241 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 2242 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 2243 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 2244 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 2245 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 2246 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 2247 have met the criteria set in the PIN_CNF[n].SENSE 2248 registers */ 2249 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 2250 and LDETECT mode */ 2251 __IM uint32_t RESERVED1[118]; 2252 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO 2253 pins */ 2254 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 2255 2256 2257 /** @} */ /* End of group Device_Peripheral_peripherals */ 2258 2259 2260 /* =========================================================================================================================== */ 2261 /* ================ Device Specific Peripheral Address Map ================ */ 2262 /* =========================================================================================================================== */ 2263 2264 2265 /** @addtogroup Device_Peripheral_peripheralAddr 2266 * @{ 2267 */ 2268 2269 #define NRF_FICR_BASE 0x10000000UL 2270 #define NRF_UICR_BASE 0x10001000UL 2271 #define NRF_BPROT_BASE 0x40000000UL 2272 #define NRF_POWER_BASE 0x40000000UL 2273 #define NRF_CLOCK_BASE 0x40000000UL 2274 #define NRF_RADIO_BASE 0x40001000UL 2275 #define NRF_UARTE0_BASE 0x40002000UL 2276 #define NRF_UART0_BASE 0x40002000UL 2277 #define NRF_SPIM0_BASE 0x40003000UL 2278 #define NRF_SPIS0_BASE 0x40003000UL 2279 #define NRF_TWIM0_BASE 0x40003000UL 2280 #define NRF_TWIS0_BASE 0x40003000UL 2281 #define NRF_SPI0_BASE 0x40003000UL 2282 #define NRF_TWI0_BASE 0x40003000UL 2283 #define NRF_SPIM1_BASE 0x40004000UL 2284 #define NRF_SPIS1_BASE 0x40004000UL 2285 #define NRF_TWIM1_BASE 0x40004000UL 2286 #define NRF_TWIS1_BASE 0x40004000UL 2287 #define NRF_SPI1_BASE 0x40004000UL 2288 #define NRF_TWI1_BASE 0x40004000UL 2289 #define NRF_NFCT_BASE 0x40005000UL 2290 #define NRF_GPIOTE_BASE 0x40006000UL 2291 #define NRF_SAADC_BASE 0x40007000UL 2292 #define NRF_TIMER0_BASE 0x40008000UL 2293 #define NRF_TIMER1_BASE 0x40009000UL 2294 #define NRF_TIMER2_BASE 0x4000A000UL 2295 #define NRF_RTC0_BASE 0x4000B000UL 2296 #define NRF_TEMP_BASE 0x4000C000UL 2297 #define NRF_RNG_BASE 0x4000D000UL 2298 #define NRF_ECB_BASE 0x4000E000UL 2299 #define NRF_CCM_BASE 0x4000F000UL 2300 #define NRF_AAR_BASE 0x4000F000UL 2301 #define NRF_WDT_BASE 0x40010000UL 2302 #define NRF_RTC1_BASE 0x40011000UL 2303 #define NRF_QDEC_BASE 0x40012000UL 2304 #define NRF_COMP_BASE 0x40013000UL 2305 #define NRF_LPCOMP_BASE 0x40013000UL 2306 #define NRF_SWI0_BASE 0x40014000UL 2307 #define NRF_EGU0_BASE 0x40014000UL 2308 #define NRF_SWI1_BASE 0x40015000UL 2309 #define NRF_EGU1_BASE 0x40015000UL 2310 #define NRF_SWI2_BASE 0x40016000UL 2311 #define NRF_EGU2_BASE 0x40016000UL 2312 #define NRF_SWI3_BASE 0x40017000UL 2313 #define NRF_EGU3_BASE 0x40017000UL 2314 #define NRF_SWI4_BASE 0x40018000UL 2315 #define NRF_EGU4_BASE 0x40018000UL 2316 #define NRF_SWI5_BASE 0x40019000UL 2317 #define NRF_EGU5_BASE 0x40019000UL 2318 #define NRF_TIMER3_BASE 0x4001A000UL 2319 #define NRF_TIMER4_BASE 0x4001B000UL 2320 #define NRF_PWM0_BASE 0x4001C000UL 2321 #define NRF_PDM_BASE 0x4001D000UL 2322 #define NRF_NVMC_BASE 0x4001E000UL 2323 #define NRF_PPI_BASE 0x4001F000UL 2324 #define NRF_MWU_BASE 0x40020000UL 2325 #define NRF_PWM1_BASE 0x40021000UL 2326 #define NRF_PWM2_BASE 0x40022000UL 2327 #define NRF_SPIM2_BASE 0x40023000UL 2328 #define NRF_SPIS2_BASE 0x40023000UL 2329 #define NRF_SPI2_BASE 0x40023000UL 2330 #define NRF_RTC2_BASE 0x40024000UL 2331 #define NRF_I2S_BASE 0x40025000UL 2332 #define NRF_FPU_BASE 0x40026000UL 2333 #define NRF_P0_BASE 0x50000000UL 2334 2335 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2336 2337 2338 /* =========================================================================================================================== */ 2339 /* ================ Peripheral declaration ================ */ 2340 /* =========================================================================================================================== */ 2341 2342 2343 /** @addtogroup Device_Peripheral_declaration 2344 * @{ 2345 */ 2346 2347 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2348 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2349 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 2350 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2351 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2352 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2353 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2354 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2355 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2356 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2357 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2358 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2359 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2360 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2361 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2362 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2363 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2364 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2365 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2366 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2367 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2368 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2369 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2370 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2371 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2372 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2373 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2374 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2375 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2376 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2377 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2378 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2379 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2380 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2381 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2382 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2383 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2384 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2385 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2386 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2387 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2388 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2389 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2390 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2391 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2392 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2393 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2394 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2395 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2396 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2397 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2398 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2399 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2400 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2401 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2402 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2403 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2404 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2405 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2406 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2407 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2408 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2409 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2410 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2411 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2412 2413 /** @} */ /* End of group Device_Peripheral_declaration */ 2414 2415 2416 /* ========================================= End of section using anonymous unions ========================================= */ 2417 #if defined (__CC_ARM) 2418 #pragma pop 2419 #elif defined (__ICCARM__) 2420 /* leave anonymous unions enabled */ 2421 #elif (__ARMCC_VERSION >= 6010050) 2422 #pragma clang diagnostic pop 2423 #elif defined (__GNUC__) 2424 /* anonymous unions are enabled by default */ 2425 #elif defined (__TMS470__) 2426 /* anonymous unions are enabled by default */ 2427 #elif defined (__TASKING__) 2428 #pragma warning restore 2429 #elif defined (__CSMC__) 2430 /* anonymous unions are enabled by default */ 2431 #endif 2432 2433 2434 #ifdef __cplusplus 2435 } 2436 #endif 2437 2438 #endif /* NRF52_H */ 2439 2440 2441 /** @} */ /* End of group nrf52 */ 2442 2443 /** @} */ /* End of group Nordic Semiconductor */ 2444