1 /* 2 3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef NRF51_TO_NRF52_H 34 #define NRF51_TO_NRF52_H 35 36 /*lint ++flb "Enter library region */ 37 38 /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. 39 * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 40 * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros 41 * from the nrf51_deprecated.h file. */ 42 43 44 /* IRQ */ 45 /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 46 #define UART0_IRQHandler UARTE0_UART0_IRQHandler 47 #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 48 #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 49 #define ADC_IRQHandler SAADC_IRQHandler 50 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 51 #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 52 #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 53 #define SWI2_IRQHandler SWI2_EGU2_IRQHandler 54 #define SWI3_IRQHandler SWI3_EGU3_IRQHandler 55 #define SWI4_IRQHandler SWI4_EGU4_IRQHandler 56 #define SWI5_IRQHandler SWI5_EGU5_IRQHandler 57 58 #define UART0_IRQn UARTE0_UART0_IRQn 59 #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 60 #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 61 #define ADC_IRQn SAADC_IRQn 62 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 63 #define SWI0_IRQn SWI0_EGU0_IRQn 64 #define SWI1_IRQn SWI1_EGU1_IRQn 65 #define SWI2_IRQn SWI2_EGU2_IRQn 66 #define SWI3_IRQn SWI3_EGU3_IRQn 67 #define SWI4_IRQn SWI4_EGU4_IRQn 68 #define SWI5_IRQn SWI5_EGU5_IRQn 69 70 71 /* UICR */ 72 /* Register RBPCONF was renamed to APPROTECT. */ 73 #define RBPCONF APPROTECT 74 75 #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 76 #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 77 #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 78 #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 79 80 81 /* GPIO */ 82 /* GPIO port was renamed to P0. */ 83 #define NRF_GPIO NRF_P0 84 #define NRF_GPIO_BASE NRF_P0_BASE 85 86 87 /* QDEC */ 88 /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ 89 #define PSELLED PSEL.LED 90 #define PSELA PSEL.A 91 #define PSELB PSEL.B 92 93 94 /* SPIS */ 95 /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 96 #define PSELSCK PSEL.SCK 97 #define PSELMISO PSEL.MISO 98 #define PSELMOSI PSEL.MOSI 99 #define PSELCSN PSEL.CSN 100 101 /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 102 #define RXDPTR RXD.PTR 103 #define MAXRX RXD.MAXCNT 104 #define AMOUNTRX RXD.AMOUNT 105 106 #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 107 #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 108 109 #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 110 #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 111 112 /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 113 #define TXDPTR TXD.PTR 114 #define MAXTX TXD.MAXCNT 115 #define AMOUNTTX TXD.AMOUNT 116 117 #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 118 #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 119 120 #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 121 #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 122 123 124 /* MPU */ 125 /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ 126 #define NRF_MPU NRF_BPROT 127 128 /* Register DISABLEINDEBUG macros were affected. */ 129 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos 130 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk 131 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled 132 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled 133 134 /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ 135 #define PROTENSET0 CONFIG0 136 #define PROTENSET1 CONFIG1 137 138 #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos 139 #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk 140 #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled 141 #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled 142 #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled 143 144 #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos 145 #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk 146 #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled 147 #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled 148 #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled 149 150 #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos 151 #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk 152 #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled 153 #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled 154 #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled 155 156 #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos 157 #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk 158 #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled 159 #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled 160 #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled 161 162 #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos 163 #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk 164 #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled 165 #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled 166 #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled 167 168 #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos 169 #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk 170 #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled 171 #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled 172 #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled 173 174 #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos 175 #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk 176 #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled 177 #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled 178 #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled 179 180 #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos 181 #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk 182 #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled 183 #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled 184 #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled 185 186 #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos 187 #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk 188 #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled 189 #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled 190 #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled 191 192 #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos 193 #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk 194 #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled 195 #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled 196 #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled 197 198 #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos 199 #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk 200 #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled 201 #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled 202 #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled 203 204 #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos 205 #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk 206 #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled 207 #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled 208 #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled 209 210 #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos 211 #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk 212 #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled 213 #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled 214 #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled 215 216 #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos 217 #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk 218 #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled 219 #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled 220 #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled 221 222 #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos 223 #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk 224 #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled 225 #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled 226 #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled 227 228 #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos 229 #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk 230 #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled 231 #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled 232 #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled 233 234 #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos 235 #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk 236 #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled 237 #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled 238 #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled 239 240 #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos 241 #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk 242 #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled 243 #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled 244 #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled 245 246 #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos 247 #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk 248 #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled 249 #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled 250 #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled 251 252 #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos 253 #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk 254 #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled 255 #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled 256 #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled 257 258 #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos 259 #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk 260 #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled 261 #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled 262 #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled 263 264 #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos 265 #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk 266 #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled 267 #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled 268 #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled 269 270 #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos 271 #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk 272 #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled 273 #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled 274 #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled 275 276 #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos 277 #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk 278 #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled 279 #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled 280 #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled 281 282 #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos 283 #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk 284 #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled 285 #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled 286 #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled 287 288 #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos 289 #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk 290 #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled 291 #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled 292 #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled 293 294 #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos 295 #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk 296 #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled 297 #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled 298 #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled 299 300 #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos 301 #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk 302 #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled 303 #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled 304 #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled 305 306 #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos 307 #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk 308 #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled 309 #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled 310 #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled 311 312 #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos 313 #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk 314 #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled 315 #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled 316 #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled 317 318 #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos 319 #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk 320 #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled 321 #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled 322 #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled 323 324 #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos 325 #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk 326 #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled 327 #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled 328 #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled 329 330 #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos 331 #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk 332 #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled 333 #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled 334 #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled 335 336 #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos 337 #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk 338 #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled 339 #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled 340 #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled 341 342 #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos 343 #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk 344 #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled 345 #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled 346 #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled 347 348 #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos 349 #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk 350 #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled 351 #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled 352 #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled 353 354 #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos 355 #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk 356 #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled 357 #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled 358 #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled 359 360 #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos 361 #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk 362 #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled 363 #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled 364 #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled 365 366 #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos 367 #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk 368 #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled 369 #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled 370 #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled 371 372 #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos 373 #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk 374 #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled 375 #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled 376 #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled 377 378 #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos 379 #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk 380 #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled 381 #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled 382 #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled 383 384 #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos 385 #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk 386 #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled 387 #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled 388 #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled 389 390 #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos 391 #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk 392 #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled 393 #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled 394 #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled 395 396 #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos 397 #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk 398 #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled 399 #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled 400 #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled 401 402 #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos 403 #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk 404 #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled 405 #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled 406 #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled 407 408 #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos 409 #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk 410 #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled 411 #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled 412 #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled 413 414 #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos 415 #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk 416 #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled 417 #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled 418 #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled 419 420 #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos 421 #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk 422 #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled 423 #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled 424 #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled 425 426 #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos 427 #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk 428 #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled 429 #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled 430 #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled 431 432 #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos 433 #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk 434 #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled 435 #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled 436 #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled 437 438 #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos 439 #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk 440 #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled 441 #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled 442 #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled 443 444 #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos 445 #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk 446 #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled 447 #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled 448 #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled 449 450 #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos 451 #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk 452 #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled 453 #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled 454 #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled 455 456 #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos 457 #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk 458 #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled 459 #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled 460 #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled 461 462 #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos 463 #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk 464 #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled 465 #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled 466 #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled 467 468 #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos 469 #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk 470 #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled 471 #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled 472 #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled 473 474 #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos 475 #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk 476 #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled 477 #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled 478 #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled 479 480 #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos 481 #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk 482 #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled 483 #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled 484 #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled 485 486 #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos 487 #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk 488 #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled 489 #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled 490 #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled 491 492 #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos 493 #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk 494 #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled 495 #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled 496 #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled 497 498 #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos 499 #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk 500 #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled 501 #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled 502 #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled 503 504 #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos 505 #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk 506 #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled 507 #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled 508 #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled 509 510 #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos 511 #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk 512 #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled 513 #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled 514 #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled 515 516 #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos 517 #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk 518 #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled 519 #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled 520 #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled 521 522 523 /* From nrf51_deprecated.h */ 524 525 /* NVMC */ 526 /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ 527 #define ERASEPROTECTEDPAGE ERASEPCR0 528 529 530 /* IRQ */ 531 /* COMP module was eliminated. Adapted to nrf52 headers. */ 532 #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler 533 #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn 534 535 536 /* REFSEL register redefined enumerated values and added some more. */ 537 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd 538 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd 539 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd 540 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd 541 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd 542 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd 543 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd 544 545 546 /* RADIO */ 547 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 548 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 549 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 550 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 551 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 552 553 554 /* FICR */ 555 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 556 #define DEVICEID0 DEVICEID[0] 557 #define DEVICEID1 DEVICEID[1] 558 559 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 560 #define ER0 ER[0] 561 #define ER1 ER[1] 562 #define ER2 ER[2] 563 #define ER3 ER[3] 564 565 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 566 #define IR0 IR[0] 567 #define IR1 IR[1] 568 #define IR2 IR[2] 569 #define IR3 IR[3] 570 571 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 572 #define DEVICEADDR0 DEVICEADDR[0] 573 #define DEVICEADDR1 DEVICEADDR[1] 574 575 576 /* PPI */ 577 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 578 #define TASKS_CHG0EN TASKS_CHG[0].EN 579 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 580 #define TASKS_CHG1EN TASKS_CHG[1].EN 581 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 582 #define TASKS_CHG2EN TASKS_CHG[2].EN 583 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 584 #define TASKS_CHG3EN TASKS_CHG[3].EN 585 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 586 587 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 588 #define CH0_EEP CH[0].EEP 589 #define CH0_TEP CH[0].TEP 590 #define CH1_EEP CH[1].EEP 591 #define CH1_TEP CH[1].TEP 592 #define CH2_EEP CH[2].EEP 593 #define CH2_TEP CH[2].TEP 594 #define CH3_EEP CH[3].EEP 595 #define CH3_TEP CH[3].TEP 596 #define CH4_EEP CH[4].EEP 597 #define CH4_TEP CH[4].TEP 598 #define CH5_EEP CH[5].EEP 599 #define CH5_TEP CH[5].TEP 600 #define CH6_EEP CH[6].EEP 601 #define CH6_TEP CH[6].TEP 602 #define CH7_EEP CH[7].EEP 603 #define CH7_TEP CH[7].TEP 604 #define CH8_EEP CH[8].EEP 605 #define CH8_TEP CH[8].TEP 606 #define CH9_EEP CH[9].EEP 607 #define CH9_TEP CH[9].TEP 608 #define CH10_EEP CH[10].EEP 609 #define CH10_TEP CH[10].TEP 610 #define CH11_EEP CH[11].EEP 611 #define CH11_TEP CH[11].TEP 612 #define CH12_EEP CH[12].EEP 613 #define CH12_TEP CH[12].TEP 614 #define CH13_EEP CH[13].EEP 615 #define CH13_TEP CH[13].TEP 616 #define CH14_EEP CH[14].EEP 617 #define CH14_TEP CH[14].TEP 618 #define CH15_EEP CH[15].EEP 619 #define CH15_TEP CH[15].TEP 620 621 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 622 #define CHG0 CHG[0] 623 #define CHG1 CHG[1] 624 #define CHG2 CHG[2] 625 #define CHG3 CHG[3] 626 627 /* All bitfield macros for the CHGx registers therefore changed name. */ 628 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 629 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 630 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 631 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 632 633 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 634 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 635 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 636 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 637 638 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 639 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 640 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 641 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 642 643 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 644 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 645 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 646 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 647 648 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 649 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 650 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 651 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 652 653 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 654 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 655 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 656 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 657 658 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 659 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 660 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 661 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 662 663 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 664 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 665 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 666 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 667 668 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 669 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 670 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 671 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 672 673 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 674 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 675 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 676 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 677 678 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 679 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 680 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 681 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 682 683 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 684 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 685 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 686 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 687 688 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 689 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 690 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 691 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 692 693 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 694 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 695 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 696 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 697 698 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 699 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 700 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 701 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 702 703 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 704 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 705 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 706 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 707 708 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 709 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 710 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 711 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 712 713 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 714 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 715 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 716 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 717 718 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 719 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 720 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 721 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 722 723 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 724 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 725 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 726 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 727 728 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 729 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 730 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 731 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 732 733 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 734 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 735 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 736 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 737 738 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 739 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 740 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 741 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 742 743 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 744 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 745 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 746 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 747 748 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 749 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 750 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 751 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 752 753 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 754 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 755 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 756 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 757 758 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 759 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 760 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 761 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 762 763 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 764 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 765 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 766 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 767 768 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 769 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 770 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 771 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 772 773 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 774 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 775 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 776 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 777 778 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 779 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 780 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 781 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 782 783 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 784 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 785 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 786 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 787 788 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 789 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 790 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 791 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 792 793 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 794 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 795 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 796 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 797 798 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 799 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 800 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 801 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 802 803 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 804 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 805 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 806 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 807 808 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 809 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 810 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 811 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 812 813 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 814 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 815 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 816 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 817 818 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 819 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 820 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 821 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 822 823 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 824 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 825 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 826 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 827 828 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 829 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 830 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 831 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 832 833 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 834 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 835 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 836 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 837 838 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 839 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 840 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 841 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 842 843 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 844 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 845 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 846 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 847 848 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 849 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 850 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 851 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 852 853 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 854 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 855 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 856 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 857 858 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 859 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 860 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 861 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 862 863 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 864 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 865 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 866 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 867 868 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 869 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 870 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 871 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 872 873 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 874 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 875 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 876 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 877 878 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 879 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 880 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 881 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 882 883 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 884 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 885 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 886 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 887 888 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 889 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 890 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 891 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 892 893 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 894 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 895 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 896 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 897 898 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 899 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 900 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 901 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 902 903 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 904 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 905 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 906 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 907 908 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 909 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 910 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 911 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 912 913 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 914 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 915 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 916 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 917 918 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 919 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 920 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 921 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 922 923 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 924 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 925 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 926 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 927 928 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 929 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 930 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 931 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 932 933 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 934 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 935 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 936 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 937 938 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 939 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 940 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 941 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 942 943 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 944 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 945 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 946 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 947 948 949 950 951 /*lint --flb "Leave library region" */ 952 953 #endif /* NRF51_TO_NRF52_H */ 954 955