1 /* 2 3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef __NRF51_BITS_H 34 #define __NRF51_BITS_H 35 36 /*lint ++flb "Enter library region" */ 37 38 /* Peripheral: AAR */ 39 /* Description: Accelerated Address Resolver. */ 40 41 /* Register: AAR_INTENSET */ 42 /* Description: Interrupt enable set register. */ 43 44 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */ 45 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 46 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 48 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 49 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ 50 51 /* Bit 1 : Enable interrupt on RESOLVED event. */ 52 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 53 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 55 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 56 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ 57 58 /* Bit 0 : Enable interrupt on END event. */ 59 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 60 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 62 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 63 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 64 65 /* Register: AAR_INTENCLR */ 66 /* Description: Interrupt enable clear register. */ 67 68 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */ 69 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 70 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 72 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 73 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ 74 75 /* Bit 1 : Disable interrupt on RESOLVED event. */ 76 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 77 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 79 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 80 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ 81 82 /* Bit 0 : Disable interrupt on ENDKSGEN event. */ 83 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 84 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 86 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 87 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 88 89 /* Register: AAR_STATUS */ 90 /* Description: Resolution status. */ 91 92 /* Bits 3..0 : The IRK used last time an address was resolved. */ 93 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 94 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 95 96 /* Register: AAR_ENABLE */ 97 /* Description: Enable AAR. */ 98 99 /* Bits 1..0 : Enable AAR. */ 100 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 101 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 102 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ 103 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ 104 105 /* Register: AAR_NIRK */ 106 /* Description: Number of Identity root Keys in the IRK data structure. */ 107 108 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ 109 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 110 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 111 112 /* Register: AAR_POWER */ 113 /* Description: Peripheral power control. */ 114 115 /* Bit 0 : Peripheral power control. */ 116 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 117 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 118 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 119 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 120 121 122 /* Peripheral: ADC */ 123 /* Description: Analog to digital converter. */ 124 125 /* Register: ADC_INTENSET */ 126 /* Description: Interrupt enable set register. */ 127 128 /* Bit 0 : Enable interrupt on END event. */ 129 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 130 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 131 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 132 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 133 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 134 135 /* Register: ADC_INTENCLR */ 136 /* Description: Interrupt enable clear register. */ 137 138 /* Bit 0 : Disable interrupt on END event. */ 139 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 140 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 141 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 142 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 143 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 144 145 /* Register: ADC_BUSY */ 146 /* Description: ADC busy register. */ 147 148 /* Bit 0 : ADC busy register. */ 149 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ 150 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ 151 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ 152 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ 153 154 /* Register: ADC_ENABLE */ 155 /* Description: ADC enable. */ 156 157 /* Bits 1..0 : ADC enable. */ 158 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 159 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 160 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ 161 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ 162 163 /* Register: ADC_CONFIG */ 164 /* Description: ADC configuration register. */ 165 166 /* Bits 17..16 : ADC external reference pin selection. */ 167 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ 168 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 169 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ 170 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ 171 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ 172 173 /* Bits 15..8 : ADC analog pin selection. */ 174 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 175 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 176 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ 177 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ 178 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ 179 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ 180 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ 181 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ 182 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ 183 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ 184 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ 185 186 /* Bits 6..5 : ADC reference selection. */ 187 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ 188 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 189 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ 190 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ 191 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ 192 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ 193 194 /* Bits 4..2 : ADC input selection. */ 195 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ 196 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ 197 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ 198 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ 199 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ 200 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ 201 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ 202 203 /* Bits 1..0 : ADC resolution. */ 204 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ 205 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ 206 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ 207 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ 208 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ 209 210 /* Register: ADC_RESULT */ 211 /* Description: Result of ADC conversion. */ 212 213 /* Bits 9..0 : Result of ADC conversion. */ 214 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 215 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 216 217 /* Register: ADC_POWER */ 218 /* Description: Peripheral power control. */ 219 220 /* Bit 0 : Peripheral power control. */ 221 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 222 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 223 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 224 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 225 226 227 /* Peripheral: CCM */ 228 /* Description: AES CCM Mode Encryption. */ 229 230 /* Register: CCM_SHORTS */ 231 /* Description: Shortcuts for the CCM. */ 232 233 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ 234 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 235 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 236 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ 237 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ 238 239 /* Register: CCM_INTENSET */ 240 /* Description: Interrupt enable set register. */ 241 242 /* Bit 2 : Enable interrupt on ERROR event. */ 243 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 244 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 245 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 246 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 247 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 248 249 /* Bit 1 : Enable interrupt on ENDCRYPT event. */ 250 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 251 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 252 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ 253 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ 254 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ 255 256 /* Bit 0 : Enable interrupt on ENDKSGEN event. */ 257 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 258 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 259 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ 260 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ 261 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ 262 263 /* Register: CCM_INTENCLR */ 264 /* Description: Interrupt enable clear register. */ 265 266 /* Bit 2 : Disable interrupt on ERROR event. */ 267 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 268 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 269 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 270 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 271 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 272 273 /* Bit 1 : Disable interrupt on ENDCRYPT event. */ 274 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 275 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 276 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ 277 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ 278 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ 279 280 /* Bit 0 : Disable interrupt on ENDKSGEN event. */ 281 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 282 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 283 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ 284 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ 285 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ 286 287 /* Register: CCM_MICSTATUS */ 288 /* Description: CCM RX MIC check result. */ 289 290 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ 291 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 292 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 293 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ 294 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ 295 296 /* Register: CCM_ENABLE */ 297 /* Description: CCM enable. */ 298 299 /* Bits 1..0 : CCM enable. */ 300 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 301 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 302 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ 303 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ 304 305 /* Register: CCM_MODE */ 306 /* Description: Operation mode. */ 307 308 /* Bit 0 : CCM mode operation. */ 309 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 310 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 311 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ 312 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ 313 314 /* Register: CCM_POWER */ 315 /* Description: Peripheral power control. */ 316 317 /* Bit 0 : Peripheral power control. */ 318 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 319 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 320 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 321 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 322 323 324 /* Peripheral: CLOCK */ 325 /* Description: Clock control. */ 326 327 /* Register: CLOCK_INTENSET */ 328 /* Description: Interrupt enable set register. */ 329 330 /* Bit 4 : Enable interrupt on CTTO event. */ 331 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 332 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ 333 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ 334 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ 335 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ 336 337 /* Bit 3 : Enable interrupt on DONE event. */ 338 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ 339 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 340 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ 341 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ 342 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ 343 344 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ 345 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 346 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 347 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 348 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 349 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ 350 351 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ 352 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 353 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 354 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 355 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 356 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ 357 358 /* Register: CLOCK_INTENCLR */ 359 /* Description: Interrupt enable clear register. */ 360 361 /* Bit 4 : Disable interrupt on CTTO event. */ 362 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 363 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ 364 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ 365 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ 366 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ 367 368 /* Bit 3 : Disable interrupt on DONE event. */ 369 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ 370 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 371 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ 372 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ 373 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ 374 375 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ 376 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 377 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 378 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 379 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 380 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ 381 382 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ 383 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 384 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 385 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 386 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 387 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ 388 389 /* Register: CLOCK_HFCLKRUN */ 390 /* Description: Task HFCLKSTART trigger status. */ 391 392 /* Bit 0 : Task HFCLKSTART trigger status. */ 393 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 394 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 395 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ 396 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ 397 398 /* Register: CLOCK_HFCLKSTAT */ 399 /* Description: High frequency clock status. */ 400 401 /* Bit 16 : State for the HFCLK. */ 402 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 403 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 404 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ 405 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ 406 407 /* Bit 0 : Active clock source for the HF clock. */ 408 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 409 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 410 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ 411 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ 412 413 /* Register: CLOCK_LFCLKRUN */ 414 /* Description: Task LFCLKSTART triggered status. */ 415 416 /* Bit 0 : Task LFCLKSTART triggered status. */ 417 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 418 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 419 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ 420 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ 421 422 /* Register: CLOCK_LFCLKSTAT */ 423 /* Description: Low frequency clock status. */ 424 425 /* Bit 16 : State for the LF clock. */ 426 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 427 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 428 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ 429 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ 430 431 /* Bits 1..0 : Active clock source for the LF clock. */ 432 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 433 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 434 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ 435 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ 436 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ 437 438 /* Register: CLOCK_LFCLKSRCCOPY */ 439 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ 440 441 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ 442 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 443 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 444 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ 445 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ 446 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ 447 448 /* Register: CLOCK_LFCLKSRC */ 449 /* Description: Clock source for the LFCLK clock. */ 450 451 /* Bits 1..0 : Clock source. */ 452 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 453 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 454 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ 455 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ 456 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ 457 458 /* Register: CLOCK_CTIV */ 459 /* Description: Calibration timer interval. */ 460 461 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ 462 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ 463 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ 464 465 /* Register: CLOCK_XTALFREQ */ 466 /* Description: Crystal frequency. */ 467 468 /* Bits 7..0 : External Xtal frequency selection. */ 469 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ 470 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ 471 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ 472 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ 473 474 475 /* Peripheral: ECB */ 476 /* Description: AES ECB Mode Encryption. */ 477 478 /* Register: ECB_INTENSET */ 479 /* Description: Interrupt enable set register. */ 480 481 /* Bit 1 : Enable interrupt on ERRORECB event. */ 482 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 483 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 484 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ 485 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ 486 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ 487 488 /* Bit 0 : Enable interrupt on ENDECB event. */ 489 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 490 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 491 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ 492 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ 493 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ 494 495 /* Register: ECB_INTENCLR */ 496 /* Description: Interrupt enable clear register. */ 497 498 /* Bit 1 : Disable interrupt on ERRORECB event. */ 499 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 500 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 501 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ 502 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ 503 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ 504 505 /* Bit 0 : Disable interrupt on ENDECB event. */ 506 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 507 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 508 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ 509 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ 510 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ 511 512 /* Register: ECB_POWER */ 513 /* Description: Peripheral power control. */ 514 515 /* Bit 0 : Peripheral power control. */ 516 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 517 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 518 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 519 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 520 521 522 /* Peripheral: FICR */ 523 /* Description: Factory Information Configuration. */ 524 525 /* Register: FICR_PPFC */ 526 /* Description: Pre-programmed factory code present. */ 527 528 /* Bits 7..0 : Pre-programmed factory code present. */ 529 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ 530 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ 531 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ 532 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ 533 534 /* Register: FICR_CONFIGID */ 535 /* Description: Configuration identifier. */ 536 537 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ 538 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ 539 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ 540 541 /* Bits 15..0 : Hardware Identification Number. */ 542 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ 543 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ 544 545 /* Register: FICR_DEVICEADDRTYPE */ 546 /* Description: Device address type. */ 547 548 /* Bit 0 : Device address type. */ 549 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ 550 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ 551 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ 552 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ 553 554 /* Register: FICR_OVERRIDEEN */ 555 /* Description: Radio calibration override enable. */ 556 557 /* Bit 3 : Override default values for BLE_1Mbit mode. */ 558 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ 559 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ 560 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ 561 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ 562 563 /* Bit 0 : Override default values for NRF_1Mbit mode. */ 564 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ 565 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ 566 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ 567 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ 568 569 570 /* Peripheral: GPIO */ 571 /* Description: General purpose input and output. */ 572 573 /* Register: GPIO_OUT */ 574 /* Description: Write GPIO port. */ 575 576 /* Bit 31 : Pin 31. */ 577 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 578 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 579 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ 580 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ 581 582 /* Bit 30 : Pin 30. */ 583 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 584 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 585 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ 586 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ 587 588 /* Bit 29 : Pin 29. */ 589 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 590 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 591 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ 592 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ 593 594 /* Bit 28 : Pin 28. */ 595 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 596 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 597 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ 598 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ 599 600 /* Bit 27 : Pin 27. */ 601 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 602 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 603 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ 604 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ 605 606 /* Bit 26 : Pin 26. */ 607 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 608 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 609 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ 610 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ 611 612 /* Bit 25 : Pin 25. */ 613 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 614 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 615 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ 616 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ 617 618 /* Bit 24 : Pin 24. */ 619 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 620 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 621 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ 622 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ 623 624 /* Bit 23 : Pin 23. */ 625 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 626 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 627 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ 628 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ 629 630 /* Bit 22 : Pin 22. */ 631 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 632 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 633 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ 634 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ 635 636 /* Bit 21 : Pin 21. */ 637 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 638 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 639 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ 640 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ 641 642 /* Bit 20 : Pin 20. */ 643 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 644 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 645 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ 646 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ 647 648 /* Bit 19 : Pin 19. */ 649 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 650 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 651 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ 652 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ 653 654 /* Bit 18 : Pin 18. */ 655 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 656 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 657 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ 658 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ 659 660 /* Bit 17 : Pin 17. */ 661 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 662 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 663 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ 664 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ 665 666 /* Bit 16 : Pin 16. */ 667 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 668 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 669 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ 670 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ 671 672 /* Bit 15 : Pin 15. */ 673 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 674 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 675 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ 676 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ 677 678 /* Bit 14 : Pin 14. */ 679 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 680 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 681 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ 682 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ 683 684 /* Bit 13 : Pin 13. */ 685 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 686 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 687 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ 688 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ 689 690 /* Bit 12 : Pin 12. */ 691 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 692 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 693 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ 694 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ 695 696 /* Bit 11 : Pin 11. */ 697 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 698 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 699 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ 700 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ 701 702 /* Bit 10 : Pin 10. */ 703 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 704 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 705 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ 706 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ 707 708 /* Bit 9 : Pin 9. */ 709 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 710 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 711 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ 712 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ 713 714 /* Bit 8 : Pin 8. */ 715 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 716 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 717 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ 718 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ 719 720 /* Bit 7 : Pin 7. */ 721 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 722 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 723 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ 724 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ 725 726 /* Bit 6 : Pin 6. */ 727 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 728 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 729 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ 730 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ 731 732 /* Bit 5 : Pin 5. */ 733 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 734 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 735 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ 736 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ 737 738 /* Bit 4 : Pin 4. */ 739 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 740 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 741 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ 742 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ 743 744 /* Bit 3 : Pin 3. */ 745 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 746 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 747 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ 748 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ 749 750 /* Bit 2 : Pin 2. */ 751 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 752 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 753 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ 754 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ 755 756 /* Bit 1 : Pin 1. */ 757 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 758 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 759 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ 760 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ 761 762 /* Bit 0 : Pin 0. */ 763 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 764 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 765 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ 766 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ 767 768 /* Register: GPIO_OUTSET */ 769 /* Description: Set individual bits in GPIO port. */ 770 771 /* Bit 31 : Pin 31. */ 772 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 773 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 774 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ 775 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ 776 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ 777 778 /* Bit 30 : Pin 30. */ 779 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 780 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 781 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ 782 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ 783 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ 784 785 /* Bit 29 : Pin 29. */ 786 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 787 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 788 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ 789 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ 790 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ 791 792 /* Bit 28 : Pin 28. */ 793 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 794 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 795 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ 796 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ 797 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ 798 799 /* Bit 27 : Pin 27. */ 800 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 801 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 802 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ 803 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ 804 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ 805 806 /* Bit 26 : Pin 26. */ 807 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 808 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 809 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ 810 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ 811 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ 812 813 /* Bit 25 : Pin 25. */ 814 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 815 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 816 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ 817 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ 818 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ 819 820 /* Bit 24 : Pin 24. */ 821 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 822 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 823 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ 824 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ 825 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ 826 827 /* Bit 23 : Pin 23. */ 828 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 829 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 830 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ 831 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ 832 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ 833 834 /* Bit 22 : Pin 22. */ 835 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 836 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 837 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ 838 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ 839 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ 840 841 /* Bit 21 : Pin 21. */ 842 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 843 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 844 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ 845 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ 846 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ 847 848 /* Bit 20 : Pin 20. */ 849 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 850 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 851 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ 852 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ 853 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ 854 855 /* Bit 19 : Pin 19. */ 856 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 857 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 858 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ 859 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ 860 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ 861 862 /* Bit 18 : Pin 18. */ 863 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 864 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 865 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ 866 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ 867 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ 868 869 /* Bit 17 : Pin 17. */ 870 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 871 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 872 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ 873 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ 874 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ 875 876 /* Bit 16 : Pin 16. */ 877 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 878 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 879 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ 880 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ 881 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ 882 883 /* Bit 15 : Pin 15. */ 884 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 885 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 886 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ 887 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ 888 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ 889 890 /* Bit 14 : Pin 14. */ 891 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 892 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 893 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ 894 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ 895 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ 896 897 /* Bit 13 : Pin 13. */ 898 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 899 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 900 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ 901 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ 902 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ 903 904 /* Bit 12 : Pin 12. */ 905 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 906 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 907 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ 908 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ 909 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ 910 911 /* Bit 11 : Pin 11. */ 912 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 913 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 914 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ 915 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ 916 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ 917 918 /* Bit 10 : Pin 10. */ 919 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 920 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 921 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ 922 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ 923 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ 924 925 /* Bit 9 : Pin 9. */ 926 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 927 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 928 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ 929 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ 930 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ 931 932 /* Bit 8 : Pin 8. */ 933 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 934 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 935 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ 936 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ 937 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ 938 939 /* Bit 7 : Pin 7. */ 940 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 941 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 942 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ 943 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ 944 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ 945 946 /* Bit 6 : Pin 6. */ 947 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 948 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 949 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ 950 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ 951 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ 952 953 /* Bit 5 : Pin 5. */ 954 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 955 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 956 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ 957 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ 958 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ 959 960 /* Bit 4 : Pin 4. */ 961 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 962 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 963 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ 964 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ 965 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ 966 967 /* Bit 3 : Pin 3. */ 968 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 969 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 970 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ 971 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ 972 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ 973 974 /* Bit 2 : Pin 2. */ 975 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 976 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 977 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ 978 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ 979 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ 980 981 /* Bit 1 : Pin 1. */ 982 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 983 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 984 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ 985 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ 986 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ 987 988 /* Bit 0 : Pin 0. */ 989 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 990 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 991 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ 992 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ 993 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ 994 995 /* Register: GPIO_OUTCLR */ 996 /* Description: Clear individual bits in GPIO port. */ 997 998 /* Bit 31 : Pin 31. */ 999 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1000 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1001 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ 1002 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ 1003 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ 1004 1005 /* Bit 30 : Pin 30. */ 1006 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1007 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1008 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ 1009 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ 1010 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ 1011 1012 /* Bit 29 : Pin 29. */ 1013 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1014 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1015 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ 1016 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ 1017 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ 1018 1019 /* Bit 28 : Pin 28. */ 1020 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1021 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1022 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ 1023 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ 1024 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ 1025 1026 /* Bit 27 : Pin 27. */ 1027 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1028 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1029 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ 1030 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ 1031 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ 1032 1033 /* Bit 26 : Pin 26. */ 1034 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1035 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1036 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ 1037 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ 1038 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ 1039 1040 /* Bit 25 : Pin 25. */ 1041 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1042 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1043 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ 1044 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ 1045 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ 1046 1047 /* Bit 24 : Pin 24. */ 1048 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1049 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1050 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ 1051 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ 1052 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ 1053 1054 /* Bit 23 : Pin 23. */ 1055 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1056 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1057 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ 1058 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ 1059 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ 1060 1061 /* Bit 22 : Pin 22. */ 1062 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1063 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1064 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ 1065 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ 1066 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ 1067 1068 /* Bit 21 : Pin 21. */ 1069 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1070 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1071 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ 1072 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ 1073 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ 1074 1075 /* Bit 20 : Pin 20. */ 1076 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1077 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1078 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ 1079 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ 1080 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ 1081 1082 /* Bit 19 : Pin 19. */ 1083 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1084 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1085 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ 1086 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ 1087 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ 1088 1089 /* Bit 18 : Pin 18. */ 1090 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1091 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1092 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ 1093 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ 1094 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ 1095 1096 /* Bit 17 : Pin 17. */ 1097 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1098 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1099 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ 1100 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ 1101 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ 1102 1103 /* Bit 16 : Pin 16. */ 1104 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1105 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1106 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ 1107 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ 1108 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ 1109 1110 /* Bit 15 : Pin 15. */ 1111 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1112 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1113 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ 1114 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ 1115 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ 1116 1117 /* Bit 14 : Pin 14. */ 1118 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1119 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1120 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ 1121 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ 1122 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ 1123 1124 /* Bit 13 : Pin 13. */ 1125 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1126 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1127 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ 1128 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ 1129 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ 1130 1131 /* Bit 12 : Pin 12. */ 1132 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1133 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1134 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ 1135 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ 1136 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ 1137 1138 /* Bit 11 : Pin 11. */ 1139 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1140 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1141 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ 1142 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ 1143 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ 1144 1145 /* Bit 10 : Pin 10. */ 1146 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1147 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1148 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ 1149 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ 1150 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ 1151 1152 /* Bit 9 : Pin 9. */ 1153 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1154 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1155 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ 1156 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ 1157 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ 1158 1159 /* Bit 8 : Pin 8. */ 1160 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1161 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1162 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ 1163 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ 1164 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ 1165 1166 /* Bit 7 : Pin 7. */ 1167 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1168 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1169 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ 1170 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ 1171 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ 1172 1173 /* Bit 6 : Pin 6. */ 1174 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1175 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1176 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ 1177 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ 1178 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ 1179 1180 /* Bit 5 : Pin 5. */ 1181 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1182 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1183 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ 1184 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ 1185 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ 1186 1187 /* Bit 4 : Pin 4. */ 1188 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1189 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1190 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ 1191 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ 1192 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ 1193 1194 /* Bit 3 : Pin 3. */ 1195 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1196 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1197 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ 1198 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ 1199 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ 1200 1201 /* Bit 2 : Pin 2. */ 1202 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1203 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1204 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ 1205 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ 1206 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ 1207 1208 /* Bit 1 : Pin 1. */ 1209 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1210 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1211 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ 1212 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ 1213 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ 1214 1215 /* Bit 0 : Pin 0. */ 1216 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1217 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1218 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ 1219 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ 1220 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ 1221 1222 /* Register: GPIO_IN */ 1223 /* Description: Read GPIO port. */ 1224 1225 /* Bit 31 : Pin 31. */ 1226 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1227 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1228 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ 1229 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ 1230 1231 /* Bit 30 : Pin 30. */ 1232 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1233 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1234 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ 1235 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ 1236 1237 /* Bit 29 : Pin 29. */ 1238 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1239 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1240 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ 1241 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ 1242 1243 /* Bit 28 : Pin 28. */ 1244 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1245 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1246 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ 1247 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ 1248 1249 /* Bit 27 : Pin 27. */ 1250 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1251 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1252 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ 1253 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ 1254 1255 /* Bit 26 : Pin 26. */ 1256 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1257 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1258 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ 1259 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ 1260 1261 /* Bit 25 : Pin 25. */ 1262 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1263 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1264 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ 1265 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ 1266 1267 /* Bit 24 : Pin 24. */ 1268 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1269 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1270 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ 1271 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ 1272 1273 /* Bit 23 : Pin 23. */ 1274 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1275 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1276 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ 1277 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ 1278 1279 /* Bit 22 : Pin 22. */ 1280 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1281 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1282 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ 1283 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ 1284 1285 /* Bit 21 : Pin 21. */ 1286 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1287 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1288 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ 1289 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ 1290 1291 /* Bit 20 : Pin 20. */ 1292 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1293 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1294 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ 1295 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ 1296 1297 /* Bit 19 : Pin 19. */ 1298 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1299 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1300 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ 1301 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ 1302 1303 /* Bit 18 : Pin 18. */ 1304 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1305 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1306 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ 1307 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ 1308 1309 /* Bit 17 : Pin 17. */ 1310 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1311 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1312 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ 1313 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ 1314 1315 /* Bit 16 : Pin 16. */ 1316 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1317 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1318 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ 1319 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ 1320 1321 /* Bit 15 : Pin 15. */ 1322 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1323 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1324 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ 1325 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ 1326 1327 /* Bit 14 : Pin 14. */ 1328 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1329 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1330 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ 1331 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ 1332 1333 /* Bit 13 : Pin 13. */ 1334 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1335 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1336 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ 1337 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ 1338 1339 /* Bit 12 : Pin 12. */ 1340 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1341 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1342 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ 1343 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ 1344 1345 /* Bit 11 : Pin 11. */ 1346 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1347 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1348 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ 1349 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ 1350 1351 /* Bit 10 : Pin 10. */ 1352 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1353 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1354 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ 1355 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ 1356 1357 /* Bit 9 : Pin 9. */ 1358 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1359 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1360 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ 1361 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ 1362 1363 /* Bit 8 : Pin 8. */ 1364 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1365 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1366 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ 1367 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ 1368 1369 /* Bit 7 : Pin 7. */ 1370 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1371 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1372 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ 1373 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ 1374 1375 /* Bit 6 : Pin 6. */ 1376 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1377 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1378 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ 1379 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ 1380 1381 /* Bit 5 : Pin 5. */ 1382 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1383 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1384 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ 1385 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ 1386 1387 /* Bit 4 : Pin 4. */ 1388 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1389 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1390 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ 1391 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ 1392 1393 /* Bit 3 : Pin 3. */ 1394 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1395 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1396 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ 1397 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ 1398 1399 /* Bit 2 : Pin 2. */ 1400 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1401 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1402 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ 1403 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ 1404 1405 /* Bit 1 : Pin 1. */ 1406 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1407 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1408 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ 1409 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ 1410 1411 /* Bit 0 : Pin 0. */ 1412 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1413 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1414 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ 1415 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ 1416 1417 /* Register: GPIO_DIR */ 1418 /* Description: Direction of GPIO pins. */ 1419 1420 /* Bit 31 : Pin 31. */ 1421 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1422 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1423 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ 1424 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ 1425 1426 /* Bit 30 : Pin 30. */ 1427 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1428 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1429 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ 1430 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ 1431 1432 /* Bit 29 : Pin 29. */ 1433 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1434 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1435 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ 1436 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ 1437 1438 /* Bit 28 : Pin 28. */ 1439 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1440 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1441 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ 1442 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ 1443 1444 /* Bit 27 : Pin 27. */ 1445 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1446 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1447 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ 1448 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ 1449 1450 /* Bit 26 : Pin 26. */ 1451 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1452 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1453 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ 1454 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ 1455 1456 /* Bit 25 : Pin 25. */ 1457 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1458 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1459 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ 1460 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ 1461 1462 /* Bit 24 : Pin 24. */ 1463 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1464 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1465 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ 1466 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ 1467 1468 /* Bit 23 : Pin 23. */ 1469 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1470 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1471 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ 1472 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ 1473 1474 /* Bit 22 : Pin 22. */ 1475 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1476 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1477 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ 1478 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ 1479 1480 /* Bit 21 : Pin 21. */ 1481 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1482 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1483 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ 1484 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ 1485 1486 /* Bit 20 : Pin 20. */ 1487 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1488 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1489 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ 1490 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ 1491 1492 /* Bit 19 : Pin 19. */ 1493 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1494 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1495 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ 1496 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ 1497 1498 /* Bit 18 : Pin 18. */ 1499 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1500 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1501 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ 1502 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ 1503 1504 /* Bit 17 : Pin 17. */ 1505 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1506 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1507 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ 1508 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ 1509 1510 /* Bit 16 : Pin 16. */ 1511 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1512 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1513 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ 1514 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ 1515 1516 /* Bit 15 : Pin 15. */ 1517 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1518 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1519 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ 1520 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ 1521 1522 /* Bit 14 : Pin 14. */ 1523 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1524 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1525 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ 1526 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ 1527 1528 /* Bit 13 : Pin 13. */ 1529 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1530 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1531 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ 1532 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ 1533 1534 /* Bit 12 : Pin 12. */ 1535 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1536 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1537 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ 1538 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ 1539 1540 /* Bit 11 : Pin 11. */ 1541 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1542 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1543 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ 1544 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ 1545 1546 /* Bit 10 : Pin 10. */ 1547 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1548 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1549 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ 1550 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ 1551 1552 /* Bit 9 : Pin 9. */ 1553 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1554 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1555 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ 1556 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ 1557 1558 /* Bit 8 : Pin 8. */ 1559 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1560 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1561 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ 1562 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ 1563 1564 /* Bit 7 : Pin 7. */ 1565 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1566 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1567 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ 1568 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ 1569 1570 /* Bit 6 : Pin 6. */ 1571 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1572 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1573 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ 1574 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ 1575 1576 /* Bit 5 : Pin 5. */ 1577 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1578 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1579 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ 1580 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ 1581 1582 /* Bit 4 : Pin 4. */ 1583 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1584 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1585 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ 1586 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ 1587 1588 /* Bit 3 : Pin 3. */ 1589 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1590 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1591 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ 1592 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ 1593 1594 /* Bit 2 : Pin 2. */ 1595 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1596 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1597 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ 1598 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ 1599 1600 /* Bit 1 : Pin 1. */ 1601 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1602 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1603 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ 1604 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ 1605 1606 /* Bit 0 : Pin 0. */ 1607 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1608 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1609 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ 1610 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ 1611 1612 /* Register: GPIO_DIRSET */ 1613 /* Description: DIR set register. */ 1614 1615 /* Bit 31 : Set as output pin 31. */ 1616 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1617 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1618 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ 1619 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ 1620 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ 1621 1622 /* Bit 30 : Set as output pin 30. */ 1623 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1624 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1625 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ 1626 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ 1627 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ 1628 1629 /* Bit 29 : Set as output pin 29. */ 1630 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1631 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1632 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ 1633 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ 1634 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ 1635 1636 /* Bit 28 : Set as output pin 28. */ 1637 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1638 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1639 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ 1640 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ 1641 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ 1642 1643 /* Bit 27 : Set as output pin 27. */ 1644 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1645 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1646 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ 1647 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ 1648 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ 1649 1650 /* Bit 26 : Set as output pin 26. */ 1651 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1652 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1653 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ 1654 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ 1655 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ 1656 1657 /* Bit 25 : Set as output pin 25. */ 1658 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1659 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1660 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ 1661 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ 1662 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ 1663 1664 /* Bit 24 : Set as output pin 24. */ 1665 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1666 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1667 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ 1668 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ 1669 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ 1670 1671 /* Bit 23 : Set as output pin 23. */ 1672 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1673 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1674 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ 1675 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ 1676 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ 1677 1678 /* Bit 22 : Set as output pin 22. */ 1679 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1680 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1681 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ 1682 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ 1683 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ 1684 1685 /* Bit 21 : Set as output pin 21. */ 1686 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1687 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1688 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ 1689 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ 1690 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ 1691 1692 /* Bit 20 : Set as output pin 20. */ 1693 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1694 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1695 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ 1696 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ 1697 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ 1698 1699 /* Bit 19 : Set as output pin 19. */ 1700 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1701 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1702 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ 1703 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ 1704 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ 1705 1706 /* Bit 18 : Set as output pin 18. */ 1707 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1708 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1709 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ 1710 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ 1711 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ 1712 1713 /* Bit 17 : Set as output pin 17. */ 1714 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1715 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1716 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ 1717 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ 1718 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ 1719 1720 /* Bit 16 : Set as output pin 16. */ 1721 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1722 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1723 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ 1724 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ 1725 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ 1726 1727 /* Bit 15 : Set as output pin 15. */ 1728 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1729 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1730 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ 1731 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ 1732 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ 1733 1734 /* Bit 14 : Set as output pin 14. */ 1735 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1736 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1737 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ 1738 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ 1739 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ 1740 1741 /* Bit 13 : Set as output pin 13. */ 1742 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1743 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1744 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ 1745 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ 1746 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ 1747 1748 /* Bit 12 : Set as output pin 12. */ 1749 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1750 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1751 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ 1752 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ 1753 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ 1754 1755 /* Bit 11 : Set as output pin 11. */ 1756 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1757 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1758 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ 1759 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ 1760 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ 1761 1762 /* Bit 10 : Set as output pin 10. */ 1763 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1764 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1765 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ 1766 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ 1767 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ 1768 1769 /* Bit 9 : Set as output pin 9. */ 1770 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1771 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1772 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ 1773 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ 1774 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ 1775 1776 /* Bit 8 : Set as output pin 8. */ 1777 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1778 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1779 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ 1780 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ 1781 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ 1782 1783 /* Bit 7 : Set as output pin 7. */ 1784 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1785 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1786 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ 1787 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ 1788 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ 1789 1790 /* Bit 6 : Set as output pin 6. */ 1791 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1792 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1793 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ 1794 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ 1795 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ 1796 1797 /* Bit 5 : Set as output pin 5. */ 1798 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1799 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1800 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ 1801 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ 1802 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ 1803 1804 /* Bit 4 : Set as output pin 4. */ 1805 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1806 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1807 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ 1808 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ 1809 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ 1810 1811 /* Bit 3 : Set as output pin 3. */ 1812 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1813 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1814 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ 1815 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ 1816 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ 1817 1818 /* Bit 2 : Set as output pin 2. */ 1819 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1820 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1821 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ 1822 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ 1823 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ 1824 1825 /* Bit 1 : Set as output pin 1. */ 1826 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1827 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1828 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ 1829 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ 1830 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ 1831 1832 /* Bit 0 : Set as output pin 0. */ 1833 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1834 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1835 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ 1836 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ 1837 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ 1838 1839 /* Register: GPIO_DIRCLR */ 1840 /* Description: DIR clear register. */ 1841 1842 /* Bit 31 : Set as input pin 31. */ 1843 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1844 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1845 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ 1846 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ 1847 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ 1848 1849 /* Bit 30 : Set as input pin 30. */ 1850 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1851 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1852 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ 1853 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ 1854 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ 1855 1856 /* Bit 29 : Set as input pin 29. */ 1857 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1858 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1859 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ 1860 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ 1861 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ 1862 1863 /* Bit 28 : Set as input pin 28. */ 1864 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1865 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1866 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ 1867 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ 1868 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ 1869 1870 /* Bit 27 : Set as input pin 27. */ 1871 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1872 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1873 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ 1874 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ 1875 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ 1876 1877 /* Bit 26 : Set as input pin 26. */ 1878 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1879 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1880 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ 1881 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ 1882 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ 1883 1884 /* Bit 25 : Set as input pin 25. */ 1885 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1886 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1887 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ 1888 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ 1889 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ 1890 1891 /* Bit 24 : Set as input pin 24. */ 1892 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1893 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1894 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ 1895 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ 1896 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ 1897 1898 /* Bit 23 : Set as input pin 23. */ 1899 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1900 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1901 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ 1902 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ 1903 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ 1904 1905 /* Bit 22 : Set as input pin 22. */ 1906 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1907 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1908 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ 1909 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ 1910 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ 1911 1912 /* Bit 21 : Set as input pin 21. */ 1913 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1914 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1915 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ 1916 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ 1917 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ 1918 1919 /* Bit 20 : Set as input pin 20. */ 1920 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1921 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1922 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ 1923 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ 1924 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ 1925 1926 /* Bit 19 : Set as input pin 19. */ 1927 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1928 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1929 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ 1930 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ 1931 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ 1932 1933 /* Bit 18 : Set as input pin 18. */ 1934 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1935 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1936 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ 1937 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ 1938 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ 1939 1940 /* Bit 17 : Set as input pin 17. */ 1941 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1942 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1943 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ 1944 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ 1945 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ 1946 1947 /* Bit 16 : Set as input pin 16. */ 1948 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1949 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1950 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ 1951 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ 1952 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ 1953 1954 /* Bit 15 : Set as input pin 15. */ 1955 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1956 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1957 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ 1958 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ 1959 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ 1960 1961 /* Bit 14 : Set as input pin 14. */ 1962 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1963 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1964 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ 1965 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ 1966 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ 1967 1968 /* Bit 13 : Set as input pin 13. */ 1969 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1970 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1971 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ 1972 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ 1973 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ 1974 1975 /* Bit 12 : Set as input pin 12. */ 1976 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1977 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1978 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ 1979 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ 1980 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ 1981 1982 /* Bit 11 : Set as input pin 11. */ 1983 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1984 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1985 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ 1986 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ 1987 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ 1988 1989 /* Bit 10 : Set as input pin 10. */ 1990 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1991 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1992 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ 1993 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ 1994 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ 1995 1996 /* Bit 9 : Set as input pin 9. */ 1997 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1998 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1999 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ 2000 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ 2001 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ 2002 2003 /* Bit 8 : Set as input pin 8. */ 2004 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2005 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2006 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ 2007 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ 2008 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ 2009 2010 /* Bit 7 : Set as input pin 7. */ 2011 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2012 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2013 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ 2014 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ 2015 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ 2016 2017 /* Bit 6 : Set as input pin 6. */ 2018 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2019 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2020 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ 2021 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ 2022 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ 2023 2024 /* Bit 5 : Set as input pin 5. */ 2025 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2026 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2027 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ 2028 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ 2029 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ 2030 2031 /* Bit 4 : Set as input pin 4. */ 2032 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2033 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2034 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ 2035 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ 2036 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ 2037 2038 /* Bit 3 : Set as input pin 3. */ 2039 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2040 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2041 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ 2042 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ 2043 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ 2044 2045 /* Bit 2 : Set as input pin 2. */ 2046 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2047 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2048 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ 2049 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ 2050 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ 2051 2052 /* Bit 1 : Set as input pin 1. */ 2053 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2054 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2055 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ 2056 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ 2057 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ 2058 2059 /* Bit 0 : Set as input pin 0. */ 2060 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2061 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2062 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ 2063 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ 2064 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ 2065 2066 /* Register: GPIO_PIN_CNF */ 2067 /* Description: Configuration of GPIO pins. */ 2068 2069 /* Bits 17..16 : Pin sensing mechanism. */ 2070 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 2071 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 2072 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ 2073 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ 2074 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ 2075 2076 /* Bits 10..8 : Drive configuration. */ 2077 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 2078 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 2079 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ 2080 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ 2081 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ 2082 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ 2083 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ 2084 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ 2085 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ 2086 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ 2087 2088 /* Bits 3..2 : Pull-up or -down configuration. */ 2089 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 2090 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 2091 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ 2092 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ 2093 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ 2094 2095 /* Bit 1 : Connect or disconnect input path. */ 2096 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 2097 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 2098 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ 2099 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ 2100 2101 /* Bit 0 : Pin direction. */ 2102 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 2103 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 2104 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ 2105 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ 2106 2107 2108 /* Peripheral: GPIOTE */ 2109 /* Description: GPIO tasks and events. */ 2110 2111 /* Register: GPIOTE_INTENSET */ 2112 /* Description: Interrupt enable set register. */ 2113 2114 /* Bit 31 : Enable interrupt on PORT event. */ 2115 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 2116 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 2117 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ 2118 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ 2119 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ 2120 2121 /* Bit 3 : Enable interrupt on IN[3] event. */ 2122 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 2123 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 2124 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ 2125 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ 2126 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ 2127 2128 /* Bit 2 : Enable interrupt on IN[2] event. */ 2129 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 2130 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 2131 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ 2132 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ 2133 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ 2134 2135 /* Bit 1 : Enable interrupt on IN[1] event. */ 2136 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 2137 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 2138 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ 2139 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ 2140 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ 2141 2142 /* Bit 0 : Enable interrupt on IN[0] event. */ 2143 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 2144 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 2145 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ 2146 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ 2147 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ 2148 2149 /* Register: GPIOTE_INTENCLR */ 2150 /* Description: Interrupt enable clear register. */ 2151 2152 /* Bit 31 : Disable interrupt on PORT event. */ 2153 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 2154 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 2155 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ 2156 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ 2157 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ 2158 2159 /* Bit 3 : Disable interrupt on IN[3] event. */ 2160 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 2161 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 2162 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ 2163 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ 2164 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ 2165 2166 /* Bit 2 : Disable interrupt on IN[2] event. */ 2167 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 2168 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 2169 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ 2170 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ 2171 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ 2172 2173 /* Bit 1 : Disable interrupt on IN[1] event. */ 2174 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 2175 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 2176 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ 2177 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ 2178 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ 2179 2180 /* Bit 0 : Disable interrupt on IN[0] event. */ 2181 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 2182 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 2183 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ 2184 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ 2185 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ 2186 2187 /* Register: GPIOTE_CONFIG */ 2188 /* Description: Channel configuration registers. */ 2189 2190 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ 2191 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 2192 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 2193 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ 2194 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ 2195 2196 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ 2197 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 2198 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 2199 #define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ 2200 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ 2201 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ 2202 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ 2203 2204 /* Bits 12..8 : Pin select. */ 2205 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 2206 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 2207 2208 /* Bits 1..0 : Mode */ 2209 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 2210 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 2211 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ 2212 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ 2213 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ 2214 2215 /* Register: GPIOTE_POWER */ 2216 /* Description: Peripheral power control. */ 2217 2218 /* Bit 0 : Peripheral power control. */ 2219 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 2220 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 2221 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 2222 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 2223 2224 2225 /* Peripheral: LPCOMP */ 2226 /* Description: Low power comparator. */ 2227 2228 /* Register: LPCOMP_SHORTS */ 2229 /* Description: Shortcuts for the LPCOMP. */ 2230 2231 /* Bit 4 : Shortcut between CROSS event and STOP task. */ 2232 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ 2233 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ 2234 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2235 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2236 2237 /* Bit 3 : Shortcut between UP event and STOP task. */ 2238 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ 2239 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ 2240 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2241 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2242 2243 /* Bit 2 : Shortcut between DOWN event and STOP task. */ 2244 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ 2245 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ 2246 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2247 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2248 2249 /* Bit 1 : Shortcut between RADY event and STOP task. */ 2250 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ 2251 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ 2252 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2253 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2254 2255 /* Bit 0 : Shortcut between READY event and SAMPLE task. */ 2256 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ 2257 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ 2258 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ 2259 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ 2260 2261 /* Register: LPCOMP_INTENSET */ 2262 /* Description: Interrupt enable set register. */ 2263 2264 /* Bit 3 : Enable interrupt on CROSS event. */ 2265 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 2266 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ 2267 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ 2268 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ 2269 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ 2270 2271 /* Bit 2 : Enable interrupt on UP event. */ 2272 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ 2273 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ 2274 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ 2275 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ 2276 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ 2277 2278 /* Bit 1 : Enable interrupt on DOWN event. */ 2279 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 2280 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ 2281 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ 2282 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ 2283 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ 2284 2285 /* Bit 0 : Enable interrupt on READY event. */ 2286 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 2287 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 2288 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 2289 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 2290 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 2291 2292 /* Register: LPCOMP_INTENCLR */ 2293 /* Description: Interrupt enable clear register. */ 2294 2295 /* Bit 3 : Disable interrupt on CROSS event. */ 2296 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 2297 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ 2298 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ 2299 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ 2300 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ 2301 2302 /* Bit 2 : Disable interrupt on UP event. */ 2303 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ 2304 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ 2305 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ 2306 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ 2307 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ 2308 2309 /* Bit 1 : Disable interrupt on DOWN event. */ 2310 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 2311 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ 2312 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ 2313 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ 2314 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ 2315 2316 /* Bit 0 : Disable interrupt on READY event. */ 2317 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 2318 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 2319 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 2320 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 2321 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 2322 2323 /* Register: LPCOMP_RESULT */ 2324 /* Description: Result of last compare. */ 2325 2326 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ 2327 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 2328 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 2329 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */ 2330 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ 2331 2332 /* Register: LPCOMP_ENABLE */ 2333 /* Description: Enable the LPCOMP. */ 2334 2335 /* Bits 1..0 : Enable or disable LPCOMP. */ 2336 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 2337 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 2338 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ 2339 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ 2340 2341 /* Register: LPCOMP_PSEL */ 2342 /* Description: Input pin select. */ 2343 2344 /* Bits 2..0 : Analog input pin select. */ 2345 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ 2346 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ 2347 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ 2348 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ 2349 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ 2350 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ 2351 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ 2352 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ 2353 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ 2354 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ 2355 2356 /* Register: LPCOMP_REFSEL */ 2357 /* Description: Reference select. */ 2358 2359 /* Bits 2..0 : Reference select. */ 2360 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ 2361 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 2362 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ 2363 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ 2364 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ 2365 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ 2366 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ 2367 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ 2368 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ 2369 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ 2370 2371 /* Register: LPCOMP_EXTREFSEL */ 2372 /* Description: External reference select. */ 2373 2374 /* Bit 0 : External analog reference pin selection. */ 2375 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ 2376 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 2377 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ 2378 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ 2379 2380 /* Register: LPCOMP_ANADETECT */ 2381 /* Description: Analog detect configuration. */ 2382 2383 /* Bits 1..0 : Analog detect configuration. */ 2384 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ 2385 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ 2386 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ 2387 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ 2388 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ 2389 2390 /* Register: LPCOMP_POWER */ 2391 /* Description: Peripheral power control. */ 2392 2393 /* Bit 0 : Peripheral power control. */ 2394 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 2395 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 2396 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 2397 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 2398 2399 2400 /* Peripheral: MPU */ 2401 /* Description: Memory Protection Unit. */ 2402 2403 /* Register: MPU_PERR0 */ 2404 /* Description: Configuration of peripherals in mpu regions. */ 2405 2406 /* Bit 31 : PPI region configuration. */ 2407 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ 2408 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ 2409 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2410 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2411 2412 /* Bit 30 : NVMC region configuration. */ 2413 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ 2414 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ 2415 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2416 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2417 2418 /* Bit 19 : LPCOMP region configuration. */ 2419 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ 2420 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 2421 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2422 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2423 2424 /* Bit 18 : QDEC region configuration. */ 2425 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ 2426 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ 2427 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2428 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2429 2430 /* Bit 17 : RTC1 region configuration. */ 2431 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ 2432 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ 2433 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2434 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2435 2436 /* Bit 16 : WDT region configuration. */ 2437 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ 2438 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ 2439 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2440 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2441 2442 /* Bit 15 : CCM and AAR region configuration. */ 2443 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ 2444 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ 2445 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2446 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2447 2448 /* Bit 14 : ECB region configuration. */ 2449 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ 2450 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ 2451 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2452 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2453 2454 /* Bit 13 : RNG region configuration. */ 2455 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ 2456 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ 2457 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2458 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2459 2460 /* Bit 12 : TEMP region configuration. */ 2461 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ 2462 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ 2463 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2464 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2465 2466 /* Bit 11 : RTC0 region configuration. */ 2467 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ 2468 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ 2469 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2470 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2471 2472 /* Bit 10 : TIMER2 region configuration. */ 2473 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ 2474 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ 2475 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2476 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2477 2478 /* Bit 9 : TIMER1 region configuration. */ 2479 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ 2480 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ 2481 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2482 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2483 2484 /* Bit 8 : TIMER0 region configuration. */ 2485 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ 2486 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ 2487 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2488 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2489 2490 /* Bit 7 : ADC region configuration. */ 2491 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ 2492 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ 2493 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2494 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2495 2496 /* Bit 6 : GPIOTE region configuration. */ 2497 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ 2498 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ 2499 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2500 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2501 2502 /* Bit 4 : SPI1 and TWI1 region configuration. */ 2503 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ 2504 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ 2505 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2506 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2507 2508 /* Bit 3 : SPI0 and TWI0 region configuration. */ 2509 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ 2510 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ 2511 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2512 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2513 2514 /* Bit 2 : UART0 region configuration. */ 2515 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ 2516 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ 2517 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2518 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2519 2520 /* Bit 1 : RADIO region configuration. */ 2521 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ 2522 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ 2523 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2524 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2525 2526 /* Bit 0 : POWER_CLOCK region configuration. */ 2527 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ 2528 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ 2529 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 2530 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 2531 2532 /* Register: MPU_PROTENSET0 */ 2533 /* Description: Erase and write protection bit enable set register. */ 2534 2535 /* Bit 31 : Protection enable for region 31. */ 2536 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ 2537 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ 2538 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ 2539 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ 2540 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ 2541 2542 /* Bit 30 : Protection enable for region 30. */ 2543 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ 2544 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ 2545 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ 2546 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ 2547 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ 2548 2549 /* Bit 29 : Protection enable for region 29. */ 2550 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ 2551 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ 2552 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ 2553 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ 2554 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ 2555 2556 /* Bit 28 : Protection enable for region 28. */ 2557 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ 2558 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ 2559 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ 2560 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ 2561 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ 2562 2563 /* Bit 27 : Protection enable for region 27. */ 2564 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ 2565 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ 2566 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ 2567 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ 2568 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ 2569 2570 /* Bit 26 : Protection enable for region 26. */ 2571 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ 2572 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ 2573 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ 2574 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ 2575 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ 2576 2577 /* Bit 25 : Protection enable for region 25. */ 2578 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ 2579 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ 2580 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ 2581 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ 2582 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ 2583 2584 /* Bit 24 : Protection enable for region 24. */ 2585 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ 2586 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ 2587 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ 2588 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ 2589 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ 2590 2591 /* Bit 23 : Protection enable for region 23. */ 2592 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ 2593 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ 2594 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ 2595 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ 2596 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ 2597 2598 /* Bit 22 : Protection enable for region 22. */ 2599 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ 2600 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ 2601 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ 2602 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ 2603 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ 2604 2605 /* Bit 21 : Protection enable for region 21. */ 2606 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ 2607 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ 2608 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ 2609 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ 2610 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ 2611 2612 /* Bit 20 : Protection enable for region 20. */ 2613 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ 2614 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ 2615 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ 2616 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ 2617 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ 2618 2619 /* Bit 19 : Protection enable for region 19. */ 2620 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ 2621 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ 2622 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ 2623 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ 2624 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ 2625 2626 /* Bit 18 : Protection enable for region 18. */ 2627 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ 2628 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ 2629 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ 2630 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ 2631 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ 2632 2633 /* Bit 17 : Protection enable for region 17. */ 2634 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ 2635 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ 2636 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ 2637 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ 2638 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ 2639 2640 /* Bit 16 : Protection enable for region 16. */ 2641 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ 2642 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ 2643 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ 2644 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ 2645 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ 2646 2647 /* Bit 15 : Protection enable for region 15. */ 2648 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ 2649 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ 2650 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ 2651 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ 2652 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ 2653 2654 /* Bit 14 : Protection enable for region 14. */ 2655 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ 2656 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ 2657 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ 2658 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ 2659 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ 2660 2661 /* Bit 13 : Protection enable for region 13. */ 2662 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ 2663 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ 2664 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ 2665 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ 2666 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ 2667 2668 /* Bit 12 : Protection enable for region 12. */ 2669 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ 2670 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ 2671 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ 2672 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ 2673 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ 2674 2675 /* Bit 11 : Protection enable for region 11. */ 2676 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ 2677 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ 2678 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ 2679 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ 2680 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ 2681 2682 /* Bit 10 : Protection enable for region 10. */ 2683 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ 2684 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ 2685 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ 2686 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ 2687 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ 2688 2689 /* Bit 9 : Protection enable for region 9. */ 2690 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ 2691 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ 2692 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ 2693 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ 2694 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ 2695 2696 /* Bit 8 : Protection enable for region 8. */ 2697 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ 2698 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ 2699 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ 2700 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ 2701 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ 2702 2703 /* Bit 7 : Protection enable for region 7. */ 2704 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ 2705 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ 2706 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ 2707 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ 2708 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ 2709 2710 /* Bit 6 : Protection enable for region 6. */ 2711 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ 2712 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ 2713 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ 2714 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ 2715 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ 2716 2717 /* Bit 5 : Protection enable for region 5. */ 2718 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ 2719 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ 2720 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ 2721 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ 2722 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ 2723 2724 /* Bit 4 : Protection enable for region 4. */ 2725 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ 2726 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ 2727 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ 2728 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ 2729 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ 2730 2731 /* Bit 3 : Protection enable for region 3. */ 2732 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ 2733 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ 2734 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ 2735 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ 2736 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ 2737 2738 /* Bit 2 : Protection enable for region 2. */ 2739 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ 2740 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ 2741 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ 2742 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ 2743 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ 2744 2745 /* Bit 1 : Protection enable for region 1. */ 2746 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ 2747 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ 2748 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ 2749 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ 2750 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ 2751 2752 /* Bit 0 : Protection enable for region 0. */ 2753 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ 2754 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ 2755 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ 2756 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ 2757 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ 2758 2759 /* Register: MPU_PROTENSET1 */ 2760 /* Description: Erase and write protection bit enable set register. */ 2761 2762 /* Bit 31 : Protection enable for region 63. */ 2763 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ 2764 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ 2765 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ 2766 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ 2767 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ 2768 2769 /* Bit 30 : Protection enable for region 62. */ 2770 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ 2771 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ 2772 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ 2773 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ 2774 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ 2775 2776 /* Bit 29 : Protection enable for region 61. */ 2777 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ 2778 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ 2779 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ 2780 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ 2781 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ 2782 2783 /* Bit 28 : Protection enable for region 60. */ 2784 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ 2785 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ 2786 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ 2787 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ 2788 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ 2789 2790 /* Bit 27 : Protection enable for region 59. */ 2791 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ 2792 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ 2793 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ 2794 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ 2795 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ 2796 2797 /* Bit 26 : Protection enable for region 58. */ 2798 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ 2799 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ 2800 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ 2801 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ 2802 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ 2803 2804 /* Bit 25 : Protection enable for region 57. */ 2805 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ 2806 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ 2807 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ 2808 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ 2809 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ 2810 2811 /* Bit 24 : Protection enable for region 56. */ 2812 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ 2813 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ 2814 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ 2815 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ 2816 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ 2817 2818 /* Bit 23 : Protection enable for region 55. */ 2819 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ 2820 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ 2821 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ 2822 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ 2823 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ 2824 2825 /* Bit 22 : Protection enable for region 54. */ 2826 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ 2827 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ 2828 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ 2829 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ 2830 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ 2831 2832 /* Bit 21 : Protection enable for region 53. */ 2833 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ 2834 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ 2835 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ 2836 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ 2837 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ 2838 2839 /* Bit 20 : Protection enable for region 52. */ 2840 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ 2841 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ 2842 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ 2843 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ 2844 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ 2845 2846 /* Bit 19 : Protection enable for region 51. */ 2847 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ 2848 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ 2849 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ 2850 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ 2851 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ 2852 2853 /* Bit 18 : Protection enable for region 50. */ 2854 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ 2855 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ 2856 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ 2857 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ 2858 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ 2859 2860 /* Bit 17 : Protection enable for region 49. */ 2861 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ 2862 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ 2863 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ 2864 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ 2865 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ 2866 2867 /* Bit 16 : Protection enable for region 48. */ 2868 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ 2869 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ 2870 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ 2871 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ 2872 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ 2873 2874 /* Bit 15 : Protection enable for region 47. */ 2875 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ 2876 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ 2877 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ 2878 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ 2879 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ 2880 2881 /* Bit 14 : Protection enable for region 46. */ 2882 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ 2883 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ 2884 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ 2885 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ 2886 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ 2887 2888 /* Bit 13 : Protection enable for region 45. */ 2889 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ 2890 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ 2891 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ 2892 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ 2893 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ 2894 2895 /* Bit 12 : Protection enable for region 44. */ 2896 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ 2897 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ 2898 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ 2899 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ 2900 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ 2901 2902 /* Bit 11 : Protection enable for region 43. */ 2903 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ 2904 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ 2905 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ 2906 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ 2907 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ 2908 2909 /* Bit 10 : Protection enable for region 42. */ 2910 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ 2911 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ 2912 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ 2913 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ 2914 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ 2915 2916 /* Bit 9 : Protection enable for region 41. */ 2917 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ 2918 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ 2919 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ 2920 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ 2921 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ 2922 2923 /* Bit 8 : Protection enable for region 40. */ 2924 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ 2925 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ 2926 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ 2927 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ 2928 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ 2929 2930 /* Bit 7 : Protection enable for region 39. */ 2931 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ 2932 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ 2933 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ 2934 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ 2935 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ 2936 2937 /* Bit 6 : Protection enable for region 38. */ 2938 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ 2939 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ 2940 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ 2941 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ 2942 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ 2943 2944 /* Bit 5 : Protection enable for region 37. */ 2945 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ 2946 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ 2947 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ 2948 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ 2949 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ 2950 2951 /* Bit 4 : Protection enable for region 36. */ 2952 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ 2953 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ 2954 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ 2955 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ 2956 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ 2957 2958 /* Bit 3 : Protection enable for region 35. */ 2959 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ 2960 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ 2961 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ 2962 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ 2963 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ 2964 2965 /* Bit 2 : Protection enable for region 34. */ 2966 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ 2967 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ 2968 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ 2969 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ 2970 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ 2971 2972 /* Bit 1 : Protection enable for region 33. */ 2973 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ 2974 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ 2975 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ 2976 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ 2977 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ 2978 2979 /* Bit 0 : Protection enable for region 32. */ 2980 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ 2981 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ 2982 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ 2983 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ 2984 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ 2985 2986 /* Register: MPU_DISABLEINDEBUG */ 2987 /* Description: Disable erase and write protection mechanism in debug mode. */ 2988 2989 /* Bit 0 : Disable protection mechanism in debug mode. */ 2990 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ 2991 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ 2992 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ 2993 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ 2994 2995 /* Register: MPU_PROTBLOCKSIZE */ 2996 /* Description: Erase and write protection block size. */ 2997 2998 /* Bits 1..0 : Erase and write protection block size. */ 2999 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ 3000 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ 3001 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ 3002 3003 3004 /* Peripheral: NVMC */ 3005 /* Description: Non Volatile Memory Controller. */ 3006 3007 /* Register: NVMC_READY */ 3008 /* Description: Ready flag. */ 3009 3010 /* Bit 0 : NVMC ready. */ 3011 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 3012 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 3013 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ 3014 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ 3015 3016 /* Register: NVMC_CONFIG */ 3017 /* Description: Configuration register. */ 3018 3019 /* Bits 1..0 : Program write enable. */ 3020 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 3021 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 3022 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ 3023 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ 3024 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ 3025 3026 /* Register: NVMC_ERASEALL */ 3027 /* Description: Register for erasing all non-volatile user memory. */ 3028 3029 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ 3030 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 3031 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 3032 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ 3033 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ 3034 3035 /* Register: NVMC_ERASEUICR */ 3036 /* Description: Register for start erasing User Information Congfiguration Registers. */ 3037 3038 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */ 3039 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ 3040 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ 3041 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ 3042 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ 3043 3044 3045 /* Peripheral: POWER */ 3046 /* Description: Power Control. */ 3047 3048 /* Register: POWER_INTENSET */ 3049 /* Description: Interrupt enable set register. */ 3050 3051 /* Bit 2 : Enable interrupt on POFWARN event. */ 3052 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 3053 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 3054 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ 3055 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ 3056 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ 3057 3058 /* Register: POWER_INTENCLR */ 3059 /* Description: Interrupt enable clear register. */ 3060 3061 /* Bit 2 : Disable interrupt on POFWARN event. */ 3062 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 3063 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 3064 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ 3065 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ 3066 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ 3067 3068 /* Register: POWER_RESETREAS */ 3069 /* Description: Reset reason. */ 3070 3071 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ 3072 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ 3073 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 3074 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ 3075 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ 3076 3077 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ 3078 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ 3079 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 3080 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ 3081 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ 3082 3083 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ 3084 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ 3085 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 3086 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ 3087 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ 3088 3089 /* Bit 3 : Reset from CPU lock-up detected. */ 3090 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ 3091 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 3092 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ 3093 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ 3094 3095 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ 3096 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ 3097 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 3098 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ 3099 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ 3100 3101 /* Bit 1 : Reset from watchdog detected. */ 3102 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 3103 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 3104 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ 3105 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ 3106 3107 /* Bit 0 : Reset from pin-reset detected. */ 3108 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 3109 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 3110 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ 3111 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ 3112 3113 /* Register: POWER_RAMSTATUS */ 3114 /* Description: Ram status register. */ 3115 3116 /* Bit 3 : RAM block 3 status. */ 3117 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ 3118 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ 3119 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ 3120 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ 3121 3122 /* Bit 2 : RAM block 2 status. */ 3123 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ 3124 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ 3125 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ 3126 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ 3127 3128 /* Bit 1 : RAM block 1 status. */ 3129 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ 3130 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ 3131 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ 3132 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ 3133 3134 /* Bit 0 : RAM block 0 status. */ 3135 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ 3136 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ 3137 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ 3138 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ 3139 3140 /* Register: POWER_SYSTEMOFF */ 3141 /* Description: System off register. */ 3142 3143 /* Bit 0 : Enter system off mode. */ 3144 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 3145 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 3146 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ 3147 3148 /* Register: POWER_POFCON */ 3149 /* Description: Power failure configuration. */ 3150 3151 /* Bits 2..1 : Set threshold level. */ 3152 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ 3153 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 3154 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ 3155 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ 3156 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ 3157 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ 3158 3159 /* Bit 0 : Power failure comparator enable. */ 3160 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ 3161 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ 3162 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ 3163 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ 3164 3165 /* Register: POWER_GPREGRET */ 3166 /* Description: General purpose retention register. This register is a retained register. */ 3167 3168 /* Bits 7..0 : General purpose retention register. */ 3169 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 3170 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 3171 3172 /* Register: POWER_RAMON */ 3173 /* Description: Ram on/off. */ 3174 3175 /* Bit 17 : RAM block 1 behaviour in OFF mode. */ 3176 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ 3177 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ 3178 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ 3179 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ 3180 3181 /* Bit 16 : RAM block 0 behaviour in OFF mode. */ 3182 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ 3183 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ 3184 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ 3185 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ 3186 3187 /* Bit 1 : RAM block 1 behaviour in ON mode. */ 3188 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ 3189 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ 3190 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ 3191 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ 3192 3193 /* Bit 0 : RAM block 0 behaviour in ON mode. */ 3194 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ 3195 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ 3196 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ 3197 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ 3198 3199 /* Register: POWER_RESET */ 3200 /* Description: Pin reset functionality configuration register. This register is a retained register. */ 3201 3202 /* Bit 0 : Enable or disable pin reset in debug interface mode. */ 3203 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 3204 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 3205 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ 3206 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ 3207 3208 /* Register: POWER_RAMONB */ 3209 /* Description: Ram on/off. */ 3210 3211 /* Bit 17 : RAM block 3 behaviour in OFF mode. */ 3212 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ 3213 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ 3214 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ 3215 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ 3216 3217 /* Bit 16 : RAM block 2 behaviour in OFF mode. */ 3218 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ 3219 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ 3220 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ 3221 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ 3222 3223 /* Bit 1 : RAM block 3 behaviour in ON mode. */ 3224 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ 3225 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ 3226 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ 3227 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ 3228 3229 /* Bit 0 : RAM block 2 behaviour in ON mode. */ 3230 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ 3231 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ 3232 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ 3233 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ 3234 3235 /* Register: POWER_DCDCEN */ 3236 /* Description: DCDC converter enable configuration register. */ 3237 3238 /* Bit 0 : Enable DCDC converter. */ 3239 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 3240 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 3241 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ 3242 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ 3243 3244 /* Register: POWER_DCDCFORCE */ 3245 /* Description: DCDC power-up force register. */ 3246 3247 /* Bit 1 : DCDC power-up force on. */ 3248 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ 3249 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ 3250 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ 3251 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ 3252 3253 /* Bit 0 : DCDC power-up force off. */ 3254 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ 3255 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ 3256 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ 3257 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ 3258 3259 3260 /* Peripheral: PPI */ 3261 /* Description: PPI controller. */ 3262 3263 /* Register: PPI_CHEN */ 3264 /* Description: Channel enable. */ 3265 3266 /* Bit 31 : Enable PPI channel 31. */ 3267 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 3268 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 3269 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ 3270 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ 3271 3272 /* Bit 30 : Enable PPI channel 30. */ 3273 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ 3274 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ 3275 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ 3276 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ 3277 3278 /* Bit 29 : Enable PPI channel 29. */ 3279 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ 3280 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ 3281 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ 3282 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ 3283 3284 /* Bit 28 : Enable PPI channel 28. */ 3285 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ 3286 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ 3287 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ 3288 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ 3289 3290 /* Bit 27 : Enable PPI channel 27. */ 3291 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ 3292 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ 3293 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ 3294 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ 3295 3296 /* Bit 26 : Enable PPI channel 26. */ 3297 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ 3298 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ 3299 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ 3300 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ 3301 3302 /* Bit 25 : Enable PPI channel 25. */ 3303 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ 3304 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ 3305 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ 3306 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ 3307 3308 /* Bit 24 : Enable PPI channel 24. */ 3309 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ 3310 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ 3311 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ 3312 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ 3313 3314 /* Bit 23 : Enable PPI channel 23. */ 3315 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ 3316 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ 3317 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ 3318 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ 3319 3320 /* Bit 22 : Enable PPI channel 22. */ 3321 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ 3322 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ 3323 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ 3324 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ 3325 3326 /* Bit 21 : Enable PPI channel 21. */ 3327 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ 3328 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ 3329 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ 3330 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ 3331 3332 /* Bit 20 : Enable PPI channel 20. */ 3333 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ 3334 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ 3335 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ 3336 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ 3337 3338 /* Bit 15 : Enable PPI channel 15. */ 3339 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3340 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 3341 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ 3342 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ 3343 3344 /* Bit 14 : Enable PPI channel 14. */ 3345 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3346 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 3347 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ 3348 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ 3349 3350 /* Bit 13 : Enable PPI channel 13. */ 3351 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3352 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 3353 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ 3354 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ 3355 3356 /* Bit 12 : Enable PPI channel 12. */ 3357 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3358 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 3359 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ 3360 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ 3361 3362 /* Bit 11 : Enable PPI channel 11. */ 3363 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3364 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 3365 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ 3366 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ 3367 3368 /* Bit 10 : Enable PPI channel 10. */ 3369 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3370 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 3371 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ 3372 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ 3373 3374 /* Bit 9 : Enable PPI channel 9. */ 3375 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3376 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 3377 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ 3378 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ 3379 3380 /* Bit 8 : Enable PPI channel 8. */ 3381 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3382 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 3383 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ 3384 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ 3385 3386 /* Bit 7 : Enable PPI channel 7. */ 3387 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3388 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 3389 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ 3390 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ 3391 3392 /* Bit 6 : Enable PPI channel 6. */ 3393 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3394 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 3395 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ 3396 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ 3397 3398 /* Bit 5 : Enable PPI channel 5. */ 3399 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3400 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 3401 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ 3402 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ 3403 3404 /* Bit 4 : Enable PPI channel 4. */ 3405 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3406 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 3407 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ 3408 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ 3409 3410 /* Bit 3 : Enable PPI channel 3. */ 3411 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3412 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 3413 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ 3414 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ 3415 3416 /* Bit 2 : Enable PPI channel 2. */ 3417 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3418 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 3419 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ 3420 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ 3421 3422 /* Bit 1 : Enable PPI channel 1. */ 3423 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3424 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 3425 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ 3426 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ 3427 3428 /* Bit 0 : Enable PPI channel 0. */ 3429 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3430 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 3431 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ 3432 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ 3433 3434 /* Register: PPI_CHENSET */ 3435 /* Description: Channel enable set. */ 3436 3437 /* Bit 31 : Enable PPI channel 31. */ 3438 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 3439 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 3440 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ 3441 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ 3442 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ 3443 3444 /* Bit 30 : Enable PPI channel 30. */ 3445 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ 3446 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ 3447 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ 3448 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ 3449 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ 3450 3451 /* Bit 29 : Enable PPI channel 29. */ 3452 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ 3453 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ 3454 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ 3455 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ 3456 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ 3457 3458 /* Bit 28 : Enable PPI channel 28. */ 3459 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ 3460 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ 3461 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ 3462 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ 3463 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ 3464 3465 /* Bit 27 : Enable PPI channel 27. */ 3466 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ 3467 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ 3468 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ 3469 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ 3470 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ 3471 3472 /* Bit 26 : Enable PPI channel 26. */ 3473 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ 3474 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ 3475 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ 3476 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ 3477 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ 3478 3479 /* Bit 25 : Enable PPI channel 25. */ 3480 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ 3481 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ 3482 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ 3483 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ 3484 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ 3485 3486 /* Bit 24 : Enable PPI channel 24. */ 3487 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ 3488 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ 3489 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ 3490 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ 3491 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ 3492 3493 /* Bit 23 : Enable PPI channel 23. */ 3494 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ 3495 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ 3496 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ 3497 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ 3498 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ 3499 3500 /* Bit 22 : Enable PPI channel 22. */ 3501 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ 3502 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ 3503 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ 3504 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ 3505 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ 3506 3507 /* Bit 21 : Enable PPI channel 21. */ 3508 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ 3509 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ 3510 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ 3511 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ 3512 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ 3513 3514 /* Bit 20 : Enable PPI channel 20. */ 3515 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ 3516 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ 3517 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ 3518 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ 3519 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ 3520 3521 /* Bit 15 : Enable PPI channel 15. */ 3522 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3523 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 3524 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ 3525 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ 3526 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ 3527 3528 /* Bit 14 : Enable PPI channel 14. */ 3529 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3530 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 3531 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ 3532 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ 3533 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ 3534 3535 /* Bit 13 : Enable PPI channel 13. */ 3536 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3537 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 3538 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ 3539 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ 3540 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ 3541 3542 /* Bit 12 : Enable PPI channel 12. */ 3543 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3544 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 3545 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ 3546 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ 3547 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ 3548 3549 /* Bit 11 : Enable PPI channel 11. */ 3550 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3551 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 3552 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ 3553 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ 3554 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ 3555 3556 /* Bit 10 : Enable PPI channel 10. */ 3557 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3558 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 3559 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ 3560 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ 3561 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ 3562 3563 /* Bit 9 : Enable PPI channel 9. */ 3564 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3565 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 3566 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ 3567 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ 3568 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ 3569 3570 /* Bit 8 : Enable PPI channel 8. */ 3571 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3572 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 3573 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ 3574 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ 3575 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ 3576 3577 /* Bit 7 : Enable PPI channel 7. */ 3578 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3579 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 3580 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ 3581 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ 3582 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ 3583 3584 /* Bit 6 : Enable PPI channel 6. */ 3585 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3586 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 3587 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ 3588 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ 3589 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ 3590 3591 /* Bit 5 : Enable PPI channel 5. */ 3592 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3593 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 3594 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ 3595 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ 3596 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ 3597 3598 /* Bit 4 : Enable PPI channel 4. */ 3599 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3600 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 3601 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ 3602 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ 3603 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ 3604 3605 /* Bit 3 : Enable PPI channel 3. */ 3606 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3607 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 3608 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ 3609 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ 3610 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ 3611 3612 /* Bit 2 : Enable PPI channel 2. */ 3613 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3614 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 3615 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ 3616 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ 3617 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ 3618 3619 /* Bit 1 : Enable PPI channel 1. */ 3620 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3621 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 3622 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ 3623 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ 3624 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ 3625 3626 /* Bit 0 : Enable PPI channel 0. */ 3627 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3628 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 3629 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ 3630 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ 3631 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ 3632 3633 /* Register: PPI_CHENCLR */ 3634 /* Description: Channel enable clear. */ 3635 3636 /* Bit 31 : Disable PPI channel 31. */ 3637 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 3638 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 3639 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ 3640 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ 3641 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ 3642 3643 /* Bit 30 : Disable PPI channel 30. */ 3644 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ 3645 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ 3646 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ 3647 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ 3648 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ 3649 3650 /* Bit 29 : Disable PPI channel 29. */ 3651 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ 3652 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ 3653 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ 3654 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ 3655 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ 3656 3657 /* Bit 28 : Disable PPI channel 28. */ 3658 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ 3659 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ 3660 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ 3661 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ 3662 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ 3663 3664 /* Bit 27 : Disable PPI channel 27. */ 3665 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ 3666 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ 3667 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ 3668 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ 3669 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ 3670 3671 /* Bit 26 : Disable PPI channel 26. */ 3672 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ 3673 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ 3674 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ 3675 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ 3676 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ 3677 3678 /* Bit 25 : Disable PPI channel 25. */ 3679 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ 3680 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ 3681 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ 3682 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ 3683 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ 3684 3685 /* Bit 24 : Disable PPI channel 24. */ 3686 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ 3687 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ 3688 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ 3689 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ 3690 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ 3691 3692 /* Bit 23 : Disable PPI channel 23. */ 3693 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ 3694 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ 3695 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ 3696 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ 3697 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ 3698 3699 /* Bit 22 : Disable PPI channel 22. */ 3700 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ 3701 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ 3702 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ 3703 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ 3704 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ 3705 3706 /* Bit 21 : Disable PPI channel 21. */ 3707 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ 3708 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ 3709 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ 3710 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ 3711 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ 3712 3713 /* Bit 20 : Disable PPI channel 20. */ 3714 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ 3715 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ 3716 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ 3717 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ 3718 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ 3719 3720 /* Bit 15 : Disable PPI channel 15. */ 3721 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3722 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 3723 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ 3724 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ 3725 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ 3726 3727 /* Bit 14 : Disable PPI channel 14. */ 3728 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3729 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 3730 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ 3731 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ 3732 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ 3733 3734 /* Bit 13 : Disable PPI channel 13. */ 3735 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3736 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 3737 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ 3738 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ 3739 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ 3740 3741 /* Bit 12 : Disable PPI channel 12. */ 3742 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3743 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 3744 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ 3745 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ 3746 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ 3747 3748 /* Bit 11 : Disable PPI channel 11. */ 3749 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3750 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 3751 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ 3752 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ 3753 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ 3754 3755 /* Bit 10 : Disable PPI channel 10. */ 3756 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3757 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 3758 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ 3759 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ 3760 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ 3761 3762 /* Bit 9 : Disable PPI channel 9. */ 3763 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3764 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 3765 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ 3766 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ 3767 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ 3768 3769 /* Bit 8 : Disable PPI channel 8. */ 3770 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3771 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 3772 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ 3773 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ 3774 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ 3775 3776 /* Bit 7 : Disable PPI channel 7. */ 3777 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3778 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 3779 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ 3780 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ 3781 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ 3782 3783 /* Bit 6 : Disable PPI channel 6. */ 3784 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3785 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 3786 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ 3787 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ 3788 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ 3789 3790 /* Bit 5 : Disable PPI channel 5. */ 3791 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3792 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 3793 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ 3794 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ 3795 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ 3796 3797 /* Bit 4 : Disable PPI channel 4. */ 3798 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3799 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 3800 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ 3801 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ 3802 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ 3803 3804 /* Bit 3 : Disable PPI channel 3. */ 3805 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3806 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 3807 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ 3808 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ 3809 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ 3810 3811 /* Bit 2 : Disable PPI channel 2. */ 3812 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3813 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 3814 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ 3815 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ 3816 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ 3817 3818 /* Bit 1 : Disable PPI channel 1. */ 3819 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3820 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 3821 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ 3822 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ 3823 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ 3824 3825 /* Bit 0 : Disable PPI channel 0. */ 3826 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3827 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 3828 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ 3829 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ 3830 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ 3831 3832 /* Register: PPI_CHG */ 3833 /* Description: Channel group configuration. */ 3834 3835 /* Bit 31 : Include CH31 in channel group. */ 3836 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 3837 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 3838 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ 3839 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ 3840 3841 /* Bit 30 : Include CH30 in channel group. */ 3842 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ 3843 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ 3844 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ 3845 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ 3846 3847 /* Bit 29 : Include CH29 in channel group. */ 3848 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ 3849 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ 3850 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ 3851 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ 3852 3853 /* Bit 28 : Include CH28 in channel group. */ 3854 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ 3855 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ 3856 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ 3857 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ 3858 3859 /* Bit 27 : Include CH27 in channel group. */ 3860 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ 3861 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ 3862 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ 3863 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ 3864 3865 /* Bit 26 : Include CH26 in channel group. */ 3866 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ 3867 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ 3868 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ 3869 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ 3870 3871 /* Bit 25 : Include CH25 in channel group. */ 3872 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ 3873 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ 3874 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ 3875 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ 3876 3877 /* Bit 24 : Include CH24 in channel group. */ 3878 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ 3879 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ 3880 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ 3881 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ 3882 3883 /* Bit 23 : Include CH23 in channel group. */ 3884 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ 3885 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ 3886 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ 3887 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ 3888 3889 /* Bit 22 : Include CH22 in channel group. */ 3890 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ 3891 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ 3892 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ 3893 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ 3894 3895 /* Bit 21 : Include CH21 in channel group. */ 3896 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ 3897 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ 3898 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ 3899 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ 3900 3901 /* Bit 20 : Include CH20 in channel group. */ 3902 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ 3903 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ 3904 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ 3905 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ 3906 3907 /* Bit 15 : Include CH15 in channel group. */ 3908 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3909 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 3910 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ 3911 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ 3912 3913 /* Bit 14 : Include CH14 in channel group. */ 3914 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3915 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 3916 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ 3917 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ 3918 3919 /* Bit 13 : Include CH13 in channel group. */ 3920 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3921 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 3922 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ 3923 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ 3924 3925 /* Bit 12 : Include CH12 in channel group. */ 3926 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3927 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 3928 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ 3929 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ 3930 3931 /* Bit 11 : Include CH11 in channel group. */ 3932 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3933 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 3934 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ 3935 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ 3936 3937 /* Bit 10 : Include CH10 in channel group. */ 3938 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3939 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 3940 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ 3941 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ 3942 3943 /* Bit 9 : Include CH9 in channel group. */ 3944 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3945 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 3946 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ 3947 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ 3948 3949 /* Bit 8 : Include CH8 in channel group. */ 3950 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3951 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 3952 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ 3953 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ 3954 3955 /* Bit 7 : Include CH7 in channel group. */ 3956 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3957 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 3958 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ 3959 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ 3960 3961 /* Bit 6 : Include CH6 in channel group. */ 3962 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3963 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 3964 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ 3965 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ 3966 3967 /* Bit 5 : Include CH5 in channel group. */ 3968 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3969 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 3970 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ 3971 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ 3972 3973 /* Bit 4 : Include CH4 in channel group. */ 3974 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3975 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 3976 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ 3977 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ 3978 3979 /* Bit 3 : Include CH3 in channel group. */ 3980 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3981 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 3982 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ 3983 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ 3984 3985 /* Bit 2 : Include CH2 in channel group. */ 3986 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3987 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 3988 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ 3989 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ 3990 3991 /* Bit 1 : Include CH1 in channel group. */ 3992 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3993 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 3994 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ 3995 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ 3996 3997 /* Bit 0 : Include CH0 in channel group. */ 3998 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3999 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 4000 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ 4001 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ 4002 4003 4004 /* Peripheral: QDEC */ 4005 /* Description: Rotary decoder. */ 4006 4007 /* Register: QDEC_SHORTS */ 4008 /* Description: Shortcuts for the QDEC. */ 4009 4010 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ 4011 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ 4012 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ 4013 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 4014 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 4015 4016 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ 4017 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ 4018 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ 4019 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ 4020 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ 4021 4022 /* Register: QDEC_INTENSET */ 4023 /* Description: Interrupt enable set register. */ 4024 4025 /* Bit 2 : Enable interrupt on ACCOF event. */ 4026 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 4027 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 4028 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ 4029 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ 4030 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ 4031 4032 /* Bit 1 : Enable interrupt on REPORTRDY event. */ 4033 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 4034 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 4035 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ 4036 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ 4037 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ 4038 4039 /* Bit 0 : Enable interrupt on SAMPLERDY event. */ 4040 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 4041 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 4042 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ 4043 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ 4044 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ 4045 4046 /* Register: QDEC_INTENCLR */ 4047 /* Description: Interrupt enable clear register. */ 4048 4049 /* Bit 2 : Disable interrupt on ACCOF event. */ 4050 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 4051 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 4052 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ 4053 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ 4054 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ 4055 4056 /* Bit 1 : Disable interrupt on REPORTRDY event. */ 4057 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 4058 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 4059 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ 4060 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ 4061 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ 4062 4063 /* Bit 0 : Disable interrupt on SAMPLERDY event. */ 4064 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 4065 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 4066 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ 4067 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ 4068 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ 4069 4070 /* Register: QDEC_ENABLE */ 4071 /* Description: Enable the QDEC. */ 4072 4073 /* Bit 0 : Enable or disable QDEC. */ 4074 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 4075 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 4076 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ 4077 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ 4078 4079 /* Register: QDEC_LEDPOL */ 4080 /* Description: LED output pin polarity. */ 4081 4082 /* Bit 0 : LED output pin polarity. */ 4083 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ 4084 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ 4085 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ 4086 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ 4087 4088 /* Register: QDEC_SAMPLEPER */ 4089 /* Description: Sample period. */ 4090 4091 /* Bits 2..0 : Sample period. */ 4092 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ 4093 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ 4094 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ 4095 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ 4096 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ 4097 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ 4098 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ 4099 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ 4100 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ 4101 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ 4102 4103 /* Register: QDEC_SAMPLE */ 4104 /* Description: Motion sample value. */ 4105 4106 /* Bits 31..0 : Last sample taken in compliment to 2. */ 4107 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ 4108 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ 4109 4110 /* Register: QDEC_REPORTPER */ 4111 /* Description: Number of samples to generate an EVENT_REPORTRDY. */ 4112 4113 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ 4114 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ 4115 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ 4116 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ 4117 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ 4118 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ 4119 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ 4120 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ 4121 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ 4122 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ 4123 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ 4124 4125 /* Register: QDEC_DBFEN */ 4126 /* Description: Enable debouncer input filters. */ 4127 4128 /* Bit 0 : Enable debounce input filters. */ 4129 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ 4130 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ 4131 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ 4132 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ 4133 4134 /* Register: QDEC_LEDPRE */ 4135 /* Description: Time LED is switched ON before the sample. */ 4136 4137 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ 4138 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ 4139 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ 4140 4141 /* Register: QDEC_ACCDBL */ 4142 /* Description: Accumulated double (error) transitions register. */ 4143 4144 /* Bits 3..0 : Accumulated double (error) transitions. */ 4145 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ 4146 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ 4147 4148 /* Register: QDEC_ACCDBLREAD */ 4149 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ 4150 4151 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ 4152 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ 4153 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ 4154 4155 /* Register: QDEC_POWER */ 4156 /* Description: Peripheral power control. */ 4157 4158 /* Bit 0 : Peripheral power control. */ 4159 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 4160 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 4161 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 4162 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 4163 4164 4165 /* Peripheral: RADIO */ 4166 /* Description: The radio. */ 4167 4168 /* Register: RADIO_SHORTS */ 4169 /* Description: Shortcuts for the radio. */ 4170 4171 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ 4172 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 4173 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 4174 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ 4175 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ 4176 4177 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ 4178 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 4179 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 4180 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ 4181 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ 4182 4183 /* Bit 5 : Shortcut between END event and START task. */ 4184 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 4185 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 4186 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ 4187 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ 4188 4189 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ 4190 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 4191 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 4192 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ 4193 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ 4194 4195 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */ 4196 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 4197 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 4198 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ 4199 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ 4200 4201 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */ 4202 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 4203 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 4204 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ 4205 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ 4206 4207 /* Bit 1 : Shortcut between END event and DISABLE task. */ 4208 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 4209 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 4210 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ 4211 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ 4212 4213 /* Bit 0 : Shortcut between READY event and START task. */ 4214 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 4215 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 4216 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ 4217 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ 4218 4219 /* Register: RADIO_INTENSET */ 4220 /* Description: Interrupt enable set register. */ 4221 4222 /* Bit 10 : Enable interrupt on BCMATCH event. */ 4223 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 4224 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 4225 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 4226 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 4227 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ 4228 4229 /* Bit 7 : Enable interrupt on RSSIEND event. */ 4230 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 4231 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 4232 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ 4233 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ 4234 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ 4235 4236 /* Bit 6 : Enable interrupt on DEVMISS event. */ 4237 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 4238 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 4239 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ 4240 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ 4241 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ 4242 4243 /* Bit 5 : Enable interrupt on DEVMATCH event. */ 4244 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 4245 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 4246 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 4247 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 4248 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ 4249 4250 /* Bit 4 : Enable interrupt on DISABLED event. */ 4251 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 4252 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 4253 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ 4254 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ 4255 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ 4256 4257 /* Bit 3 : Enable interrupt on END event. */ 4258 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 4259 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 4260 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 4261 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 4262 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 4263 4264 /* Bit 2 : Enable interrupt on PAYLOAD event. */ 4265 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 4266 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 4267 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ 4268 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ 4269 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ 4270 4271 /* Bit 1 : Enable interrupt on ADDRESS event. */ 4272 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 4273 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 4274 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ 4275 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ 4276 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ 4277 4278 /* Bit 0 : Enable interrupt on READY event. */ 4279 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 4280 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 4281 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 4282 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 4283 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 4284 4285 /* Register: RADIO_INTENCLR */ 4286 /* Description: Interrupt enable clear register. */ 4287 4288 /* Bit 10 : Disable interrupt on BCMATCH event. */ 4289 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 4290 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 4291 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 4292 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 4293 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ 4294 4295 /* Bit 7 : Disable interrupt on RSSIEND event. */ 4296 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 4297 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 4298 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ 4299 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ 4300 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ 4301 4302 /* Bit 6 : Disable interrupt on DEVMISS event. */ 4303 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 4304 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 4305 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ 4306 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ 4307 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ 4308 4309 /* Bit 5 : Disable interrupt on DEVMATCH event. */ 4310 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 4311 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 4312 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 4313 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 4314 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ 4315 4316 /* Bit 4 : Disable interrupt on DISABLED event. */ 4317 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 4318 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 4319 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ 4320 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ 4321 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ 4322 4323 /* Bit 3 : Disable interrupt on END event. */ 4324 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 4325 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 4326 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 4327 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 4328 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 4329 4330 /* Bit 2 : Disable interrupt on PAYLOAD event. */ 4331 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 4332 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 4333 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ 4334 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ 4335 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ 4336 4337 /* Bit 1 : Disable interrupt on ADDRESS event. */ 4338 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 4339 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 4340 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ 4341 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ 4342 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ 4343 4344 /* Bit 0 : Disable interrupt on READY event. */ 4345 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 4346 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 4347 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 4348 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 4349 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 4350 4351 /* Register: RADIO_CRCSTATUS */ 4352 /* Description: CRC status of received packet. */ 4353 4354 /* Bit 0 : CRC status of received packet. */ 4355 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 4356 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 4357 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ 4358 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ 4359 4360 /* Register: RADIO_RXMATCH */ 4361 /* Description: Received address. */ 4362 4363 /* Bits 2..0 : Logical address in which previous packet was received. */ 4364 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 4365 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 4366 4367 /* Register: RADIO_RXCRC */ 4368 /* Description: Received CRC. */ 4369 4370 /* Bits 23..0 : CRC field of previously received packet. */ 4371 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 4372 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 4373 4374 /* Register: RADIO_DAI */ 4375 /* Description: Device address match index. */ 4376 4377 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ 4378 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 4379 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 4380 4381 /* Register: RADIO_FREQUENCY */ 4382 /* Description: Frequency. */ 4383 4384 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ 4385 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 4386 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 4387 4388 /* Register: RADIO_TXPOWER */ 4389 /* Description: Output power. */ 4390 4391 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */ 4392 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 4393 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 4394 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ 4395 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ 4396 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ 4397 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ 4398 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ 4399 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ 4400 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ 4401 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ 4402 4403 /* Register: RADIO_MODE */ 4404 /* Description: Data rate and modulation. */ 4405 4406 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ 4407 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 4408 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 4409 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ 4410 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ 4411 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ 4412 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ 4413 4414 /* Register: RADIO_PCNF0 */ 4415 /* Description: Packet configuration 0. */ 4416 4417 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ 4418 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 4419 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 4420 4421 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ 4422 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 4423 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 4424 4425 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ 4426 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 4427 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 4428 4429 /* Register: RADIO_PCNF1 */ 4430 /* Description: Packet configuration 1. */ 4431 4432 /* Bit 25 : Packet whitening enable. */ 4433 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 4434 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 4435 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ 4436 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ 4437 4438 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */ 4439 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 4440 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 4441 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ 4442 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 4443 4444 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ 4445 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 4446 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 4447 4448 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ 4449 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 4450 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 4451 4452 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */ 4453 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 4454 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 4455 4456 /* Register: RADIO_PREFIX0 */ 4457 /* Description: Prefixes bytes for logical addresses 0 to 3. */ 4458 4459 /* Bits 31..24 : Address prefix 3. Decision point: START task. */ 4460 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 4461 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 4462 4463 /* Bits 23..16 : Address prefix 2. Decision point: START task. */ 4464 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 4465 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 4466 4467 /* Bits 15..8 : Address prefix 1. Decision point: START task. */ 4468 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 4469 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 4470 4471 /* Bits 7..0 : Address prefix 0. Decision point: START task. */ 4472 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 4473 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 4474 4475 /* Register: RADIO_PREFIX1 */ 4476 /* Description: Prefixes bytes for logical addresses 4 to 7. */ 4477 4478 /* Bits 31..24 : Address prefix 7. Decision point: START task. */ 4479 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 4480 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 4481 4482 /* Bits 23..16 : Address prefix 6. Decision point: START task. */ 4483 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 4484 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 4485 4486 /* Bits 15..8 : Address prefix 5. Decision point: START task. */ 4487 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 4488 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 4489 4490 /* Bits 7..0 : Address prefix 4. Decision point: START task. */ 4491 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 4492 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 4493 4494 /* Register: RADIO_TXADDRESS */ 4495 /* Description: Transmit address select. */ 4496 4497 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ 4498 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 4499 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 4500 4501 /* Register: RADIO_RXADDRESSES */ 4502 /* Description: Receive address select. */ 4503 4504 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ 4505 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 4506 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 4507 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ 4508 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ 4509 4510 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ 4511 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 4512 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 4513 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ 4514 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ 4515 4516 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ 4517 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 4518 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 4519 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ 4520 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ 4521 4522 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ 4523 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 4524 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 4525 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ 4526 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ 4527 4528 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ 4529 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 4530 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 4531 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ 4532 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ 4533 4534 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ 4535 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 4536 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 4537 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ 4538 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ 4539 4540 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ 4541 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 4542 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 4543 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ 4544 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ 4545 4546 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ 4547 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 4548 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 4549 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ 4550 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ 4551 4552 /* Register: RADIO_CRCCNF */ 4553 /* Description: CRC configuration. */ 4554 4555 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ 4556 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 4557 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 4558 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ 4559 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ 4560 4561 /* Bits 1..0 : CRC length. Decision point: START task. */ 4562 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 4563 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 4564 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ 4565 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ 4566 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ 4567 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ 4568 4569 /* Register: RADIO_CRCPOLY */ 4570 /* Description: CRC polynomial. */ 4571 4572 /* Bits 23..0 : CRC polynomial. Decision point: START task. */ 4573 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 4574 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 4575 4576 /* Register: RADIO_CRCINIT */ 4577 /* Description: CRC initial value. */ 4578 4579 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ 4580 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 4581 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 4582 4583 /* Register: RADIO_TEST */ 4584 /* Description: Test features enable register. */ 4585 4586 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ 4587 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ 4588 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ 4589 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ 4590 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ 4591 4592 /* Bit 0 : Constant carrier. Decision point: TXEN task. */ 4593 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ 4594 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ 4595 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ 4596 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ 4597 4598 /* Register: RADIO_TIFS */ 4599 /* Description: Inter Frame Spacing in microseconds. */ 4600 4601 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ 4602 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 4603 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 4604 4605 /* Register: RADIO_RSSISAMPLE */ 4606 /* Description: RSSI sample. */ 4607 4608 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ 4609 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 4610 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 4611 4612 /* Register: RADIO_STATE */ 4613 /* Description: Current radio state. */ 4614 4615 /* Bits 3..0 : Current radio state. */ 4616 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 4617 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 4618 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ 4619 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ 4620 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ 4621 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ 4622 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ 4623 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ 4624 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ 4625 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ 4626 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ 4627 4628 /* Register: RADIO_DATAWHITEIV */ 4629 /* Description: Data whitening initial value. */ 4630 4631 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ 4632 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 4633 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 4634 4635 /* Register: RADIO_DAP */ 4636 /* Description: Device address prefix. */ 4637 4638 /* Bits 15..0 : Device address prefix. */ 4639 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 4640 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 4641 4642 /* Register: RADIO_DACNF */ 4643 /* Description: Device address match configuration. */ 4644 4645 /* Bit 15 : TxAdd for device address 7. */ 4646 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 4647 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 4648 4649 /* Bit 14 : TxAdd for device address 6. */ 4650 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 4651 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 4652 4653 /* Bit 13 : TxAdd for device address 5. */ 4654 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 4655 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 4656 4657 /* Bit 12 : TxAdd for device address 4. */ 4658 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 4659 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 4660 4661 /* Bit 11 : TxAdd for device address 3. */ 4662 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 4663 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 4664 4665 /* Bit 10 : TxAdd for device address 2. */ 4666 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 4667 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 4668 4669 /* Bit 9 : TxAdd for device address 1. */ 4670 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 4671 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 4672 4673 /* Bit 8 : TxAdd for device address 0. */ 4674 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 4675 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 4676 4677 /* Bit 7 : Enable or disable device address matching using device address 7. */ 4678 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 4679 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 4680 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ 4681 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ 4682 4683 /* Bit 6 : Enable or disable device address matching using device address 6. */ 4684 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 4685 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 4686 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ 4687 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ 4688 4689 /* Bit 5 : Enable or disable device address matching using device address 5. */ 4690 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 4691 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 4692 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ 4693 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ 4694 4695 /* Bit 4 : Enable or disable device address matching using device address 4. */ 4696 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 4697 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 4698 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ 4699 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ 4700 4701 /* Bit 3 : Enable or disable device address matching using device address 3. */ 4702 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 4703 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 4704 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ 4705 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ 4706 4707 /* Bit 2 : Enable or disable device address matching using device address 2. */ 4708 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 4709 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 4710 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ 4711 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ 4712 4713 /* Bit 1 : Enable or disable device address matching using device address 1. */ 4714 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 4715 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 4716 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ 4717 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ 4718 4719 /* Bit 0 : Enable or disable device address matching using device address 0. */ 4720 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 4721 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 4722 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ 4723 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ 4724 4725 /* Register: RADIO_OVERRIDE0 */ 4726 /* Description: Trim value override register 0. */ 4727 4728 /* Bits 31..0 : Trim value override 0. */ 4729 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ 4730 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ 4731 4732 /* Register: RADIO_OVERRIDE1 */ 4733 /* Description: Trim value override register 1. */ 4734 4735 /* Bits 31..0 : Trim value override 1. */ 4736 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ 4737 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ 4738 4739 /* Register: RADIO_OVERRIDE2 */ 4740 /* Description: Trim value override register 2. */ 4741 4742 /* Bits 31..0 : Trim value override 2. */ 4743 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ 4744 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ 4745 4746 /* Register: RADIO_OVERRIDE3 */ 4747 /* Description: Trim value override register 3. */ 4748 4749 /* Bits 31..0 : Trim value override 3. */ 4750 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ 4751 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ 4752 4753 /* Register: RADIO_OVERRIDE4 */ 4754 /* Description: Trim value override register 4. */ 4755 4756 /* Bit 31 : Enable or disable override of default trim values. */ 4757 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ 4758 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 4759 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ 4760 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ 4761 4762 /* Bits 27..0 : Trim value override 4. */ 4763 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ 4764 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ 4765 4766 /* Register: RADIO_POWER */ 4767 /* Description: Peripheral power control. */ 4768 4769 /* Bit 0 : Peripheral power control. */ 4770 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 4771 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 4772 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 4773 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 4774 4775 4776 /* Peripheral: RNG */ 4777 /* Description: Random Number Generator. */ 4778 4779 /* Register: RNG_SHORTS */ 4780 /* Description: Shortcuts for the RNG. */ 4781 4782 /* Bit 0 : Shortcut between VALRDY event and STOP task. */ 4783 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 4784 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 4785 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 4786 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 4787 4788 /* Register: RNG_INTENSET */ 4789 /* Description: Interrupt enable set register */ 4790 4791 /* Bit 0 : Enable interrupt on VALRDY event. */ 4792 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 4793 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 4794 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ 4795 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ 4796 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ 4797 4798 /* Register: RNG_INTENCLR */ 4799 /* Description: Interrupt enable clear register */ 4800 4801 /* Bit 0 : Disable interrupt on VALRDY event. */ 4802 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 4803 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 4804 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ 4805 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ 4806 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ 4807 4808 /* Register: RNG_CONFIG */ 4809 /* Description: Configuration register. */ 4810 4811 /* Bit 0 : Digital error correction enable. */ 4812 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 4813 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 4814 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ 4815 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ 4816 4817 /* Register: RNG_VALUE */ 4818 /* Description: RNG random number. */ 4819 4820 /* Bits 7..0 : Generated random number. */ 4821 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 4822 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 4823 4824 /* Register: RNG_POWER */ 4825 /* Description: Peripheral power control. */ 4826 4827 /* Bit 0 : Peripheral power control. */ 4828 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 4829 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 4830 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 4831 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 4832 4833 4834 /* Peripheral: RTC */ 4835 /* Description: Real time counter 0. */ 4836 4837 /* Register: RTC_INTENSET */ 4838 /* Description: Interrupt enable set register. */ 4839 4840 /* Bit 19 : Enable interrupt on COMPARE[3] event. */ 4841 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4842 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4843 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 4844 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 4845 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ 4846 4847 /* Bit 18 : Enable interrupt on COMPARE[2] event. */ 4848 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 4849 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 4850 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 4851 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 4852 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ 4853 4854 /* Bit 17 : Enable interrupt on COMPARE[1] event. */ 4855 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 4856 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 4857 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 4858 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 4859 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ 4860 4861 /* Bit 16 : Enable interrupt on COMPARE[0] event. */ 4862 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4863 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4864 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 4865 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 4866 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ 4867 4868 /* Bit 1 : Enable interrupt on OVRFLW event. */ 4869 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4870 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4871 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ 4872 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ 4873 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ 4874 4875 /* Bit 0 : Enable interrupt on TICK event. */ 4876 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 4877 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 4878 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ 4879 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ 4880 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ 4881 4882 /* Register: RTC_INTENCLR */ 4883 /* Description: Interrupt enable clear register. */ 4884 4885 /* Bit 19 : Disable interrupt on COMPARE[3] event. */ 4886 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4887 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4888 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 4889 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 4890 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ 4891 4892 /* Bit 18 : Disable interrupt on COMPARE[2] event. */ 4893 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 4894 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 4895 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 4896 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 4897 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ 4898 4899 /* Bit 17 : Disable interrupt on COMPARE[1] event. */ 4900 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 4901 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 4902 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 4903 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 4904 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ 4905 4906 /* Bit 16 : Disable interrupt on COMPARE[0] event. */ 4907 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4908 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4909 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 4910 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 4911 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ 4912 4913 /* Bit 1 : Disable interrupt on OVRFLW event. */ 4914 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4915 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4916 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ 4917 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ 4918 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ 4919 4920 /* Bit 0 : Disable interrupt on TICK event. */ 4921 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 4922 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 4923 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ 4924 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ 4925 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ 4926 4927 /* Register: RTC_EVTEN */ 4928 /* Description: Configures event enable routing to PPI for each RTC event. */ 4929 4930 /* Bit 19 : COMPARE[3] event enable. */ 4931 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4932 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4933 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 4934 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 4935 4936 /* Bit 18 : COMPARE[2] event enable. */ 4937 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 4938 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 4939 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 4940 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 4941 4942 /* Bit 17 : COMPARE[1] event enable. */ 4943 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 4944 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 4945 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 4946 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 4947 4948 /* Bit 16 : COMPARE[0] event enable. */ 4949 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4950 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4951 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 4952 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 4953 4954 /* Bit 1 : OVRFLW event enable. */ 4955 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4956 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4957 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 4958 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 4959 4960 /* Bit 0 : TICK event enable. */ 4961 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 4962 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 4963 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ 4964 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ 4965 4966 /* Register: RTC_EVTENSET */ 4967 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ 4968 4969 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ 4970 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4971 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4972 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 4973 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 4974 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ 4975 4976 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ 4977 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 4978 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 4979 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 4980 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 4981 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ 4982 4983 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ 4984 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 4985 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 4986 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 4987 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 4988 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ 4989 4990 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ 4991 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4992 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4993 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 4994 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 4995 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ 4996 4997 /* Bit 1 : Enable routing to PPI of OVRFLW event. */ 4998 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4999 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5000 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 5001 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 5002 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ 5003 5004 /* Bit 0 : Enable routing to PPI of TICK event. */ 5005 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 5006 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 5007 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ 5008 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ 5009 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ 5010 5011 /* Register: RTC_EVTENCLR */ 5012 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ 5013 5014 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ 5015 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5016 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5017 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 5018 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 5019 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ 5020 5021 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ 5022 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5023 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5024 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 5025 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 5026 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ 5027 5028 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ 5029 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5030 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5031 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 5032 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 5033 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ 5034 5035 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ 5036 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5037 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5038 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 5039 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 5040 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ 5041 5042 /* Bit 1 : Disable routing to PPI of OVRFLW event. */ 5043 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5044 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5045 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 5046 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 5047 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ 5048 5049 /* Bit 0 : Disable routing to PPI of TICK event. */ 5050 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 5051 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 5052 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ 5053 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ 5054 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ 5055 5056 /* Register: RTC_COUNTER */ 5057 /* Description: Current COUNTER value. */ 5058 5059 /* Bits 23..0 : Counter value. */ 5060 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 5061 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 5062 5063 /* Register: RTC_PRESCALER */ 5064 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ 5065 5066 /* Bits 11..0 : RTC PRESCALER value. */ 5067 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5068 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5069 5070 /* Register: RTC_CC */ 5071 /* Description: Capture/compare registers. */ 5072 5073 /* Bits 23..0 : Compare value. */ 5074 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 5075 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 5076 5077 /* Register: RTC_POWER */ 5078 /* Description: Peripheral power control. */ 5079 5080 /* Bit 0 : Peripheral power control. */ 5081 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5082 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5083 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5084 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5085 5086 5087 /* Peripheral: SPI */ 5088 /* Description: SPI master 0. */ 5089 5090 /* Register: SPI_INTENSET */ 5091 /* Description: Interrupt enable set register. */ 5092 5093 /* Bit 2 : Enable interrupt on READY event. */ 5094 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ 5095 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 5096 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 5097 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 5098 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 5099 5100 /* Register: SPI_INTENCLR */ 5101 /* Description: Interrupt enable clear register. */ 5102 5103 /* Bit 2 : Disable interrupt on READY event. */ 5104 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ 5105 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 5106 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 5107 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 5108 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 5109 5110 /* Register: SPI_ENABLE */ 5111 /* Description: Enable SPI. */ 5112 5113 /* Bits 2..0 : Enable or disable SPI. */ 5114 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5115 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5116 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ 5117 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ 5118 5119 /* Register: SPI_RXD */ 5120 /* Description: RX data. */ 5121 5122 /* Bits 7..0 : RX data from last transfer. */ 5123 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 5124 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 5125 5126 /* Register: SPI_TXD */ 5127 /* Description: TX data. */ 5128 5129 /* Bits 7..0 : TX data for next transfer. */ 5130 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 5131 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 5132 5133 /* Register: SPI_FREQUENCY */ 5134 /* Description: SPI frequency */ 5135 5136 /* Bits 31..0 : SPI data rate. */ 5137 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 5138 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 5139 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ 5140 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ 5141 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ 5142 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ 5143 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ 5144 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ 5145 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ 5146 5147 /* Register: SPI_CONFIG */ 5148 /* Description: Configuration register. */ 5149 5150 /* Bit 2 : Serial clock (SCK) polarity. */ 5151 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 5152 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 5153 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 5154 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 5155 5156 /* Bit 1 : Serial clock (SCK) phase. */ 5157 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 5158 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 5159 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 5160 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 5161 5162 /* Bit 0 : Bit order. */ 5163 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 5164 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 5165 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 5166 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 5167 5168 /* Register: SPI_POWER */ 5169 /* Description: Peripheral power control. */ 5170 5171 /* Bit 0 : Peripheral power control. */ 5172 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5173 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5174 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5175 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5176 5177 5178 /* Peripheral: SPIS */ 5179 /* Description: SPI slave 1. */ 5180 5181 /* Register: SPIS_SHORTS */ 5182 /* Description: Shortcuts for SPIS. */ 5183 5184 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */ 5185 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 5186 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 5187 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ 5188 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ 5189 5190 /* Register: SPIS_INTENSET */ 5191 /* Description: Interrupt enable set register. */ 5192 5193 /* Bit 10 : Enable interrupt on ACQUIRED event. */ 5194 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 5195 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 5196 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ 5197 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ 5198 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ 5199 5200 /* Bit 4 : enable interrupt on ENDRX event. */ 5201 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 5202 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 5203 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ 5204 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ 5205 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ 5206 5207 /* Bit 1 : Enable interrupt on END event. */ 5208 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 5209 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 5210 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 5211 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 5212 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 5213 5214 /* Register: SPIS_INTENCLR */ 5215 /* Description: Interrupt enable clear register. */ 5216 5217 /* Bit 10 : Disable interrupt on ACQUIRED event. */ 5218 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 5219 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 5220 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ 5221 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ 5222 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ 5223 5224 /* Bit 4 : Disable interrupt on ENDRX event. */ 5225 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 5226 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 5227 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ 5228 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ 5229 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ 5230 5231 /* Bit 1 : Disable interrupt on END event. */ 5232 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 5233 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 5234 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 5235 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 5236 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 5237 5238 /* Register: SPIS_SEMSTAT */ 5239 /* Description: Semaphore status. */ 5240 5241 /* Bits 1..0 : Semaphore status. */ 5242 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 5243 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 5244 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ 5245 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ 5246 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ 5247 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ 5248 5249 /* Register: SPIS_STATUS */ 5250 /* Description: Status from last transaction. */ 5251 5252 /* Bit 1 : RX buffer overflow detected, and prevented. */ 5253 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 5254 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 5255 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ 5256 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ 5257 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ 5258 5259 /* Bit 0 : TX buffer overread detected, and prevented. */ 5260 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 5261 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 5262 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ 5263 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ 5264 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ 5265 5266 /* Register: SPIS_ENABLE */ 5267 /* Description: Enable SPIS. */ 5268 5269 /* Bits 2..0 : Enable or disable SPIS. */ 5270 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5271 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5272 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ 5273 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ 5274 5275 /* Register: SPIS_MAXRX */ 5276 /* Description: Maximum number of bytes in the receive buffer. */ 5277 5278 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */ 5279 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ 5280 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ 5281 5282 /* Register: SPIS_AMOUNTRX */ 5283 /* Description: Number of bytes received in last granted transaction. */ 5284 5285 /* Bits 7..0 : Number of bytes received in last granted transaction. */ 5286 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ 5287 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ 5288 5289 /* Register: SPIS_MAXTX */ 5290 /* Description: Maximum number of bytes in the transmit buffer. */ 5291 5292 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ 5293 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ 5294 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ 5295 5296 /* Register: SPIS_AMOUNTTX */ 5297 /* Description: Number of bytes transmitted in last granted transaction. */ 5298 5299 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ 5300 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ 5301 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ 5302 5303 /* Register: SPIS_CONFIG */ 5304 /* Description: Configuration register. */ 5305 5306 /* Bit 2 : Serial clock (SCK) polarity. */ 5307 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 5308 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 5309 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 5310 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 5311 5312 /* Bit 1 : Serial clock (SCK) phase. */ 5313 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 5314 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 5315 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 5316 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 5317 5318 /* Bit 0 : Bit order. */ 5319 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 5320 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 5321 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 5322 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 5323 5324 /* Register: SPIS_DEF */ 5325 /* Description: Default character. */ 5326 5327 /* Bits 7..0 : Default character. */ 5328 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 5329 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 5330 5331 /* Register: SPIS_ORC */ 5332 /* Description: Over-read character. */ 5333 5334 /* Bits 7..0 : Over-read character. */ 5335 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 5336 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 5337 5338 /* Register: SPIS_POWER */ 5339 /* Description: Peripheral power control. */ 5340 5341 /* Bit 0 : Peripheral power control. */ 5342 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5343 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5344 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5345 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5346 5347 5348 /* Peripheral: TEMP */ 5349 /* Description: Temperature Sensor. */ 5350 5351 /* Register: TEMP_INTENSET */ 5352 /* Description: Interrupt enable set register. */ 5353 5354 /* Bit 0 : Enable interrupt on DATARDY event. */ 5355 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 5356 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 5357 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ 5358 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ 5359 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ 5360 5361 /* Register: TEMP_INTENCLR */ 5362 /* Description: Interrupt enable clear register. */ 5363 5364 /* Bit 0 : Disable interrupt on DATARDY event. */ 5365 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 5366 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 5367 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ 5368 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ 5369 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ 5370 5371 /* Register: TEMP_POWER */ 5372 /* Description: Peripheral power control. */ 5373 5374 /* Bit 0 : Peripheral power control. */ 5375 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5376 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5377 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5378 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5379 5380 5381 /* Peripheral: TIMER */ 5382 /* Description: Timer 0. */ 5383 5384 /* Register: TIMER_SHORTS */ 5385 /* Description: Shortcuts for Timer. */ 5386 5387 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */ 5388 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 5389 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 5390 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 5391 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 5392 5393 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */ 5394 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 5395 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 5396 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 5397 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 5398 5399 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */ 5400 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 5401 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 5402 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 5403 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 5404 5405 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */ 5406 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 5407 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 5408 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 5409 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 5410 5411 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ 5412 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 5413 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 5414 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 5415 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 5416 5417 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ 5418 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 5419 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 5420 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 5421 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 5422 5423 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ 5424 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 5425 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 5426 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 5427 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 5428 5429 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ 5430 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 5431 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 5432 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 5433 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 5434 5435 /* Register: TIMER_INTENSET */ 5436 /* Description: Interrupt enable set register. */ 5437 5438 /* Bit 19 : Enable interrupt on COMPARE[3] */ 5439 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5440 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5441 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 5442 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 5443 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ 5444 5445 /* Bit 18 : Enable interrupt on COMPARE[2] */ 5446 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5447 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5448 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 5449 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 5450 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ 5451 5452 /* Bit 17 : Enable interrupt on COMPARE[1] */ 5453 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5454 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5455 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 5456 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 5457 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ 5458 5459 /* Bit 16 : Enable interrupt on COMPARE[0] */ 5460 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5461 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5462 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 5463 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 5464 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ 5465 5466 /* Register: TIMER_INTENCLR */ 5467 /* Description: Interrupt enable clear register. */ 5468 5469 /* Bit 19 : Disable interrupt on COMPARE[3] */ 5470 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5471 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5472 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 5473 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 5474 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ 5475 5476 /* Bit 18 : Disable interrupt on COMPARE[2] */ 5477 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5478 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5479 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 5480 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 5481 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ 5482 5483 /* Bit 17 : Disable interrupt on COMPARE[1] */ 5484 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5485 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5486 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 5487 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 5488 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ 5489 5490 /* Bit 16 : Disable interrupt on COMPARE[0] */ 5491 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5492 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5493 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 5494 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 5495 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ 5496 5497 /* Register: TIMER_MODE */ 5498 /* Description: Timer Mode selection. */ 5499 5500 /* Bit 0 : Select Normal or Counter mode. */ 5501 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 5502 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 5503 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ 5504 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ 5505 5506 /* Register: TIMER_BITMODE */ 5507 /* Description: Sets timer behaviour. */ 5508 5509 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ 5510 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 5511 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 5512 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ 5513 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ 5514 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ 5515 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ 5516 5517 /* Register: TIMER_PRESCALER */ 5518 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ 5519 5520 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ 5521 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5522 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5523 5524 /* Register: TIMER_POWER */ 5525 /* Description: Peripheral power control. */ 5526 5527 /* Bit 0 : Peripheral power control. */ 5528 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5529 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5530 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5531 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5532 5533 5534 /* Peripheral: TWI */ 5535 /* Description: Two-wire interface master 0. */ 5536 5537 /* Register: TWI_SHORTS */ 5538 /* Description: Shortcuts for TWI. */ 5539 5540 /* Bit 1 : Shortcut between BB event and the STOP task. */ 5541 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ 5542 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ 5543 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 5544 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 5545 5546 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */ 5547 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ 5548 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ 5549 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ 5550 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ 5551 5552 /* Register: TWI_INTENSET */ 5553 /* Description: Interrupt enable set register. */ 5554 5555 /* Bit 18 : Enable interrupt on SUSPENDED event. */ 5556 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 5557 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 5558 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ 5559 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ 5560 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ 5561 5562 /* Bit 14 : Enable interrupt on BB event. */ 5563 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ 5564 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ 5565 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ 5566 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ 5567 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ 5568 5569 /* Bit 9 : Enable interrupt on ERROR event. */ 5570 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 5571 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 5572 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 5573 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 5574 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 5575 5576 /* Bit 7 : Enable interrupt on TXDSENT event. */ 5577 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 5578 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 5579 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ 5580 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ 5581 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ 5582 5583 /* Bit 2 : Enable interrupt on READY event. */ 5584 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 5585 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 5586 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ 5587 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ 5588 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ 5589 5590 /* Bit 1 : Enable interrupt on STOPPED event. */ 5591 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5592 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5593 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 5594 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 5595 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ 5596 5597 /* Register: TWI_INTENCLR */ 5598 /* Description: Interrupt enable clear register. */ 5599 5600 /* Bit 18 : Disable interrupt on SUSPENDED event. */ 5601 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 5602 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 5603 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ 5604 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ 5605 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ 5606 5607 /* Bit 14 : Disable interrupt on BB event. */ 5608 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ 5609 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ 5610 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ 5611 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ 5612 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ 5613 5614 /* Bit 9 : Disable interrupt on ERROR event. */ 5615 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 5616 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 5617 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 5618 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 5619 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 5620 5621 /* Bit 7 : Disable interrupt on TXDSENT event. */ 5622 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 5623 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 5624 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ 5625 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ 5626 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ 5627 5628 /* Bit 2 : Disable interrupt on RXDREADY event. */ 5629 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 5630 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 5631 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ 5632 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ 5633 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ 5634 5635 /* Bit 1 : Disable interrupt on STOPPED event. */ 5636 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 5637 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 5638 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 5639 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 5640 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ 5641 5642 /* Register: TWI_ERRORSRC */ 5643 /* Description: Two-wire error source. Write error field to 1 to clear error. */ 5644 5645 /* Bit 2 : NACK received after sending a data byte. */ 5646 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 5647 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 5648 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ 5649 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ 5650 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ 5651 5652 /* Bit 1 : NACK received after sending the address. */ 5653 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 5654 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 5655 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ 5656 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ 5657 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ 5658 5659 /* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ 5660 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 5661 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 5662 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ 5663 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ 5664 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ 5665 5666 /* Register: TWI_ENABLE */ 5667 /* Description: Enable two-wire master. */ 5668 5669 /* Bits 2..0 : Enable or disable W2M */ 5670 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5671 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5672 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ 5673 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ 5674 5675 /* Register: TWI_RXD */ 5676 /* Description: RX data register. */ 5677 5678 /* Bits 7..0 : RX data from last transfer. */ 5679 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 5680 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 5681 5682 /* Register: TWI_TXD */ 5683 /* Description: TX data register. */ 5684 5685 /* Bits 7..0 : TX data for next transfer. */ 5686 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 5687 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 5688 5689 /* Register: TWI_FREQUENCY */ 5690 /* Description: Two-wire frequency. */ 5691 5692 /* Bits 31..0 : Two-wire master clock frequency. */ 5693 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 5694 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 5695 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ 5696 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ 5697 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */ 5698 5699 /* Register: TWI_ADDRESS */ 5700 /* Description: Address used in the two-wire transfer. */ 5701 5702 /* Bits 6..0 : Two-wire address. */ 5703 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 5704 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 5705 5706 /* Register: TWI_POWER */ 5707 /* Description: Peripheral power control. */ 5708 5709 /* Bit 0 : Peripheral power control. */ 5710 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5711 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5712 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5713 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5714 5715 5716 /* Peripheral: UART */ 5717 /* Description: Universal Asynchronous Receiver/Transmitter. */ 5718 5719 /* Register: UART_SHORTS */ 5720 /* Description: Shortcuts for UART. */ 5721 5722 /* Bit 4 : Shortcut between NCTS event and STOPRX task. */ 5723 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ 5724 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ 5725 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ 5726 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ 5727 5728 /* Bit 3 : Shortcut between CTS event and STARTRX task. */ 5729 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ 5730 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ 5731 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ 5732 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ 5733 5734 /* Register: UART_INTENSET */ 5735 /* Description: Interrupt enable set register. */ 5736 5737 /* Bit 17 : Enable interrupt on RXTO event. */ 5738 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 5739 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 5740 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ 5741 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ 5742 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ 5743 5744 /* Bit 9 : Enable interrupt on ERROR event. */ 5745 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 5746 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 5747 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 5748 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 5749 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 5750 5751 /* Bit 7 : Enable interrupt on TXRDY event. */ 5752 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 5753 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 5754 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 5755 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 5756 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ 5757 5758 /* Bit 2 : Enable interrupt on RXRDY event. */ 5759 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 5760 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 5761 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 5762 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 5763 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ 5764 5765 /* Bit 1 : Enable interrupt on NCTS event. */ 5766 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 5767 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 5768 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ 5769 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ 5770 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ 5771 5772 /* Bit 0 : Enable interrupt on CTS event. */ 5773 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 5774 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 5775 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ 5776 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ 5777 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ 5778 5779 /* Register: UART_INTENCLR */ 5780 /* Description: Interrupt enable clear register. */ 5781 5782 /* Bit 17 : Disable interrupt on RXTO event. */ 5783 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 5784 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 5785 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ 5786 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ 5787 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ 5788 5789 /* Bit 9 : Disable interrupt on ERROR event. */ 5790 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 5791 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 5792 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 5793 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 5794 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 5795 5796 /* Bit 7 : Disable interrupt on TXRDY event. */ 5797 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 5798 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 5799 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 5800 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 5801 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ 5802 5803 /* Bit 2 : Disable interrupt on RXRDY event. */ 5804 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 5805 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 5806 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 5807 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 5808 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ 5809 5810 /* Bit 1 : Disable interrupt on NCTS event. */ 5811 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 5812 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 5813 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ 5814 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ 5815 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ 5816 5817 /* Bit 0 : Disable interrupt on CTS event. */ 5818 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 5819 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 5820 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ 5821 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ 5822 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ 5823 5824 /* Register: UART_ERRORSRC */ 5825 /* Description: Error source. Write error field to 1 to clear error. */ 5826 5827 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ 5828 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 5829 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 5830 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ 5831 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ 5832 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ 5833 5834 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ 5835 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 5836 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 5837 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ 5838 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ 5839 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ 5840 5841 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ 5842 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 5843 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 5844 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ 5845 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ 5846 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ 5847 5848 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ 5849 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 5850 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 5851 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ 5852 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ 5853 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ 5854 5855 /* Register: UART_ENABLE */ 5856 /* Description: Enable UART and acquire IOs. */ 5857 5858 /* Bits 2..0 : Enable or disable UART and acquire IOs. */ 5859 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5860 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5861 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ 5862 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ 5863 5864 /* Register: UART_RXD */ 5865 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ 5866 5867 /* Bits 7..0 : RX data from previous transfer. Double buffered. */ 5868 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 5869 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 5870 5871 /* Register: UART_TXD */ 5872 /* Description: TXD register. */ 5873 5874 /* Bits 7..0 : TX data for transfer. */ 5875 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 5876 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 5877 5878 /* Register: UART_BAUDRATE */ 5879 /* Description: UART Baudrate. */ 5880 5881 /* Bits 31..0 : UART baudrate. */ 5882 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 5883 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 5884 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ 5885 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ 5886 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ 5887 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ 5888 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ 5889 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ 5890 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ 5891 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */ 5892 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ 5893 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */ 5894 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ 5895 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ 5896 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ 5897 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ 5898 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ 5899 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ 5900 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ 5901 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ 5902 5903 /* Register: UART_CONFIG */ 5904 /* Description: Configuration of parity and hardware flow control register. */ 5905 5906 /* Bits 3..1 : Include parity bit. */ 5907 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 5908 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 5909 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ 5910 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ 5911 5912 /* Bit 0 : Hardware flow control. */ 5913 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 5914 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 5915 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ 5916 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ 5917 5918 /* Register: UART_POWER */ 5919 /* Description: Peripheral power control. */ 5920 5921 /* Bit 0 : Peripheral power control. */ 5922 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5923 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5924 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5925 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5926 5927 5928 /* Peripheral: UICR */ 5929 /* Description: User Information Configuration. */ 5930 5931 /* Register: UICR_RBPCONF */ 5932 /* Description: Readback protection configuration. */ 5933 5934 /* Bits 15..8 : Readback protect all code in the device. */ 5935 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ 5936 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ 5937 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ 5938 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ 5939 5940 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ 5941 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ 5942 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ 5943 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ 5944 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ 5945 5946 /* Register: UICR_XTALFREQ */ 5947 /* Description: Reset value for CLOCK XTALFREQ register. */ 5948 5949 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ 5950 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ 5951 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ 5952 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ 5953 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ 5954 5955 /* Register: UICR_FWID */ 5956 /* Description: Firmware ID. */ 5957 5958 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */ 5959 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ 5960 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ 5961 5962 5963 /* Peripheral: WDT */ 5964 /* Description: Watchdog Timer. */ 5965 5966 /* Register: WDT_INTENSET */ 5967 /* Description: Interrupt enable set register. */ 5968 5969 /* Bit 0 : Enable interrupt on TIMEOUT event. */ 5970 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 5971 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 5972 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ 5973 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ 5974 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ 5975 5976 /* Register: WDT_INTENCLR */ 5977 /* Description: Interrupt enable clear register. */ 5978 5979 /* Bit 0 : Disable interrupt on TIMEOUT event. */ 5980 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 5981 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 5982 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ 5983 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ 5984 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ 5985 5986 /* Register: WDT_RUNSTATUS */ 5987 /* Description: Watchdog running status. */ 5988 5989 /* Bit 0 : Watchdog running status. */ 5990 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ 5991 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ 5992 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ 5993 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ 5994 5995 /* Register: WDT_REQSTATUS */ 5996 /* Description: Request status. */ 5997 5998 /* Bit 7 : Request status for RR[7]. */ 5999 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 6000 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 6001 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ 6002 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ 6003 6004 /* Bit 6 : Request status for RR[6]. */ 6005 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 6006 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 6007 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ 6008 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ 6009 6010 /* Bit 5 : Request status for RR[5]. */ 6011 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 6012 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 6013 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ 6014 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ 6015 6016 /* Bit 4 : Request status for RR[4]. */ 6017 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 6018 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 6019 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ 6020 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ 6021 6022 /* Bit 3 : Request status for RR[3]. */ 6023 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 6024 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 6025 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ 6026 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ 6027 6028 /* Bit 2 : Request status for RR[2]. */ 6029 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 6030 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 6031 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ 6032 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ 6033 6034 /* Bit 1 : Request status for RR[1]. */ 6035 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 6036 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 6037 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ 6038 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ 6039 6040 /* Bit 0 : Request status for RR[0]. */ 6041 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 6042 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 6043 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ 6044 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ 6045 6046 /* Register: WDT_RREN */ 6047 /* Description: Reload request enable. */ 6048 6049 /* Bit 7 : Enable or disable RR[7] register. */ 6050 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 6051 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 6052 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ 6053 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ 6054 6055 /* Bit 6 : Enable or disable RR[6] register. */ 6056 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 6057 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 6058 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ 6059 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ 6060 6061 /* Bit 5 : Enable or disable RR[5] register. */ 6062 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 6063 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 6064 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ 6065 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ 6066 6067 /* Bit 4 : Enable or disable RR[4] register. */ 6068 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 6069 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 6070 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ 6071 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ 6072 6073 /* Bit 3 : Enable or disable RR[3] register. */ 6074 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 6075 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 6076 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ 6077 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ 6078 6079 /* Bit 2 : Enable or disable RR[2] register. */ 6080 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 6081 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 6082 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ 6083 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ 6084 6085 /* Bit 1 : Enable or disable RR[1] register. */ 6086 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 6087 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 6088 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ 6089 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ 6090 6091 /* Bit 0 : Enable or disable RR[0] register. */ 6092 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 6093 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 6094 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ 6095 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ 6096 6097 /* Register: WDT_CONFIG */ 6098 /* Description: Configuration register. */ 6099 6100 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ 6101 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 6102 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 6103 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ 6104 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ 6105 6106 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ 6107 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 6108 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 6109 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ 6110 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ 6111 6112 /* Register: WDT_RR */ 6113 /* Description: Reload requests registers. */ 6114 6115 /* Bits 31..0 : Reload register. */ 6116 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 6117 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 6118 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ 6119 6120 /* Register: WDT_POWER */ 6121 /* Description: Peripheral power control. */ 6122 6123 /* Bit 0 : Peripheral power control. */ 6124 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6125 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6126 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6127 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6128 6129 6130 /*lint --flb "Leave library region" */ 6131 #endif 6132