1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf51.h 31 * @brief CMSIS HeaderFile 32 * @version 522 33 * @date 03. December 2018 34 * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35 * from File 'nrf51.svd', 36 * last modified on Monday, 03.12.2018 10:18:20 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf51 47 * @{ 48 */ 49 50 51 #ifndef NRF51_H 52 #define NRF51_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 75 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 76 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 77 /* =========================================== nrf51 Specific Interrupt Numbers ============================================ */ 78 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 79 RADIO_IRQn = 1, /*!< 1 RADIO */ 80 UART0_IRQn = 2, /*!< 2 UART0 */ 81 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 82 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 83 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 84 ADC_IRQn = 7, /*!< 7 ADC */ 85 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 86 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 87 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 88 RTC0_IRQn = 11, /*!< 11 RTC0 */ 89 TEMP_IRQn = 12, /*!< 12 TEMP */ 90 RNG_IRQn = 13, /*!< 13 RNG */ 91 ECB_IRQn = 14, /*!< 14 ECB */ 92 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 93 WDT_IRQn = 16, /*!< 16 WDT */ 94 RTC1_IRQn = 17, /*!< 17 RTC1 */ 95 QDEC_IRQn = 18, /*!< 18 QDEC */ 96 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 97 SWI0_IRQn = 20, /*!< 20 SWI0 */ 98 SWI1_IRQn = 21, /*!< 21 SWI1 */ 99 SWI2_IRQn = 22, /*!< 22 SWI2 */ 100 SWI3_IRQn = 23, /*!< 23 SWI3 */ 101 SWI4_IRQn = 24, /*!< 24 SWI4 */ 102 SWI5_IRQn = 25 /*!< 25 SWI5 */ 103 } IRQn_Type; 104 105 106 107 /* =========================================================================================================================== */ 108 /* ================ Processor and Core Peripheral Section ================ */ 109 /* =========================================================================================================================== */ 110 111 /* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ 112 #define __CM0_REV 0x0301U /*!< CM0 Core Revision */ 113 #define __DSP_PRESENT 0 /*!< DSP present or not */ 114 #define __MPU_PRESENT 0 /*!< MPU present or not */ 115 #define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 116 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 117 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 118 119 120 /** @} */ /* End of group Configuration_of_CMSIS */ 121 122 #include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ 123 #include "system_nrf51.h" /*!< nrf51 System */ 124 125 #ifndef __IM /*!< Fallback for older CMSIS versions */ 126 #define __IM __I 127 #endif 128 #ifndef __OM /*!< Fallback for older CMSIS versions */ 129 #define __OM __O 130 #endif 131 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 132 #define __IOM __IO 133 #endif 134 135 136 /* ======================================== Start of section using anonymous unions ======================================== */ 137 #if defined (__CC_ARM) 138 #pragma push 139 #pragma anon_unions 140 #elif defined (__ICCARM__) 141 #pragma language=extended 142 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 143 #pragma clang diagnostic push 144 #pragma clang diagnostic ignored "-Wc11-extensions" 145 #pragma clang diagnostic ignored "-Wreserved-id-macro" 146 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 147 #pragma clang diagnostic ignored "-Wnested-anon-types" 148 #elif defined (__GNUC__) 149 /* anonymous unions are enabled by default */ 150 #elif defined (__TMS470__) 151 /* anonymous unions are enabled by default */ 152 #elif defined (__TASKING__) 153 #pragma warning 586 154 #elif defined (__CSMC__) 155 /* anonymous unions are enabled by default */ 156 #else 157 #warning Not supported compiler type 158 #endif 159 160 161 /* =========================================================================================================================== */ 162 /* ================ Device Specific Cluster Section ================ */ 163 /* =========================================================================================================================== */ 164 165 166 /** @addtogroup Device_Peripheral_clusters 167 * @{ 168 */ 169 170 171 /** 172 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks.) 173 */ 174 typedef struct { 175 __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. */ 176 __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. */ 177 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 178 179 180 /** 181 * @brief PPI_CH [CH] (PPI Channel.) 182 */ 183 typedef struct { 184 __IOM uint32_t EEP; /*!< (@ 0x00000000) Channel event end-point. */ 185 __IOM uint32_t TEP; /*!< (@ 0x00000004) Channel task end-point. */ 186 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 187 188 189 /** @} */ /* End of group Device_Peripheral_clusters */ 190 191 192 /* =========================================================================================================================== */ 193 /* ================ Device Specific Peripheral Section ================ */ 194 /* =========================================================================================================================== */ 195 196 197 /** @addtogroup Device_Peripheral_peripherals 198 * @{ 199 */ 200 201 202 203 /* =========================================================================================================================== */ 204 /* ================ POWER ================ */ 205 /* =========================================================================================================================== */ 206 207 208 /** 209 * @brief Power Control. (POWER) 210 */ 211 212 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 213 __IM uint32_t RESERVED[30]; 214 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 215 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency). */ 216 __IM uint32_t RESERVED1[34]; 217 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning. */ 218 __IM uint32_t RESERVED2[126]; 219 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 220 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 221 __IM uint32_t RESERVED3[61]; 222 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason. */ 223 __IM uint32_t RESERVED4[9]; 224 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Ram status register. */ 225 __IM uint32_t RESERVED5[53]; 226 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System off register. */ 227 __IM uint32_t RESERVED6[3]; 228 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure configuration. */ 229 __IM uint32_t RESERVED7[2]; 230 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register. This register 231 is a retained register. */ 232 __IM uint32_t RESERVED8; 233 __IOM uint32_t RAMON; /*!< (@ 0x00000524) Ram on/off. */ 234 __IM uint32_t RESERVED9[7]; 235 __IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configuration register. 236 This register is a retained register. */ 237 __IM uint32_t RESERVED10[3]; 238 __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Ram on/off. */ 239 __IM uint32_t RESERVED11[8]; 240 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DCDC converter enable configuration register. */ 241 __IM uint32_t RESERVED12[291]; 242 __IOM uint32_t DCDCFORCE; /*!< (@ 0x00000A08) DCDC power-up force register. */ 243 } NRF_POWER_Type; /*!< Size = 2572 (0xa0c) */ 244 245 246 247 /* =========================================================================================================================== */ 248 /* ================ CLOCK ================ */ 249 /* =========================================================================================================================== */ 250 251 252 /** 253 * @brief Clock control. (CLOCK) 254 */ 255 256 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 257 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK clock source. */ 258 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK clock source. */ 259 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK clock source. */ 260 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK clock source. */ 261 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFCLK RC oscillator. */ 262 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer. */ 263 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer. */ 264 __IM uint32_t RESERVED[57]; 265 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started. */ 266 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK oscillator started. */ 267 __IM uint32_t RESERVED1; 268 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator completed. */ 269 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout. */ 270 __IM uint32_t RESERVED2[124]; 271 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 272 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 273 __IM uint32_t RESERVED3[63]; 274 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Task HFCLKSTART trigger status. */ 275 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) High frequency clock status. */ 276 __IM uint32_t RESERVED4; 277 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Task LFCLKSTART triggered status. */ 278 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Low frequency clock status. */ 279 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Clock source for the LFCLK clock, set when task 280 LKCLKSTART is triggered. */ 281 __IM uint32_t RESERVED5[62]; 282 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK clock. */ 283 __IM uint32_t RESERVED6[7]; 284 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval. */ 285 __IM uint32_t RESERVED7[5]; 286 __IOM uint32_t XTALFREQ; /*!< (@ 0x00000550) Crystal frequency. */ 287 } NRF_CLOCK_Type; /*!< Size = 1364 (0x554) */ 288 289 290 291 /* =========================================================================================================================== */ 292 /* ================ MPU ================ */ 293 /* =========================================================================================================================== */ 294 295 296 /** 297 * @brief Memory Protection Unit. (MPU) 298 */ 299 300 typedef struct { /*!< (@ 0x40000000) MPU Structure */ 301 __IM uint32_t RESERVED[330]; 302 __IOM uint32_t PERR0; /*!< (@ 0x00000528) Configuration of peripherals in mpu regions. */ 303 __IOM uint32_t RLENR0; /*!< (@ 0x0000052C) Length of RAM region 0. */ 304 __IM uint32_t RESERVED1[52]; 305 __IOM uint32_t PROTENSET0; /*!< (@ 0x00000600) Erase and write protection bit enable set register. */ 306 __IOM uint32_t PROTENSET1; /*!< (@ 0x00000604) Erase and write protection bit enable set register. */ 307 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protection mechanism 308 in debug mode. */ 309 __IOM uint32_t PROTBLOCKSIZE; /*!< (@ 0x0000060C) Erase and write protection block size. */ 310 } NRF_MPU_Type; /*!< Size = 1552 (0x610) */ 311 312 313 314 /* =========================================================================================================================== */ 315 /* ================ RADIO ================ */ 316 /* =========================================================================================================================== */ 317 318 319 /** 320 * @brief The radio. (RADIO) 321 */ 322 323 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 324 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable radio in TX mode. */ 325 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable radio in RX mode. */ 326 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start radio. */ 327 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop radio. */ 328 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable radio. */ 329 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sample of the receive 330 signal strength. */ 331 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement. */ 332 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter. */ 333 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter. */ 334 __IM uint32_t RESERVED[55]; 335 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) Ready event. */ 336 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address event. */ 337 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Payload event. */ 338 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) End event. */ 339 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) Disable event. */ 340 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 341 packet. */ 342 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 343 received packet. */ 344 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of the receive signal strength complete. 345 A new RSSI sample is ready for readout at 346 the RSSISAMPLE register. */ 347 __IM uint32_t RESERVED1[2]; 348 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value specified 349 in BCC register. */ 350 __IM uint32_t RESERVED2[53]; 351 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the radio. */ 352 __IM uint32_t RESERVED3[64]; 353 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 354 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 355 __IM uint32_t RESERVED4[61]; 356 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status of received packet. */ 357 __IM uint32_t RESERVED5; 358 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address. */ 359 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) Received CRC. */ 360 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index. */ 361 __IM uint32_t RESERVED6[60]; 362 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer. Decision point: START task. */ 363 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency. */ 364 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power. */ 365 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation. */ 366 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration 0. */ 367 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration 1. */ 368 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Radio base address 0. Decision point: START task. */ 369 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Radio base address 1. Decision point: START task. */ 370 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0 to 3. */ 371 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4 to 7. */ 372 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select. */ 373 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select. */ 374 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration. */ 375 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial. */ 376 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value. */ 377 __IOM uint32_t TEST; /*!< (@ 0x00000540) Test features enable register. */ 378 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in microseconds. */ 379 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample. */ 380 __IM uint32_t RESERVED7; 381 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state. */ 382 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value. */ 383 __IM uint32_t RESERVED8[2]; 384 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare. */ 385 __IM uint32_t RESERVED9[39]; 386 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Device address base segment. */ 387 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Device address prefix. */ 388 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration. */ 389 __IM uint32_t RESERVED10[56]; 390 __IOM uint32_t OVERRIDE0; /*!< (@ 0x00000724) Trim value override register 0. */ 391 __IOM uint32_t OVERRIDE1; /*!< (@ 0x00000728) Trim value override register 1. */ 392 __IOM uint32_t OVERRIDE2; /*!< (@ 0x0000072C) Trim value override register 2. */ 393 __IOM uint32_t OVERRIDE3; /*!< (@ 0x00000730) Trim value override register 3. */ 394 __IOM uint32_t OVERRIDE4; /*!< (@ 0x00000734) Trim value override register 4. */ 395 __IM uint32_t RESERVED11[561]; 396 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 397 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 398 399 400 401 /* =========================================================================================================================== */ 402 /* ================ UART0 ================ */ 403 /* =========================================================================================================================== */ 404 405 406 /** 407 * @brief Universal Asynchronous Receiver/Transmitter. (UART0) 408 */ 409 410 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 411 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver. */ 412 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver. */ 413 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter. */ 414 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter. */ 415 __IM uint32_t RESERVED[3]; 416 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART. */ 417 __IM uint32_t RESERVED1[56]; 418 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS activated. */ 419 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS deactivated. */ 420 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD. */ 421 __IM uint32_t RESERVED2[4]; 422 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD. */ 423 __IM uint32_t RESERVED3; 424 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected. */ 425 __IM uint32_t RESERVED4[7]; 426 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout. */ 427 __IM uint32_t RESERVED5[46]; 428 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for UART. */ 429 __IM uint32_t RESERVED6[64]; 430 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 431 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 432 __IM uint32_t RESERVED7[93]; 433 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field to 1 to clear 434 error. */ 435 __IM uint32_t RESERVED8[31]; 436 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART and acquire IOs. */ 437 __IM uint32_t RESERVED9; 438 __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS. */ 439 __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD. */ 440 __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS. */ 441 __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD. */ 442 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. On read action the buffer pointer 443 is displaced. Once read the character is 444 consumed. If read when no character available, 445 the UART will stop working. */ 446 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register. */ 447 __IM uint32_t RESERVED10; 448 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) UART Baudrate. */ 449 __IM uint32_t RESERVED11[17]; 450 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control 451 register. */ 452 __IM uint32_t RESERVED12[675]; 453 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 454 } NRF_UART_Type; /*!< Size = 4096 (0x1000) */ 455 456 457 458 /* =========================================================================================================================== */ 459 /* ================ SPI0 ================ */ 460 /* =========================================================================================================================== */ 461 462 463 /** 464 * @brief SPI master 0. (SPI0) 465 */ 466 467 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 468 __IM uint32_t RESERVED[66]; 469 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received. */ 470 __IM uint32_t RESERVED1[126]; 471 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 472 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 473 __IM uint32_t RESERVED2[125]; 474 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI. */ 475 __IM uint32_t RESERVED3; 476 __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ 477 __IOM uint32_t PSELMOSI; /*!< (@ 0x0000050C) Pin select for MOSI. */ 478 __IOM uint32_t PSELMISO; /*!< (@ 0x00000510) Pin select for MISO. */ 479 __IM uint32_t RESERVED4; 480 __IM uint32_t RXD; /*!< (@ 0x00000518) RX data. */ 481 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data. */ 482 __IM uint32_t RESERVED5; 483 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 484 __IM uint32_t RESERVED6[11]; 485 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ 486 __IM uint32_t RESERVED7[681]; 487 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 488 } NRF_SPI_Type; /*!< Size = 4096 (0x1000) */ 489 490 491 492 /* =========================================================================================================================== */ 493 /* ================ TWI0 ================ */ 494 /* =========================================================================================================================== */ 495 496 497 /** 498 * @brief Two-wire interface master 0. (TWI0) 499 */ 500 501 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 502 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start 2-Wire master receive sequence. */ 503 __IM uint32_t RESERVED; 504 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start 2-Wire master transmit sequence. */ 505 __IM uint32_t RESERVED1[2]; 506 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop 2-Wire transaction. */ 507 __IM uint32_t RESERVED2; 508 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend 2-Wire transaction. */ 509 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume 2-Wire transaction. */ 510 __IM uint32_t RESERVED3[56]; 511 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Two-wire stopped. */ 512 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) Two-wire ready to deliver new RXD byte received. */ 513 __IM uint32_t RESERVED4[4]; 514 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) Two-wire finished sending last TXD byte. */ 515 __IM uint32_t RESERVED5; 516 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Two-wire error detected. */ 517 __IM uint32_t RESERVED6[4]; 518 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) Two-wire byte boundary. */ 519 __IM uint32_t RESERVED7[3]; 520 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Two-wire suspended. */ 521 __IM uint32_t RESERVED8[45]; 522 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for TWI. */ 523 __IM uint32_t RESERVED9[64]; 524 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 525 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 526 __IM uint32_t RESERVED10[110]; 527 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write error field to 1 528 to clear error. */ 529 __IM uint32_t RESERVED11[14]; 530 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable two-wire master. */ 531 __IM uint32_t RESERVED12; 532 __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL. */ 533 __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA. */ 534 __IM uint32_t RESERVED13[2]; 535 __IM uint32_t RXD; /*!< (@ 0x00000518) RX data register. */ 536 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data register. */ 537 __IM uint32_t RESERVED14; 538 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) Two-wire frequency. */ 539 __IM uint32_t RESERVED15[24]; 540 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the two-wire transfer. */ 541 __IM uint32_t RESERVED16[668]; 542 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 543 } NRF_TWI_Type; /*!< Size = 4096 (0x1000) */ 544 545 546 547 /* =========================================================================================================================== */ 548 /* ================ SPIS1 ================ */ 549 /* =========================================================================================================================== */ 550 551 552 /** 553 * @brief SPI slave 1. (SPIS1) 554 */ 555 556 typedef struct { /*!< (@ 0x40004000) SPIS1 Structure */ 557 __IM uint32_t RESERVED[9]; 558 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore. */ 559 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore. */ 560 __IM uint32_t RESERVED1[54]; 561 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed. */ 562 __IM uint32_t RESERVED2[2]; 563 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 564 __IM uint32_t RESERVED3[5]; 565 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired. */ 566 __IM uint32_t RESERVED4[53]; 567 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for SPIS. */ 568 __IM uint32_t RESERVED5[64]; 569 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 570 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 571 __IM uint32_t RESERVED6[61]; 572 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status. */ 573 __IM uint32_t RESERVED7[15]; 574 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction. */ 575 __IM uint32_t RESERVED8[47]; 576 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIS. */ 577 __IM uint32_t RESERVED9; 578 __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ 579 __IOM uint32_t PSELMISO; /*!< (@ 0x0000050C) Pin select for MISO. */ 580 __IOM uint32_t PSELMOSI; /*!< (@ 0x00000510) Pin select for MOSI. */ 581 __IOM uint32_t PSELCSN; /*!< (@ 0x00000514) Pin select for CSN. */ 582 __IM uint32_t RESERVED10[7]; 583 __IOM uint32_t RXDPTR; /*!< (@ 0x00000534) RX data pointer. */ 584 __IOM uint32_t MAXRX; /*!< (@ 0x00000538) Maximum number of bytes in the receive buffer. */ 585 __IM uint32_t AMOUNTRX; /*!< (@ 0x0000053C) Number of bytes received in last granted transaction. */ 586 __IM uint32_t RESERVED11; 587 __IOM uint32_t TXDPTR; /*!< (@ 0x00000544) TX data pointer. */ 588 __IOM uint32_t MAXTX; /*!< (@ 0x00000548) Maximum number of bytes in the transmit buffer. */ 589 __IM uint32_t AMOUNTTX; /*!< (@ 0x0000054C) Number of bytes transmitted in last granted transaction. */ 590 __IM uint32_t RESERVED12; 591 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ 592 __IM uint32_t RESERVED13; 593 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. */ 594 __IM uint32_t RESERVED14[24]; 595 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. */ 596 __IM uint32_t RESERVED15[654]; 597 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 598 } NRF_SPIS_Type; /*!< Size = 4096 (0x1000) */ 599 600 601 602 /* =========================================================================================================================== */ 603 /* ================ GPIOTE ================ */ 604 /* =========================================================================================================================== */ 605 606 607 /** 608 * @brief GPIO tasks and events. (GPIOTE) 609 */ 610 611 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 612 __OM uint32_t TASKS_OUT[4]; /*!< (@ 0x00000000) Tasks asssociated with GPIOTE channels. */ 613 __IM uint32_t RESERVED[60]; 614 __IOM uint32_t EVENTS_IN[4]; /*!< (@ 0x00000100) Tasks asssociated with GPIOTE channels. */ 615 __IM uint32_t RESERVED1[27]; 616 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple pins. */ 617 __IM uint32_t RESERVED2[97]; 618 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 619 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 620 __IM uint32_t RESERVED3[129]; 621 __IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers. */ 622 __IM uint32_t RESERVED4[695]; 623 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 624 } NRF_GPIOTE_Type; /*!< Size = 4096 (0x1000) */ 625 626 627 628 /* =========================================================================================================================== */ 629 /* ================ ADC ================ */ 630 /* =========================================================================================================================== */ 631 632 633 /** 634 * @brief Analog to digital converter. (ADC) 635 */ 636 637 typedef struct { /*!< (@ 0x40007000) ADC Structure */ 638 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start an ADC conversion. */ 639 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop ADC. */ 640 __IM uint32_t RESERVED[62]; 641 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ADC conversion complete. */ 642 __IM uint32_t RESERVED1[128]; 643 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 644 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 645 __IM uint32_t RESERVED2[61]; 646 __IM uint32_t BUSY; /*!< (@ 0x00000400) ADC busy register. */ 647 __IM uint32_t RESERVED3[63]; 648 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) ADC enable. */ 649 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. */ 650 __IM uint32_t RESULT; /*!< (@ 0x00000508) Result of ADC conversion. */ 651 __IM uint32_t RESERVED4[700]; 652 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 653 } NRF_ADC_Type; /*!< Size = 4096 (0x1000) */ 654 655 656 657 /* =========================================================================================================================== */ 658 /* ================ TIMER0 ================ */ 659 /* =========================================================================================================================== */ 660 661 662 /** 663 * @brief Timer 0. (TIMER0) 664 */ 665 666 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 667 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer. */ 668 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer. */ 669 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (In counter mode). */ 670 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear timer. */ 671 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shutdown timer. */ 672 __IM uint32_t RESERVED[11]; 673 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Capture Timer value to CC[n] registers. */ 674 __IM uint32_t RESERVED1[60]; 675 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ 676 __IM uint32_t RESERVED2[44]; 677 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for Timer. */ 678 __IM uint32_t RESERVED3[64]; 679 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 680 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 681 __IM uint32_t RESERVED4[126]; 682 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer Mode selection. */ 683 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Sets timer behaviour. */ 684 __IM uint32_t RESERVED5; 685 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) 4-bit prescaler to source clock frequency (max 686 value 9). Source clock frequency is divided 687 by 2^SCALE. */ 688 __IM uint32_t RESERVED6[11]; 689 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ 690 __IM uint32_t RESERVED7[683]; 691 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 692 } NRF_TIMER_Type; /*!< Size = 4096 (0x1000) */ 693 694 695 696 /* =========================================================================================================================== */ 697 /* ================ RTC0 ================ */ 698 /* =========================================================================================================================== */ 699 700 701 /** 702 * @brief Real time counter 0. (RTC0) 703 */ 704 705 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 706 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC Counter. */ 707 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC Counter. */ 708 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC Counter. */ 709 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFFFF0. */ 710 __IM uint32_t RESERVED[60]; 711 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment. */ 712 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow. */ 713 __IM uint32_t RESERVED1[14]; 714 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ 715 __IM uint32_t RESERVED2[109]; 716 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 717 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 718 __IM uint32_t RESERVED3[13]; 719 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each 720 RTC event. */ 721 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. The reading of 722 this register gives the value of EVTEN. */ 723 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. The reading of 724 this register gives the value of EVTEN. */ 725 __IM uint32_t RESERVED4[110]; 726 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value. */ 727 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 728 Must be written when RTC is STOPed. */ 729 __IM uint32_t RESERVED5[13]; 730 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ 731 __IM uint32_t RESERVED6[683]; 732 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 733 } NRF_RTC_Type; /*!< Size = 4096 (0x1000) */ 734 735 736 737 /* =========================================================================================================================== */ 738 /* ================ TEMP ================ */ 739 /* =========================================================================================================================== */ 740 741 742 /** 743 * @brief Temperature Sensor. (TEMP) 744 */ 745 746 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 747 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement. */ 748 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement. */ 749 __IM uint32_t RESERVED[62]; 750 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready 751 event. */ 752 __IM uint32_t RESERVED1[128]; 753 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 754 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 755 __IM uint32_t RESERVED2[127]; 756 __IM int32_t TEMP; /*!< (@ 0x00000508) Die temperature in degC, 2's complement format, 757 0.25 degC pecision. */ 758 __IM uint32_t RESERVED3[700]; 759 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 760 } NRF_TEMP_Type; /*!< Size = 4096 (0x1000) */ 761 762 763 764 /* =========================================================================================================================== */ 765 /* ================ RNG ================ */ 766 /* =========================================================================================================================== */ 767 768 769 /** 770 * @brief Random Number Generator. (RNG) 771 */ 772 773 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 774 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the random number generator. */ 775 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the random number generator. */ 776 __IM uint32_t RESERVED[62]; 777 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) New random number generated and written to VALUE 778 register. */ 779 __IM uint32_t RESERVED1[63]; 780 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the RNG. */ 781 __IM uint32_t RESERVED2[64]; 782 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register */ 783 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register */ 784 __IM uint32_t RESERVED3[126]; 785 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ 786 __IM uint32_t VALUE; /*!< (@ 0x00000508) RNG random number. */ 787 __IM uint32_t RESERVED4[700]; 788 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 789 } NRF_RNG_Type; /*!< Size = 4096 (0x1000) */ 790 791 792 793 /* =========================================================================================================================== */ 794 /* ================ ECB ================ */ 795 /* =========================================================================================================================== */ 796 797 798 /** 799 * @brief AES ECB Mode Encryption. (ECB) 800 */ 801 802 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 803 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a crypto operation 804 is running, this will not initiate a new 805 encryption and the ERRORECB event will be 806 triggered. */ 807 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If a crypto operation 808 is running, this will will trigger the ERRORECB 809 event. */ 810 __IM uint32_t RESERVED[62]; 811 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete. */ 812 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted due to a STOPECB task 813 or due to an error. */ 814 __IM uint32_t RESERVED1[127]; 815 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 816 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 817 __IM uint32_t RESERVED2[126]; 818 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointer. */ 819 __IM uint32_t RESERVED3[701]; 820 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 821 } NRF_ECB_Type; /*!< Size = 4096 (0x1000) */ 822 823 824 825 /* =========================================================================================================================== */ 826 /* ================ AAR ================ */ 827 /* =========================================================================================================================== */ 828 829 830 /** 831 * @brief Accelerated Address Resolver. (AAR) 832 */ 833 834 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 835 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 836 in the IRK data structure. */ 837 __IM uint32_t RESERVED; 838 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses. */ 839 __IM uint32_t RESERVED1[61]; 840 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure completed. */ 841 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved. */ 842 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved. */ 843 __IM uint32_t RESERVED2[126]; 844 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 845 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 846 __IM uint32_t RESERVED3[61]; 847 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status. */ 848 __IM uint32_t RESERVED4[63]; 849 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR. */ 850 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of Identity root Keys in the IRK data 851 structure. */ 852 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to the IRK data structure. */ 853 __IM uint32_t RESERVED5; 854 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address (6 bytes). */ 855 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary 856 storage during resolution. A minimum of 857 3 bytes must be reserved. */ 858 __IM uint32_t RESERVED6[697]; 859 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 860 } NRF_AAR_Type; /*!< Size = 4096 (0x1000) */ 861 862 863 864 /* =========================================================================================================================== */ 865 /* ================ CCM ================ */ 866 /* =========================================================================================================================== */ 867 868 869 /** 870 * @brief AES CCM Mode Encryption. (CCM) 871 */ 872 873 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 874 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 875 will stop by itself when completed. */ 876 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This operation will stop 877 by itself when completed. */ 878 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encrypt/decrypt. */ 879 __IM uint32_t RESERVED[61]; 880 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation completed. */ 881 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt completed. */ 882 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Error happened. */ 883 __IM uint32_t RESERVED1[61]; 884 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the CCM. */ 885 __IM uint32_t RESERVED2[64]; 886 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 887 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 888 __IM uint32_t RESERVED3[61]; 889 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) CCM RX MIC check result. */ 890 __IM uint32_t RESERVED4[63]; 891 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) CCM enable. */ 892 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode. */ 893 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to a data structure holding AES key and 894 NONCE vector. */ 895 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Pointer to the input packet. */ 896 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Pointer to the output packet. */ 897 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary 898 storage during resolution. A minimum of 899 43 bytes must be reserved. */ 900 __IM uint32_t RESERVED5[697]; 901 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 902 } NRF_CCM_Type; /*!< Size = 4096 (0x1000) */ 903 904 905 906 /* =========================================================================================================================== */ 907 /* ================ WDT ================ */ 908 /* =========================================================================================================================== */ 909 910 911 /** 912 * @brief Watchdog Timer. (WDT) 913 */ 914 915 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 916 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog. */ 917 __IM uint32_t RESERVED[63]; 918 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout. */ 919 __IM uint32_t RESERVED1[128]; 920 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 921 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 922 __IM uint32_t RESERVED2[61]; 923 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Watchdog running status. */ 924 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status. */ 925 __IM uint32_t RESERVED3[63]; 926 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value in number of 32kiHz clock 927 cycles. */ 928 __IOM uint32_t RREN; /*!< (@ 0x00000508) Reload request enable. */ 929 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. */ 930 __IM uint32_t RESERVED4[60]; 931 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload requests registers. */ 932 __IM uint32_t RESERVED5[631]; 933 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 934 } NRF_WDT_Type; /*!< Size = 4096 (0x1000) */ 935 936 937 938 /* =========================================================================================================================== */ 939 /* ================ QDEC ================ */ 940 /* =========================================================================================================================== */ 941 942 943 /** 944 * @brief Rotary decoder. (QDEC) 945 */ 946 947 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 948 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the quadrature decoder. */ 949 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the quadrature decoder. */ 950 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Transfers the content from ACC registers to ACCREAD 951 registers, and clears the ACC registers. */ 952 __IM uint32_t RESERVED[61]; 953 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) A new sample is written to the sample register. */ 954 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) REPORTPER number of samples accumulated in ACC 955 register, and ACC register different than 956 zero. */ 957 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow. */ 958 __IM uint32_t RESERVED1[61]; 959 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the QDEC. */ 960 __IM uint32_t RESERVED2[64]; 961 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 962 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 963 __IM uint32_t RESERVED3[125]; 964 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the QDEC. */ 965 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity. */ 966 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period. */ 967 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value. */ 968 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to generate an EVENT_REPORTRDY. */ 969 __IM int32_t ACC; /*!< (@ 0x00000514) Accumulated valid transitions register. */ 970 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of ACC register. Value generated by 971 the TASKS_READCLEACC task. */ 972 __IOM uint32_t PSELLED; /*!< (@ 0x0000051C) Pin select for LED output. */ 973 __IOM uint32_t PSELA; /*!< (@ 0x00000520) Pin select for phase A input. */ 974 __IOM uint32_t PSELB; /*!< (@ 0x00000524) Pin select for phase B input. */ 975 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable debouncer input filters. */ 976 __IM uint32_t RESERVED4[5]; 977 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time LED is switched ON before the sample. */ 978 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Accumulated double (error) transitions register. */ 979 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of ACCDBL register. Value generated 980 by the TASKS_READCLEACC task. */ 981 __IM uint32_t RESERVED5[684]; 982 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 983 } NRF_QDEC_Type; /*!< Size = 4096 (0x1000) */ 984 985 986 987 /* =========================================================================================================================== */ 988 /* ================ LPCOMP ================ */ 989 /* =========================================================================================================================== */ 990 991 992 /** 993 * @brief Low power comparator. (LPCOMP) 994 */ 995 996 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 997 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the comparator. */ 998 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the comparator. */ 999 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. */ 1000 __IM uint32_t RESERVED[61]; 1001 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid. */ 1002 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Input voltage crossed the threshold going down. */ 1003 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Input voltage crossed the threshold going up. */ 1004 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Input voltage crossed the threshold in any direction. */ 1005 __IM uint32_t RESERVED1[60]; 1006 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the LPCOMP. */ 1007 __IM uint32_t RESERVED2[64]; 1008 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 1009 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 1010 __IM uint32_t RESERVED3[61]; 1011 __IM uint32_t RESULT; /*!< (@ 0x00000400) Result of last compare. */ 1012 __IM uint32_t RESERVED4[63]; 1013 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the LPCOMP. */ 1014 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select. */ 1015 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select. */ 1016 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select. */ 1017 __IM uint32_t RESERVED5[4]; 1018 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration. */ 1019 __IM uint32_t RESERVED6[694]; 1020 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 1021 } NRF_LPCOMP_Type; /*!< Size = 4096 (0x1000) */ 1022 1023 1024 1025 /* =========================================================================================================================== */ 1026 /* ================ SWI ================ */ 1027 /* =========================================================================================================================== */ 1028 1029 1030 /** 1031 * @brief SW Interrupts. (SWI) 1032 */ 1033 1034 typedef struct { /*!< (@ 0x40014000) SWI Structure */ 1035 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1036 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1037 1038 1039 1040 /* =========================================================================================================================== */ 1041 /* ================ NVMC ================ */ 1042 /* =========================================================================================================================== */ 1043 1044 1045 /** 1046 * @brief Non Volatile Memory Controller. (NVMC) 1047 */ 1048 1049 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1050 __IM uint32_t RESERVED[256]; 1051 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag. */ 1052 __IM uint32_t RESERVED1[64]; 1053 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ 1054 1055 union { 1056 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile 1057 memory page. */ 1058 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile 1059 memory page. */ 1060 }; 1061 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory. */ 1062 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Register for erasing a protected non-volatile 1063 memory page. */ 1064 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for start erasing User Information Congfiguration 1065 Registers. */ 1066 } NRF_NVMC_Type; /*!< Size = 1304 (0x518) */ 1067 1068 1069 1070 /* =========================================================================================================================== */ 1071 /* ================ PPI ================ */ 1072 /* =========================================================================================================================== */ 1073 1074 1075 /** 1076 * @brief PPI controller. (PPI) 1077 */ 1078 1079 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1080 __IOM PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks. */ 1081 __IM uint32_t RESERVED[312]; 1082 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable. */ 1083 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set. */ 1084 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear. */ 1085 __IM uint32_t RESERVED1; 1086 __IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. */ 1087 __IM uint32_t RESERVED2[156]; 1088 __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group configuration. */ 1089 } NRF_PPI_Type; /*!< Size = 2064 (0x810) */ 1090 1091 1092 1093 /* =========================================================================================================================== */ 1094 /* ================ FICR ================ */ 1095 /* =========================================================================================================================== */ 1096 1097 1098 /** 1099 * @brief Factory Information Configuration. (FICR) 1100 */ 1101 1102 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 1103 __IM uint32_t RESERVED[4]; 1104 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size in bytes. */ 1105 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size in pages. */ 1106 __IM uint32_t RESERVED1[4]; 1107 __IM uint32_t CLENR0; /*!< (@ 0x00000028) Length of code region 0 in bytes. */ 1108 __IM uint32_t PPFC; /*!< (@ 0x0000002C) Pre-programmed factory code present. */ 1109 __IM uint32_t RESERVED2; 1110 __IM uint32_t NUMRAMBLOCK; /*!< (@ 0x00000034) Number of individualy controllable RAM blocks. */ 1111 1112 union { 1113 __IM uint32_t SIZERAMBLOCKS; /*!< (@ 0x00000038) Size of RAM blocks in bytes. */ 1114 __IM uint32_t SIZERAMBLOCK[4]; /*!< (@ 0x00000038) Deprecated array of size of RAM block in bytes. 1115 This name is kept for backward compatinility 1116 purposes. Use SIZERAMBLOCKS instead. */ 1117 }; 1118 __IM uint32_t RESERVED3[5]; 1119 __IM uint32_t CONFIGID; /*!< (@ 0x0000005C) Configuration identifier. */ 1120 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Device identifier. */ 1121 __IM uint32_t RESERVED4[6]; 1122 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Encryption root. */ 1123 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Identity root. */ 1124 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type. */ 1125 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Device address. */ 1126 __IM uint32_t OVERRIDEEN; /*!< (@ 0x000000AC) Radio calibration override enable. */ 1127 __IM uint32_t NRF_1MBIT[5]; /*!< (@ 0x000000B0) Override values for the OVERRIDEn registers in 1128 RADIO for NRF_1Mbit mode. */ 1129 __IM uint32_t RESERVED5[10]; 1130 __IM uint32_t BLE_1MBIT[5]; /*!< (@ 0x000000EC) Override values for the OVERRIDEn registers in 1131 RADIO for BLE_1Mbit mode. */ 1132 } NRF_FICR_Type; /*!< Size = 256 (0x100) */ 1133 1134 1135 1136 /* =========================================================================================================================== */ 1137 /* ================ UICR ================ */ 1138 /* =========================================================================================================================== */ 1139 1140 1141 /** 1142 * @brief User Information Configuration. (UICR) 1143 */ 1144 1145 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 1146 __IOM uint32_t CLENR0; /*!< (@ 0x00000000) Length of code region 0. */ 1147 __IOM uint32_t RBPCONF; /*!< (@ 0x00000004) Readback protection configuration. */ 1148 __IOM uint32_t XTALFREQ; /*!< (@ 0x00000008) Reset value for CLOCK XTALFREQ register. */ 1149 __IM uint32_t RESERVED; 1150 __IM uint32_t FWID; /*!< (@ 0x00000010) Firmware ID. */ 1151 1152 union { 1153 __IOM uint32_t BOOTLOADERADDR; /*!< (@ 0x00000014) Bootloader start address. */ 1154 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Reserved for Nordic firmware design. */ 1155 }; 1156 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Reserved for Nordic hardware design. */ 1157 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Reserved for customer. */ 1158 } NRF_UICR_Type; /*!< Size = 256 (0x100) */ 1159 1160 1161 1162 /* =========================================================================================================================== */ 1163 /* ================ GPIO ================ */ 1164 /* =========================================================================================================================== */ 1165 1166 1167 /** 1168 * @brief General purpose input and output. (GPIO) 1169 */ 1170 1171 typedef struct { /*!< (@ 0x50000000) GPIO Structure */ 1172 __IM uint32_t RESERVED[321]; 1173 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port. */ 1174 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port. */ 1175 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port. */ 1176 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port. */ 1177 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins. */ 1178 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register. */ 1179 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register. */ 1180 __IM uint32_t RESERVED1[120]; 1181 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Configuration of GPIO pins. */ 1182 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1183 1184 1185 /** @} */ /* End of group Device_Peripheral_peripherals */ 1186 1187 1188 /* =========================================================================================================================== */ 1189 /* ================ Device Specific Peripheral Address Map ================ */ 1190 /* =========================================================================================================================== */ 1191 1192 1193 /** @addtogroup Device_Peripheral_peripheralAddr 1194 * @{ 1195 */ 1196 1197 #define NRF_POWER_BASE 0x40000000UL 1198 #define NRF_CLOCK_BASE 0x40000000UL 1199 #define NRF_MPU_BASE 0x40000000UL 1200 #define NRF_RADIO_BASE 0x40001000UL 1201 #define NRF_UART0_BASE 0x40002000UL 1202 #define NRF_SPI0_BASE 0x40003000UL 1203 #define NRF_TWI0_BASE 0x40003000UL 1204 #define NRF_SPI1_BASE 0x40004000UL 1205 #define NRF_TWI1_BASE 0x40004000UL 1206 #define NRF_SPIS1_BASE 0x40004000UL 1207 #define NRF_GPIOTE_BASE 0x40006000UL 1208 #define NRF_ADC_BASE 0x40007000UL 1209 #define NRF_TIMER0_BASE 0x40008000UL 1210 #define NRF_TIMER1_BASE 0x40009000UL 1211 #define NRF_TIMER2_BASE 0x4000A000UL 1212 #define NRF_RTC0_BASE 0x4000B000UL 1213 #define NRF_TEMP_BASE 0x4000C000UL 1214 #define NRF_RNG_BASE 0x4000D000UL 1215 #define NRF_ECB_BASE 0x4000E000UL 1216 #define NRF_AAR_BASE 0x4000F000UL 1217 #define NRF_CCM_BASE 0x4000F000UL 1218 #define NRF_WDT_BASE 0x40010000UL 1219 #define NRF_RTC1_BASE 0x40011000UL 1220 #define NRF_QDEC_BASE 0x40012000UL 1221 #define NRF_LPCOMP_BASE 0x40013000UL 1222 #define NRF_SWI_BASE 0x40014000UL 1223 #define NRF_NVMC_BASE 0x4001E000UL 1224 #define NRF_PPI_BASE 0x4001F000UL 1225 #define NRF_FICR_BASE 0x10000000UL 1226 #define NRF_UICR_BASE 0x10001000UL 1227 #define NRF_GPIO_BASE 0x50000000UL 1228 1229 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1230 1231 1232 /* =========================================================================================================================== */ 1233 /* ================ Peripheral declaration ================ */ 1234 /* =========================================================================================================================== */ 1235 1236 1237 /** @addtogroup Device_Peripheral_declaration 1238 * @{ 1239 */ 1240 1241 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1242 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1243 #define NRF_MPU ((NRF_MPU_Type*) NRF_MPU_BASE) 1244 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1245 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 1246 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 1247 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 1248 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 1249 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 1250 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 1251 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1252 #define NRF_ADC ((NRF_ADC_Type*) NRF_ADC_BASE) 1253 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1254 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1255 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1256 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1257 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1258 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1259 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1260 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1261 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1262 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1263 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1264 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1265 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 1266 #define NRF_SWI ((NRF_SWI_Type*) NRF_SWI_BASE) 1267 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1268 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1269 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1270 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1271 #define NRF_GPIO ((NRF_GPIO_Type*) NRF_GPIO_BASE) 1272 1273 /** @} */ /* End of group Device_Peripheral_declaration */ 1274 1275 1276 /* ========================================= End of section using anonymous unions ========================================= */ 1277 #if defined (__CC_ARM) 1278 #pragma pop 1279 #elif defined (__ICCARM__) 1280 /* leave anonymous unions enabled */ 1281 #elif (__ARMCC_VERSION >= 6010050) 1282 #pragma clang diagnostic pop 1283 #elif defined (__GNUC__) 1284 /* anonymous unions are enabled by default */ 1285 #elif defined (__TMS470__) 1286 /* anonymous unions are enabled by default */ 1287 #elif defined (__TASKING__) 1288 #pragma warning restore 1289 #elif defined (__CSMC__) 1290 /* anonymous unions are enabled by default */ 1291 #endif 1292 1293 1294 #ifdef __cplusplus 1295 } 1296 #endif 1297 1298 #endif /* NRF51_H */ 1299 1300 1301 /** @} */ /* End of group nrf51 */ 1302 1303 /** @} */ /* End of group Nordic Semiconductor */ 1304